| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.2589520408 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.4059239300 |
| /workspace/coverage/default/1.prim_present_test.3527037046 |
| /workspace/coverage/default/10.prim_present_test.1537713152 |
| /workspace/coverage/default/12.prim_present_test.2511591926 |
| /workspace/coverage/default/13.prim_present_test.203907537 |
| /workspace/coverage/default/14.prim_present_test.3249301828 |
| /workspace/coverage/default/15.prim_present_test.2914371264 |
| /workspace/coverage/default/16.prim_present_test.775964314 |
| /workspace/coverage/default/17.prim_present_test.448031254 |
| /workspace/coverage/default/18.prim_present_test.2029288182 |
| /workspace/coverage/default/19.prim_present_test.480274964 |
| /workspace/coverage/default/2.prim_present_test.4160522165 |
| /workspace/coverage/default/20.prim_present_test.466707729 |
| /workspace/coverage/default/21.prim_present_test.1297544947 |
| /workspace/coverage/default/22.prim_present_test.3436172618 |
| /workspace/coverage/default/23.prim_present_test.3213514446 |
| /workspace/coverage/default/24.prim_present_test.4177795499 |
| /workspace/coverage/default/25.prim_present_test.1426015509 |
| /workspace/coverage/default/26.prim_present_test.2464450842 |
| /workspace/coverage/default/27.prim_present_test.1128242811 |
| /workspace/coverage/default/28.prim_present_test.2218291118 |
| /workspace/coverage/default/29.prim_present_test.2097532703 |
| /workspace/coverage/default/3.prim_present_test.2815390129 |
| /workspace/coverage/default/30.prim_present_test.4271934493 |
| /workspace/coverage/default/31.prim_present_test.1572978785 |
| /workspace/coverage/default/32.prim_present_test.1413314424 |
| /workspace/coverage/default/33.prim_present_test.1649606498 |
| /workspace/coverage/default/34.prim_present_test.2492906184 |
| /workspace/coverage/default/35.prim_present_test.4009070141 |
| /workspace/coverage/default/36.prim_present_test.3921018583 |
| /workspace/coverage/default/37.prim_present_test.2316209008 |
| /workspace/coverage/default/38.prim_present_test.3159484651 |
| /workspace/coverage/default/39.prim_present_test.2694861150 |
| /workspace/coverage/default/4.prim_present_test.541499605 |
| /workspace/coverage/default/40.prim_present_test.2052757480 |
| /workspace/coverage/default/41.prim_present_test.2300780725 |
| /workspace/coverage/default/42.prim_present_test.4146445383 |
| /workspace/coverage/default/43.prim_present_test.1506420475 |
| /workspace/coverage/default/44.prim_present_test.995999269 |
| /workspace/coverage/default/45.prim_present_test.1174270741 |
| /workspace/coverage/default/46.prim_present_test.3431551797 |
| /workspace/coverage/default/47.prim_present_test.3169615180 |
| /workspace/coverage/default/48.prim_present_test.866870790 |
| /workspace/coverage/default/49.prim_present_test.2439564972 |
| /workspace/coverage/default/5.prim_present_test.195376128 |
| /workspace/coverage/default/6.prim_present_test.2990419214 |
| /workspace/coverage/default/7.prim_present_test.3567433113 |
| /workspace/coverage/default/8.prim_present_test.4203217788 |
| /workspace/coverage/default/9.prim_present_test.844218611 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/39.prim_present_test.2694861150 | May 16 02:38:00 PM PDT 24 | May 16 02:39:48 PM PDT 24 | 14801880000 ps | ||
| T2 | /workspace/coverage/default/46.prim_present_test.3431551797 | May 16 02:38:00 PM PDT 24 | May 16 02:39:19 PM PDT 24 | 11063900000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.203907537 | May 16 02:37:58 PM PDT 24 | May 16 02:39:42 PM PDT 24 | 13841500000 ps | ||
| T4 | /workspace/coverage/default/2.prim_present_test.4160522165 | May 16 02:37:54 PM PDT 24 | May 16 02:38:36 PM PDT 24 | 5558920000 ps | ||
| T5 | /workspace/coverage/default/44.prim_present_test.995999269 | May 16 02:38:01 PM PDT 24 | May 16 02:39:30 PM PDT 24 | 12548800000 ps | ||
| T6 | /workspace/coverage/default/11.prim_present_test.2589520408 | May 16 02:37:58 PM PDT 24 | May 16 02:38:38 PM PDT 24 | 4395180000 ps | ||
| T7 | /workspace/coverage/default/28.prim_present_test.2218291118 | May 16 02:37:58 PM PDT 24 | May 16 02:39:18 PM PDT 24 | 14582400000 ps | ||
| T8 | /workspace/coverage/default/30.prim_present_test.4271934493 | May 16 02:38:01 PM PDT 24 | May 16 02:39:53 PM PDT 24 | 14421200000 ps | ||
| T9 | /workspace/coverage/default/8.prim_present_test.4203217788 | May 16 02:37:52 PM PDT 24 | May 16 02:39:03 PM PDT 24 | 8995580000 ps | ||
| T10 | /workspace/coverage/default/21.prim_present_test.1297544947 | May 16 02:38:01 PM PDT 24 | May 16 02:39:09 PM PDT 24 | 9282640000 ps | ||
| T11 | /workspace/coverage/default/16.prim_present_test.775964314 | May 16 02:38:01 PM PDT 24 | May 16 02:39:17 PM PDT 24 | 8642180000 ps | ||
| T12 | /workspace/coverage/default/7.prim_present_test.3567433113 | May 16 02:37:55 PM PDT 24 | May 16 02:38:48 PM PDT 24 | 6627800000 ps | ||
| T13 | /workspace/coverage/default/22.prim_present_test.3436172618 | May 16 02:37:59 PM PDT 24 | May 16 02:39:03 PM PDT 24 | 7559660000 ps | ||
| T14 | /workspace/coverage/default/1.prim_present_test.3527037046 | May 16 02:37:51 PM PDT 24 | May 16 02:39:02 PM PDT 24 | 10672060000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.2990419214 | May 16 02:37:54 PM PDT 24 | May 16 02:39:28 PM PDT 24 | 12521520000 ps | ||
| T16 | /workspace/coverage/default/32.prim_present_test.1413314424 | May 16 02:38:01 PM PDT 24 | May 16 02:38:44 PM PDT 24 | 5064160000 ps | ||
| T17 | /workspace/coverage/default/45.prim_present_test.1174270741 | May 16 02:38:01 PM PDT 24 | May 16 02:39:47 PM PDT 24 | 13219020000 ps | ||
| T18 | /workspace/coverage/default/10.prim_present_test.1537713152 | May 16 02:37:54 PM PDT 24 | May 16 02:38:53 PM PDT 24 | 7393500000 ps | ||
| T19 | /workspace/coverage/default/35.prim_present_test.4009070141 | May 16 02:38:00 PM PDT 24 | May 16 02:39:09 PM PDT 24 | 8299940000 ps | ||
| T20 | /workspace/coverage/default/33.prim_present_test.1649606498 | May 16 02:38:01 PM PDT 24 | May 16 02:38:57 PM PDT 24 | 6458540000 ps | ||
| T21 | /workspace/coverage/default/36.prim_present_test.3921018583 | May 16 02:38:05 PM PDT 24 | May 16 02:39:58 PM PDT 24 | 14837840000 ps | ||
| T22 | /workspace/coverage/default/34.prim_present_test.2492906184 | May 16 02:37:59 PM PDT 24 | May 16 02:39:43 PM PDT 24 | 13719980000 ps | ||
| T23 | /workspace/coverage/default/47.prim_present_test.3169615180 | May 16 02:38:08 PM PDT 24 | May 16 02:38:54 PM PDT 24 | 6366160000 ps | ||
| T24 | /workspace/coverage/default/15.prim_present_test.2914371264 | May 16 02:38:00 PM PDT 24 | May 16 02:38:26 PM PDT 24 | 3726820000 ps | ||
| T25 | /workspace/coverage/default/4.prim_present_test.541499605 | May 16 02:37:51 PM PDT 24 | May 16 02:39:36 PM PDT 24 | 11605780000 ps | ||
| T26 | /workspace/coverage/default/31.prim_present_test.1572978785 | May 16 02:37:59 PM PDT 24 | May 16 02:39:34 PM PDT 24 | 13977900000 ps | ||
| T27 | /workspace/coverage/default/25.prim_present_test.1426015509 | May 16 02:38:02 PM PDT 24 | May 16 02:38:52 PM PDT 24 | 6626560000 ps | ||
| T28 | /workspace/coverage/default/17.prim_present_test.448031254 | May 16 02:38:01 PM PDT 24 | May 16 02:38:27 PM PDT 24 | 3310180000 ps | ||
| T29 | /workspace/coverage/default/41.prim_present_test.2300780725 | May 16 02:38:02 PM PDT 24 | May 16 02:38:34 PM PDT 24 | 3925840000 ps | ||
| T30 | /workspace/coverage/default/19.prim_present_test.480274964 | May 16 02:38:10 PM PDT 24 | May 16 02:39:16 PM PDT 24 | 8600020000 ps | ||
| T31 | /workspace/coverage/default/26.prim_present_test.2464450842 | May 16 02:37:59 PM PDT 24 | May 16 02:38:56 PM PDT 24 | 7296780000 ps | ||
| T32 | /workspace/coverage/default/37.prim_present_test.2316209008 | May 16 02:37:58 PM PDT 24 | May 16 02:40:08 PM PDT 24 | 15183800000 ps | ||
| T33 | /workspace/coverage/default/23.prim_present_test.3213514446 | May 16 02:37:59 PM PDT 24 | May 16 02:38:31 PM PDT 24 | 3410000000 ps | ||
| T34 | /workspace/coverage/default/9.prim_present_test.844218611 | May 16 02:37:54 PM PDT 24 | May 16 02:38:37 PM PDT 24 | 5357420000 ps | ||
| T35 | /workspace/coverage/default/27.prim_present_test.1128242811 | May 16 02:37:58 PM PDT 24 | May 16 02:38:54 PM PDT 24 | 7886400000 ps | ||
| T36 | /workspace/coverage/default/0.prim_present_test.4059239300 | May 16 02:37:51 PM PDT 24 | May 16 02:39:18 PM PDT 24 | 14583020000 ps | ||
| T37 | /workspace/coverage/default/14.prim_present_test.3249301828 | May 16 02:38:02 PM PDT 24 | May 16 02:39:10 PM PDT 24 | 8883360000 ps | ||
| T38 | /workspace/coverage/default/49.prim_present_test.2439564972 | May 16 02:38:09 PM PDT 24 | May 16 02:40:11 PM PDT 24 | 14587980000 ps | ||
| T39 | /workspace/coverage/default/24.prim_present_test.4177795499 | May 16 02:38:00 PM PDT 24 | May 16 02:38:46 PM PDT 24 | 5774060000 ps | ||
| T40 | /workspace/coverage/default/38.prim_present_test.3159484651 | May 16 02:38:01 PM PDT 24 | May 16 02:39:54 PM PDT 24 | 13892960000 ps | ||
| T41 | /workspace/coverage/default/18.prim_present_test.2029288182 | May 16 02:38:04 PM PDT 24 | May 16 02:39:27 PM PDT 24 | 10710500000 ps | ||
| T42 | /workspace/coverage/default/48.prim_present_test.866870790 | May 16 02:38:09 PM PDT 24 | May 16 02:39:32 PM PDT 24 | 10575340000 ps | ||
| T43 | /workspace/coverage/default/12.prim_present_test.2511591926 | May 16 02:38:03 PM PDT 24 | May 16 02:38:48 PM PDT 24 | 5922860000 ps | ||
| T44 | /workspace/coverage/default/20.prim_present_test.466707729 | May 16 02:37:59 PM PDT 24 | May 16 02:39:13 PM PDT 24 | 8055040000 ps | ||
| T45 | /workspace/coverage/default/3.prim_present_test.2815390129 | May 16 02:37:52 PM PDT 24 | May 16 02:39:20 PM PDT 24 | 11416680000 ps | ||
| T46 | /workspace/coverage/default/40.prim_present_test.2052757480 | May 16 02:38:01 PM PDT 24 | May 16 02:39:24 PM PDT 24 | 10842560000 ps | ||
| T47 | /workspace/coverage/default/29.prim_present_test.2097532703 | May 16 02:38:00 PM PDT 24 | May 16 02:38:40 PM PDT 24 | 4652480000 ps | ||
| T48 | /workspace/coverage/default/42.prim_present_test.4146445383 | May 16 02:38:01 PM PDT 24 | May 16 02:40:05 PM PDT 24 | 15416300000 ps | ||
| T49 | /workspace/coverage/default/5.prim_present_test.195376128 | May 16 02:37:53 PM PDT 24 | May 16 02:39:35 PM PDT 24 | 14644400000 ps | ||
| T50 | /workspace/coverage/default/43.prim_present_test.1506420475 | May 16 02:38:05 PM PDT 24 | May 16 02:38:56 PM PDT 24 | 6342600000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.2589520408 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4395180000 ps |
| CPU time | 19.64 seconds |
| Started | May 16 02:37:58 PM PDT 24 |
| Finished | May 16 02:38:38 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-3b1a95d8-bbd7-4d42-9b58-c09697b3c72a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589520408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2589520408 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.4059239300 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14583020000 ps |
| CPU time | 44.78 seconds |
| Started | May 16 02:37:51 PM PDT 24 |
| Finished | May 16 02:39:18 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-53b151fc-a660-4f4e-972e-ee2c84cbf3fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059239300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.4059239300 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3527037046 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10672060000 ps |
| CPU time | 36.24 seconds |
| Started | May 16 02:37:51 PM PDT 24 |
| Finished | May 16 02:39:02 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-cb78605c-39e1-45e2-b35d-f1d804e64122 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527037046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3527037046 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1537713152 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7393500000 ps |
| CPU time | 28.98 seconds |
| Started | May 16 02:37:54 PM PDT 24 |
| Finished | May 16 02:38:53 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-7484a582-05d2-434e-83d8-49cc0ea46c09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537713152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1537713152 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2511591926 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5922860000 ps |
| CPU time | 20.74 seconds |
| Started | May 16 02:38:03 PM PDT 24 |
| Finished | May 16 02:38:48 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-8c293308-8569-4c0f-a044-28899097b046 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511591926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2511591926 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.203907537 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13841500000 ps |
| CPU time | 53.32 seconds |
| Started | May 16 02:37:58 PM PDT 24 |
| Finished | May 16 02:39:42 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-d1ee38c1-be7c-43d7-94de-1e31b665db86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203907537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.203907537 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3249301828 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8883360000 ps |
| CPU time | 33.59 seconds |
| Started | May 16 02:38:02 PM PDT 24 |
| Finished | May 16 02:39:10 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-f65e6335-2e87-4e5f-8d98-0e80e4c4acb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249301828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3249301828 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2914371264 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3726820000 ps |
| CPU time | 12.25 seconds |
| Started | May 16 02:38:00 PM PDT 24 |
| Finished | May 16 02:38:26 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-60ed8198-8fb2-458f-88e0-297670e5b857 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914371264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2914371264 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.775964314 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8642180000 ps |
| CPU time | 36.09 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:39:17 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-6052c694-7c03-405c-8ca1-cca3334b08cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775964314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.775964314 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.448031254 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3310180000 ps |
| CPU time | 11.72 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:38:27 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-486cd889-933f-4d57-97be-adfdfc4ff992 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448031254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.448031254 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2029288182 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10710500000 ps |
| CPU time | 40.3 seconds |
| Started | May 16 02:38:04 PM PDT 24 |
| Finished | May 16 02:39:27 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-f6e1b845-9f57-4a8a-ae85-c012e721cffb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029288182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2029288182 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.480274964 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8600020000 ps |
| CPU time | 31.74 seconds |
| Started | May 16 02:38:10 PM PDT 24 |
| Finished | May 16 02:39:16 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-aef48e47-93cd-4f2c-ba25-77960b242149 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480274964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.480274964 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4160522165 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5558920000 ps |
| CPU time | 20.25 seconds |
| Started | May 16 02:37:54 PM PDT 24 |
| Finished | May 16 02:38:36 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-d9cad9f7-d3f4-4bd0-a53f-1883baf78205 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160522165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4160522165 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.466707729 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8055040000 ps |
| CPU time | 38.02 seconds |
| Started | May 16 02:37:59 PM PDT 24 |
| Finished | May 16 02:39:13 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-ac3ac80a-25ef-440a-a75c-26c7c446e46a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466707729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.466707729 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1297544947 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9282640000 ps |
| CPU time | 33.85 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:39:09 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-66a7edd2-42e9-4370-8845-3040b634b2c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297544947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1297544947 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3436172618 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7559660000 ps |
| CPU time | 32.16 seconds |
| Started | May 16 02:37:59 PM PDT 24 |
| Finished | May 16 02:39:03 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-ed3fa416-ef0f-4188-b3ac-f898bb923158 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436172618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3436172618 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3213514446 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3410000000 ps |
| CPU time | 14.11 seconds |
| Started | May 16 02:37:59 PM PDT 24 |
| Finished | May 16 02:38:31 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-b0cd4ff4-7b01-4970-897d-e6c876474368 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213514446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3213514446 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4177795499 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5774060000 ps |
| CPU time | 22.32 seconds |
| Started | May 16 02:38:00 PM PDT 24 |
| Finished | May 16 02:38:46 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-e67c698c-6a36-44cf-8727-95795623a9cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177795499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4177795499 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1426015509 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6626560000 ps |
| CPU time | 24.26 seconds |
| Started | May 16 02:38:02 PM PDT 24 |
| Finished | May 16 02:38:52 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-968e1ab0-2d05-489a-b42a-502d979310be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426015509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1426015509 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2464450842 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7296780000 ps |
| CPU time | 28.39 seconds |
| Started | May 16 02:37:59 PM PDT 24 |
| Finished | May 16 02:38:56 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-b8878843-64e3-409d-9693-de85cd6fd0f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464450842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2464450842 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1128242811 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7886400000 ps |
| CPU time | 29.1 seconds |
| Started | May 16 02:37:58 PM PDT 24 |
| Finished | May 16 02:38:54 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-d0af8e34-47e8-43c5-98d3-f36834881af0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128242811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1128242811 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2218291118 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14582400000 ps |
| CPU time | 42.3 seconds |
| Started | May 16 02:37:58 PM PDT 24 |
| Finished | May 16 02:39:18 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-042ec4a7-83ba-49b2-9e6f-36780f678d30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2218291118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2218291118 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2097532703 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4652480000 ps |
| CPU time | 18.71 seconds |
| Started | May 16 02:38:00 PM PDT 24 |
| Finished | May 16 02:38:40 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-3f745997-9cf4-47ab-b334-c7036e2aead1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097532703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2097532703 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2815390129 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11416680000 ps |
| CPU time | 43.9 seconds |
| Started | May 16 02:37:52 PM PDT 24 |
| Finished | May 16 02:39:20 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-13128d1e-fce8-4574-b943-5996020a695d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815390129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2815390129 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4271934493 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14421200000 ps |
| CPU time | 55.8 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:39:53 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-eacd9551-a525-4a3a-be84-095f3acac0e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271934493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4271934493 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1572978785 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13977900000 ps |
| CPU time | 48.6 seconds |
| Started | May 16 02:37:59 PM PDT 24 |
| Finished | May 16 02:39:34 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-338adba1-2873-421c-ab1a-402a3a46406a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1572978785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1572978785 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1413314424 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5064160000 ps |
| CPU time | 20.53 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:38:44 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-24f3714f-1910-4f04-bcd2-a127936eddb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413314424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1413314424 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1649606498 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6458540000 ps |
| CPU time | 25.28 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:38:57 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-63ee9735-8b9c-466a-b06b-515d1ebfc7a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649606498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1649606498 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2492906184 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13719980000 ps |
| CPU time | 52.99 seconds |
| Started | May 16 02:37:59 PM PDT 24 |
| Finished | May 16 02:39:43 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-61439de2-9b34-4e0f-9de9-16be7a28d8d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492906184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2492906184 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4009070141 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8299940000 ps |
| CPU time | 33.32 seconds |
| Started | May 16 02:38:00 PM PDT 24 |
| Finished | May 16 02:39:09 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-67a89d68-8e3b-432f-ade6-27ec85a8df09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009070141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4009070141 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3921018583 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14837840000 ps |
| CPU time | 56.72 seconds |
| Started | May 16 02:38:05 PM PDT 24 |
| Finished | May 16 02:39:58 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-f0a54b5b-a95b-4072-b273-ade96441fe98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921018583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3921018583 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2316209008 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 15183800000 ps |
| CPU time | 62.85 seconds |
| Started | May 16 02:37:58 PM PDT 24 |
| Finished | May 16 02:40:08 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-697c7a48-418d-4375-a407-f384c1e405d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2316209008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2316209008 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3159484651 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13892960000 ps |
| CPU time | 57.85 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:39:54 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-76f563cb-d482-49dd-a9a1-9ce512641a42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159484651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3159484651 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2694861150 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14801880000 ps |
| CPU time | 55.64 seconds |
| Started | May 16 02:38:00 PM PDT 24 |
| Finished | May 16 02:39:48 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-944897d5-3ca4-4383-b920-541f38ba40a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694861150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2694861150 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.541499605 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11605780000 ps |
| CPU time | 49.24 seconds |
| Started | May 16 02:37:51 PM PDT 24 |
| Finished | May 16 02:39:36 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-ed6df113-0ea8-457c-9ab1-4bcb391f8a1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541499605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.541499605 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2052757480 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10842560000 ps |
| CPU time | 41.39 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:39:24 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-6d83a073-7919-4eab-8cc2-6ef7bff3fb44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052757480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2052757480 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2300780725 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3925840000 ps |
| CPU time | 14.89 seconds |
| Started | May 16 02:38:02 PM PDT 24 |
| Finished | May 16 02:38:34 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-5b5e8603-9032-4867-9060-89b16f9b0fac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300780725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2300780725 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4146445383 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 15416300000 ps |
| CPU time | 60.73 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:40:05 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-57f08772-079f-4a5a-b655-a10a8d7caca4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146445383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4146445383 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1506420475 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6342600000 ps |
| CPU time | 24.48 seconds |
| Started | May 16 02:38:05 PM PDT 24 |
| Finished | May 16 02:38:56 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-e04172cb-6452-4106-88af-fa4f3422f0cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506420475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1506420475 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.995999269 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12548800000 ps |
| CPU time | 43.08 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:39:30 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-72dba7aa-b51b-495b-8f41-3aaf417c13dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=995999269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.995999269 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1174270741 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 13219020000 ps |
| CPU time | 52.71 seconds |
| Started | May 16 02:38:01 PM PDT 24 |
| Finished | May 16 02:39:47 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-97066431-1ba2-4c68-9dd2-3630080beaa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174270741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1174270741 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3431551797 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11063900000 ps |
| CPU time | 38.79 seconds |
| Started | May 16 02:38:00 PM PDT 24 |
| Finished | May 16 02:39:19 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-27046985-f062-4b3f-8347-8bc45b92f9e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431551797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3431551797 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3169615180 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6366160000 ps |
| CPU time | 21.83 seconds |
| Started | May 16 02:38:08 PM PDT 24 |
| Finished | May 16 02:38:54 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-075ac9e7-6216-480d-bdb3-ca3c7f014785 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3169615180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3169615180 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.866870790 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10575340000 ps |
| CPU time | 40.63 seconds |
| Started | May 16 02:38:09 PM PDT 24 |
| Finished | May 16 02:39:32 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-1dc0b1c2-c4f2-4815-9608-8308acd468e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866870790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.866870790 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2439564972 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14587980000 ps |
| CPU time | 60.87 seconds |
| Started | May 16 02:38:09 PM PDT 24 |
| Finished | May 16 02:40:11 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-ddec7ce8-cc61-4734-9b18-33b19a240991 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439564972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2439564972 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.195376128 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14644400000 ps |
| CPU time | 51.5 seconds |
| Started | May 16 02:37:53 PM PDT 24 |
| Finished | May 16 02:39:35 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-84d50bbe-ba01-4fc9-9074-4e1805204cde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195376128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.195376128 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2990419214 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12521520000 ps |
| CPU time | 46.95 seconds |
| Started | May 16 02:37:54 PM PDT 24 |
| Finished | May 16 02:39:28 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-5c38cb09-aa4d-488c-a8a9-77d9434fb734 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990419214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2990419214 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3567433113 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6627800000 ps |
| CPU time | 25.68 seconds |
| Started | May 16 02:37:55 PM PDT 24 |
| Finished | May 16 02:38:48 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-da6d65b7-44e5-473f-9ae6-e690fc1fa8bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567433113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3567433113 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4203217788 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8995580000 ps |
| CPU time | 34.81 seconds |
| Started | May 16 02:37:52 PM PDT 24 |
| Finished | May 16 02:39:03 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-a1ab3def-75f1-4386-9eff-1ae546b40ea0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4203217788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4203217788 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.844218611 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5357420000 ps |
| CPU time | 20.5 seconds |
| Started | May 16 02:37:54 PM PDT 24 |
| Finished | May 16 02:38:37 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-705157c8-a9d5-4a4c-8660-559f2c5e4845 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844218611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.844218611 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |