| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3699825771 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.3750104990 |
| /workspace/coverage/default/10.prim_present_test.3081957237 |
| /workspace/coverage/default/11.prim_present_test.3763075314 |
| /workspace/coverage/default/12.prim_present_test.1095625285 |
| /workspace/coverage/default/13.prim_present_test.3462256961 |
| /workspace/coverage/default/14.prim_present_test.2485767131 |
| /workspace/coverage/default/15.prim_present_test.1914342408 |
| /workspace/coverage/default/16.prim_present_test.356298043 |
| /workspace/coverage/default/17.prim_present_test.2987977944 |
| /workspace/coverage/default/18.prim_present_test.495480786 |
| /workspace/coverage/default/19.prim_present_test.928447359 |
| /workspace/coverage/default/2.prim_present_test.1803484683 |
| /workspace/coverage/default/20.prim_present_test.42910028 |
| /workspace/coverage/default/21.prim_present_test.3628270539 |
| /workspace/coverage/default/22.prim_present_test.1135933478 |
| /workspace/coverage/default/23.prim_present_test.306947112 |
| /workspace/coverage/default/24.prim_present_test.1188205506 |
| /workspace/coverage/default/25.prim_present_test.3825318122 |
| /workspace/coverage/default/26.prim_present_test.3073045230 |
| /workspace/coverage/default/27.prim_present_test.1052632289 |
| /workspace/coverage/default/28.prim_present_test.3452856847 |
| /workspace/coverage/default/29.prim_present_test.3063059011 |
| /workspace/coverage/default/3.prim_present_test.2889177247 |
| /workspace/coverage/default/30.prim_present_test.33103162 |
| /workspace/coverage/default/31.prim_present_test.1868490109 |
| /workspace/coverage/default/32.prim_present_test.2717334246 |
| /workspace/coverage/default/33.prim_present_test.1824635980 |
| /workspace/coverage/default/34.prim_present_test.4223209030 |
| /workspace/coverage/default/35.prim_present_test.1591561173 |
| /workspace/coverage/default/36.prim_present_test.3218969694 |
| /workspace/coverage/default/37.prim_present_test.1376543244 |
| /workspace/coverage/default/38.prim_present_test.90378187 |
| /workspace/coverage/default/39.prim_present_test.844205928 |
| /workspace/coverage/default/4.prim_present_test.1707909195 |
| /workspace/coverage/default/40.prim_present_test.1106004082 |
| /workspace/coverage/default/41.prim_present_test.625851596 |
| /workspace/coverage/default/42.prim_present_test.2537007016 |
| /workspace/coverage/default/43.prim_present_test.1281350868 |
| /workspace/coverage/default/44.prim_present_test.1859578914 |
| /workspace/coverage/default/45.prim_present_test.2248778288 |
| /workspace/coverage/default/46.prim_present_test.2154208469 |
| /workspace/coverage/default/47.prim_present_test.4085293429 |
| /workspace/coverage/default/48.prim_present_test.2377305967 |
| /workspace/coverage/default/49.prim_present_test.4040527643 |
| /workspace/coverage/default/5.prim_present_test.2424458473 |
| /workspace/coverage/default/6.prim_present_test.1476011401 |
| /workspace/coverage/default/7.prim_present_test.3793415497 |
| /workspace/coverage/default/8.prim_present_test.1283277121 |
| /workspace/coverage/default/9.prim_present_test.2938558315 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_present_test.1803484683 | May 19 01:25:32 PM PDT 24 | May 19 01:26:43 PM PDT 24 | 10373220000 ps | ||
| T2 | /workspace/coverage/default/40.prim_present_test.1106004082 | May 19 01:25:36 PM PDT 24 | May 19 01:26:09 PM PDT 24 | 4921560000 ps | ||
| T3 | /workspace/coverage/default/27.prim_present_test.1052632289 | May 19 01:25:38 PM PDT 24 | May 19 01:26:28 PM PDT 24 | 6865260000 ps | ||
| T4 | /workspace/coverage/default/16.prim_present_test.356298043 | May 19 01:25:31 PM PDT 24 | May 19 01:26:54 PM PDT 24 | 11714280000 ps | ||
| T5 | /workspace/coverage/default/23.prim_present_test.306947112 | May 19 01:25:35 PM PDT 24 | May 19 01:26:28 PM PDT 24 | 6455440000 ps | ||
| T6 | /workspace/coverage/default/28.prim_present_test.3452856847 | May 19 01:25:35 PM PDT 24 | May 19 01:27:14 PM PDT 24 | 13961160000 ps | ||
| T7 | /workspace/coverage/default/0.prim_present_test.3699825771 | May 19 01:25:31 PM PDT 24 | May 19 01:27:18 PM PDT 24 | 15440480000 ps | ||
| T8 | /workspace/coverage/default/3.prim_present_test.2889177247 | May 19 01:25:34 PM PDT 24 | May 19 01:26:27 PM PDT 24 | 6333300000 ps | ||
| T9 | /workspace/coverage/default/41.prim_present_test.625851596 | May 19 01:25:36 PM PDT 24 | May 19 01:26:45 PM PDT 24 | 9078040000 ps | ||
| T10 | /workspace/coverage/default/46.prim_present_test.2154208469 | May 19 01:25:35 PM PDT 24 | May 19 01:27:21 PM PDT 24 | 12709380000 ps | ||
| T11 | /workspace/coverage/default/45.prim_present_test.2248778288 | May 19 01:25:36 PM PDT 24 | May 19 01:26:42 PM PDT 24 | 8952800000 ps | ||
| T12 | /workspace/coverage/default/37.prim_present_test.1376543244 | May 19 01:25:37 PM PDT 24 | May 19 01:26:58 PM PDT 24 | 12248100000 ps | ||
| T13 | /workspace/coverage/default/36.prim_present_test.3218969694 | May 19 01:25:36 PM PDT 24 | May 19 01:26:56 PM PDT 24 | 10497840000 ps | ||
| T14 | /workspace/coverage/default/38.prim_present_test.90378187 | May 19 01:25:39 PM PDT 24 | May 19 01:26:54 PM PDT 24 | 11946160000 ps | ||
| T15 | /workspace/coverage/default/48.prim_present_test.2377305967 | May 19 01:25:37 PM PDT 24 | May 19 01:27:15 PM PDT 24 | 12944360000 ps | ||
| T16 | /workspace/coverage/default/30.prim_present_test.33103162 | May 19 01:25:36 PM PDT 24 | May 19 01:26:43 PM PDT 24 | 11536960000 ps | ||
| T17 | /workspace/coverage/default/42.prim_present_test.2537007016 | May 19 01:25:37 PM PDT 24 | May 19 01:27:22 PM PDT 24 | 14043620000 ps | ||
| T18 | /workspace/coverage/default/8.prim_present_test.1283277121 | May 19 01:25:37 PM PDT 24 | May 19 01:25:59 PM PDT 24 | 3323820000 ps | ||
| T19 | /workspace/coverage/default/12.prim_present_test.1095625285 | May 19 01:25:30 PM PDT 24 | May 19 01:27:07 PM PDT 24 | 14733060000 ps | ||
| T20 | /workspace/coverage/default/1.prim_present_test.3750104990 | May 19 01:25:33 PM PDT 24 | May 19 01:26:26 PM PDT 24 | 7346380000 ps | ||
| T21 | /workspace/coverage/default/10.prim_present_test.3081957237 | May 19 01:25:33 PM PDT 24 | May 19 01:25:59 PM PDT 24 | 3566860000 ps | ||
| T22 | /workspace/coverage/default/29.prim_present_test.3063059011 | May 19 01:25:37 PM PDT 24 | May 19 01:26:17 PM PDT 24 | 5785840000 ps | ||
| T23 | /workspace/coverage/default/39.prim_present_test.844205928 | May 19 01:25:35 PM PDT 24 | May 19 01:26:45 PM PDT 24 | 9691220000 ps | ||
| T24 | /workspace/coverage/default/32.prim_present_test.2717334246 | May 19 01:25:38 PM PDT 24 | May 19 01:27:26 PM PDT 24 | 13810500000 ps | ||
| T25 | /workspace/coverage/default/26.prim_present_test.3073045230 | May 19 01:25:36 PM PDT 24 | May 19 01:26:32 PM PDT 24 | 9288840000 ps | ||
| T26 | /workspace/coverage/default/22.prim_present_test.1135933478 | May 19 01:25:32 PM PDT 24 | May 19 01:26:48 PM PDT 24 | 9412220000 ps | ||
| T27 | /workspace/coverage/default/9.prim_present_test.2938558315 | May 19 01:25:32 PM PDT 24 | May 19 01:27:18 PM PDT 24 | 14603480000 ps | ||
| T28 | /workspace/coverage/default/6.prim_present_test.1476011401 | May 19 01:25:32 PM PDT 24 | May 19 01:26:14 PM PDT 24 | 6000360000 ps | ||
| T29 | /workspace/coverage/default/34.prim_present_test.4223209030 | May 19 01:25:40 PM PDT 24 | May 19 01:27:24 PM PDT 24 | 14364780000 ps | ||
| T30 | /workspace/coverage/default/4.prim_present_test.1707909195 | May 19 01:25:33 PM PDT 24 | May 19 01:26:15 PM PDT 24 | 5638900000 ps | ||
| T31 | /workspace/coverage/default/49.prim_present_test.4040527643 | May 19 01:25:41 PM PDT 24 | May 19 01:26:15 PM PDT 24 | 4581800000 ps | ||
| T32 | /workspace/coverage/default/24.prim_present_test.1188205506 | May 19 01:25:31 PM PDT 24 | May 19 01:25:54 PM PDT 24 | 3295300000 ps | ||
| T33 | /workspace/coverage/default/5.prim_present_test.2424458473 | May 19 01:25:31 PM PDT 24 | May 19 01:26:20 PM PDT 24 | 7826880000 ps | ||
| T34 | /workspace/coverage/default/14.prim_present_test.2485767131 | May 19 01:25:33 PM PDT 24 | May 19 01:26:27 PM PDT 24 | 7451160000 ps | ||
| T35 | /workspace/coverage/default/44.prim_present_test.1859578914 | May 19 01:25:35 PM PDT 24 | May 19 01:26:14 PM PDT 24 | 5472740000 ps | ||
| T36 | /workspace/coverage/default/17.prim_present_test.2987977944 | May 19 01:25:33 PM PDT 24 | May 19 01:27:05 PM PDT 24 | 13171280000 ps | ||
| T37 | /workspace/coverage/default/21.prim_present_test.3628270539 | May 19 01:25:37 PM PDT 24 | May 19 01:27:27 PM PDT 24 | 15477060000 ps | ||
| T38 | /workspace/coverage/default/33.prim_present_test.1824635980 | May 19 01:25:38 PM PDT 24 | May 19 01:26:22 PM PDT 24 | 7865320000 ps | ||
| T39 | /workspace/coverage/default/11.prim_present_test.3763075314 | May 19 01:25:31 PM PDT 24 | May 19 01:26:08 PM PDT 24 | 5132360000 ps | ||
| T40 | /workspace/coverage/default/35.prim_present_test.1591561173 | May 19 01:25:36 PM PDT 24 | May 19 01:26:17 PM PDT 24 | 6539140000 ps | ||
| T41 | /workspace/coverage/default/20.prim_present_test.42910028 | May 19 01:25:35 PM PDT 24 | May 19 01:27:31 PM PDT 24 | 14857680000 ps | ||
| T42 | /workspace/coverage/default/31.prim_present_test.1868490109 | May 19 01:25:37 PM PDT 24 | May 19 01:26:39 PM PDT 24 | 10504660000 ps | ||
| T43 | /workspace/coverage/default/25.prim_present_test.3825318122 | May 19 01:25:35 PM PDT 24 | May 19 01:27:32 PM PDT 24 | 15374140000 ps | ||
| T44 | /workspace/coverage/default/19.prim_present_test.928447359 | May 19 01:25:31 PM PDT 24 | May 19 01:26:37 PM PDT 24 | 8549180000 ps | ||
| T45 | /workspace/coverage/default/13.prim_present_test.3462256961 | May 19 01:25:33 PM PDT 24 | May 19 01:26:05 PM PDT 24 | 4044260000 ps | ||
| T46 | /workspace/coverage/default/43.prim_present_test.1281350868 | May 19 01:25:37 PM PDT 24 | May 19 01:26:47 PM PDT 24 | 9061920000 ps | ||
| T47 | /workspace/coverage/default/18.prim_present_test.495480786 | May 19 01:25:30 PM PDT 24 | May 19 01:26:53 PM PDT 24 | 12708140000 ps | ||
| T48 | /workspace/coverage/default/47.prim_present_test.4085293429 | May 19 01:25:36 PM PDT 24 | May 19 01:26:24 PM PDT 24 | 5773440000 ps | ||
| T49 | /workspace/coverage/default/15.prim_present_test.1914342408 | May 19 01:25:31 PM PDT 24 | May 19 01:26:18 PM PDT 24 | 6048100000 ps | ||
| T50 | /workspace/coverage/default/7.prim_present_test.3793415497 | May 19 01:25:32 PM PDT 24 | May 19 01:25:57 PM PDT 24 | 4059140000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3699825771 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15440480000 ps |
| CPU time | 55.48 seconds |
| Started | May 19 01:25:31 PM PDT 24 |
| Finished | May 19 01:27:18 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-c284169b-7b41-4fab-8e3e-7f67f4c30dbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699825771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3699825771 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3750104990 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7346380000 ps |
| CPU time | 27.45 seconds |
| Started | May 19 01:25:33 PM PDT 24 |
| Finished | May 19 01:26:26 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-11358802-13b4-481b-8b64-2d547588f08c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750104990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3750104990 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3081957237 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3566860000 ps |
| CPU time | 13.18 seconds |
| Started | May 19 01:25:33 PM PDT 24 |
| Finished | May 19 01:25:59 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-b0f33aa0-5b75-40a3-a350-2b44a6820aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081957237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3081957237 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3763075314 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5132360000 ps |
| CPU time | 19.09 seconds |
| Started | May 19 01:25:31 PM PDT 24 |
| Finished | May 19 01:26:08 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-e6e86e04-633b-49dd-a08b-4d1f80c936af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763075314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3763075314 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1095625285 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14733060000 ps |
| CPU time | 51.5 seconds |
| Started | May 19 01:25:30 PM PDT 24 |
| Finished | May 19 01:27:07 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-525163be-e2ff-4e35-aa02-02fcdc9e796f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095625285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1095625285 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3462256961 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4044260000 ps |
| CPU time | 15.78 seconds |
| Started | May 19 01:25:33 PM PDT 24 |
| Finished | May 19 01:26:05 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-752a75a6-a7bc-44e8-936b-5e43048cfb6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462256961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3462256961 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2485767131 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7451160000 ps |
| CPU time | 27.54 seconds |
| Started | May 19 01:25:33 PM PDT 24 |
| Finished | May 19 01:26:27 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-bd60732f-0654-433c-9c3b-18c5357c2963 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485767131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2485767131 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1914342408 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6048100000 ps |
| CPU time | 24.27 seconds |
| Started | May 19 01:25:31 PM PDT 24 |
| Finished | May 19 01:26:18 PM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-08b65574-6a18-40e7-a7e1-d3c982c1393d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914342408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1914342408 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.356298043 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11714280000 ps |
| CPU time | 42.92 seconds |
| Started | May 19 01:25:31 PM PDT 24 |
| Finished | May 19 01:26:54 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-c26a86e5-01dd-4c64-b1af-9f7cfe47f0f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356298043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.356298043 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2987977944 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13171280000 ps |
| CPU time | 48.26 seconds |
| Started | May 19 01:25:33 PM PDT 24 |
| Finished | May 19 01:27:05 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-ac76aa72-0d3a-4f67-b20c-b5af64e433de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987977944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2987977944 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.495480786 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12708140000 ps |
| CPU time | 43.35 seconds |
| Started | May 19 01:25:30 PM PDT 24 |
| Finished | May 19 01:26:53 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-f23808a3-b6a5-4e78-a141-c88d80d13a7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495480786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.495480786 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.928447359 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8549180000 ps |
| CPU time | 33.8 seconds |
| Started | May 19 01:25:31 PM PDT 24 |
| Finished | May 19 01:26:37 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-d89cdeb5-1078-47a0-95f8-4019e5ca35b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928447359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.928447359 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1803484683 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10373220000 ps |
| CPU time | 35.93 seconds |
| Started | May 19 01:25:32 PM PDT 24 |
| Finished | May 19 01:26:43 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-a122e85c-3fca-475d-93d9-979c50cff80a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803484683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1803484683 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.42910028 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14857680000 ps |
| CPU time | 60.18 seconds |
| Started | May 19 01:25:35 PM PDT 24 |
| Finished | May 19 01:27:31 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-530b2dca-b928-4cfd-b53e-e80b6dfe50f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42910028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.42910028 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3628270539 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 15477060000 ps |
| CPU time | 56.76 seconds |
| Started | May 19 01:25:37 PM PDT 24 |
| Finished | May 19 01:27:27 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-09054b20-db0d-4598-acd6-bb96834149d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628270539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3628270539 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1135933478 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9412220000 ps |
| CPU time | 38.07 seconds |
| Started | May 19 01:25:32 PM PDT 24 |
| Finished | May 19 01:26:48 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-91387a3b-f7e0-4435-9421-9162defa22fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1135933478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1135933478 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.306947112 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 6455440000 ps |
| CPU time | 26.27 seconds |
| Started | May 19 01:25:35 PM PDT 24 |
| Finished | May 19 01:26:28 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-2679c567-038f-4b06-9b43-4ead8f78b111 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306947112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.306947112 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1188205506 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3295300000 ps |
| CPU time | 11.49 seconds |
| Started | May 19 01:25:31 PM PDT 24 |
| Finished | May 19 01:25:54 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-9b09ebc7-7705-41dc-ae68-4808b6468c29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188205506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1188205506 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3825318122 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15374140000 ps |
| CPU time | 60.95 seconds |
| Started | May 19 01:25:35 PM PDT 24 |
| Finished | May 19 01:27:32 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-ba1d9f40-0332-4110-92d2-a2446351ce02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825318122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3825318122 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3073045230 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9288840000 ps |
| CPU time | 29.9 seconds |
| Started | May 19 01:25:36 PM PDT 24 |
| Finished | May 19 01:26:32 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-c37c3bfd-9e15-4447-8595-8ed501d6c00b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073045230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3073045230 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1052632289 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6865260000 ps |
| CPU time | 25.66 seconds |
| Started | May 19 01:25:38 PM PDT 24 |
| Finished | May 19 01:26:28 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-7fa32c2e-2fe9-4723-bc8c-ffcdd777e396 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052632289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1052632289 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3452856847 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13961160000 ps |
| CPU time | 51.49 seconds |
| Started | May 19 01:25:35 PM PDT 24 |
| Finished | May 19 01:27:14 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-16ccc8c1-2113-4d24-ac38-9e25239bb9ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452856847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3452856847 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3063059011 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5785840000 ps |
| CPU time | 20.18 seconds |
| Started | May 19 01:25:37 PM PDT 24 |
| Finished | May 19 01:26:17 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-2c76524b-6220-47dd-a9d6-17570d600746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063059011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3063059011 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2889177247 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6333300000 ps |
| CPU time | 26.58 seconds |
| Started | May 19 01:25:34 PM PDT 24 |
| Finished | May 19 01:26:27 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-8c479626-df1a-49b4-a7ad-25a2e99e839d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889177247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2889177247 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.33103162 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11536960000 ps |
| CPU time | 35.39 seconds |
| Started | May 19 01:25:36 PM PDT 24 |
| Finished | May 19 01:26:43 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-c41695d8-a2f0-4089-b5f8-f0c619ecaf88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33103162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.33103162 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1868490109 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10504660000 ps |
| CPU time | 32.62 seconds |
| Started | May 19 01:25:37 PM PDT 24 |
| Finished | May 19 01:26:39 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-4d92e59e-bab3-44d3-9a6c-ca786f1b3f7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1868490109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1868490109 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2717334246 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 13810500000 ps |
| CPU time | 55.74 seconds |
| Started | May 19 01:25:38 PM PDT 24 |
| Finished | May 19 01:27:26 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-5cd87018-d0bb-4fb2-94e8-fb26dcf92d60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2717334246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2717334246 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1824635980 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7865320000 ps |
| CPU time | 23.04 seconds |
| Started | May 19 01:25:38 PM PDT 24 |
| Finished | May 19 01:26:22 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-4a31095d-ce58-4a1b-8003-c28ee1eb2715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824635980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1824635980 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.4223209030 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14364780000 ps |
| CPU time | 54.23 seconds |
| Started | May 19 01:25:40 PM PDT 24 |
| Finished | May 19 01:27:24 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-6898b2ec-47b7-4319-befd-da1ab110ad12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223209030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.4223209030 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1591561173 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6539140000 ps |
| CPU time | 21.86 seconds |
| Started | May 19 01:25:36 PM PDT 24 |
| Finished | May 19 01:26:17 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-933798bc-4053-4ea1-858a-a9262719289d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591561173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1591561173 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3218969694 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10497840000 ps |
| CPU time | 40.18 seconds |
| Started | May 19 01:25:36 PM PDT 24 |
| Finished | May 19 01:26:56 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-52acfca5-e10b-485b-9b20-c45e83b0dbb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218969694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3218969694 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1376543244 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12248100000 ps |
| CPU time | 41.97 seconds |
| Started | May 19 01:25:37 PM PDT 24 |
| Finished | May 19 01:26:58 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-2d33d4d8-6547-44c2-bd15-0ec001018424 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376543244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1376543244 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.90378187 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11946160000 ps |
| CPU time | 39.7 seconds |
| Started | May 19 01:25:39 PM PDT 24 |
| Finished | May 19 01:26:54 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-f58fc46a-c9ac-41a9-9888-86286ed27539 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90378187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.90378187 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.844205928 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9691220000 ps |
| CPU time | 36.14 seconds |
| Started | May 19 01:25:35 PM PDT 24 |
| Finished | May 19 01:26:45 PM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-8a2ed9a2-98a8-4557-9a4f-74abf40cf51d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844205928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.844205928 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1707909195 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5638900000 ps |
| CPU time | 20.85 seconds |
| Started | May 19 01:25:33 PM PDT 24 |
| Finished | May 19 01:26:15 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-29e5d238-4e6d-4588-9e54-89289548806d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707909195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1707909195 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1106004082 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4921560000 ps |
| CPU time | 16.88 seconds |
| Started | May 19 01:25:36 PM PDT 24 |
| Finished | May 19 01:26:09 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-6e6758e0-4caa-4105-900b-29f89bf032d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106004082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1106004082 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.625851596 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9078040000 ps |
| CPU time | 36.06 seconds |
| Started | May 19 01:25:36 PM PDT 24 |
| Finished | May 19 01:26:45 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-e64f1ec3-cbe8-4b2b-bb32-825606d4f0b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625851596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.625851596 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2537007016 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14043620000 ps |
| CPU time | 53.27 seconds |
| Started | May 19 01:25:37 PM PDT 24 |
| Finished | May 19 01:27:22 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-8622407f-6450-4ff7-a952-2785998ddc48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537007016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2537007016 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1281350868 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9061920000 ps |
| CPU time | 36.14 seconds |
| Started | May 19 01:25:37 PM PDT 24 |
| Finished | May 19 01:26:47 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-2c5befb8-6ce0-4845-828a-1a9f3c043ef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281350868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1281350868 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1859578914 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5472740000 ps |
| CPU time | 19.37 seconds |
| Started | May 19 01:25:35 PM PDT 24 |
| Finished | May 19 01:26:14 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-0d98348a-7b4c-4f1b-baff-6d73fb4ccba4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859578914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1859578914 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2248778288 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8952800000 ps |
| CPU time | 33.15 seconds |
| Started | May 19 01:25:36 PM PDT 24 |
| Finished | May 19 01:26:42 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-c097b10c-27ac-4354-9312-e55e7887fa87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248778288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2248778288 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2154208469 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12709380000 ps |
| CPU time | 51.53 seconds |
| Started | May 19 01:25:35 PM PDT 24 |
| Finished | May 19 01:27:21 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-bd9c90d9-bb2c-4f20-ba73-609cdad4c06e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154208469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2154208469 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4085293429 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5773440000 ps |
| CPU time | 24.1 seconds |
| Started | May 19 01:25:36 PM PDT 24 |
| Finished | May 19 01:26:24 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-a18635fd-fb13-4bb8-bff5-aaa9b3b3e696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4085293429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4085293429 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2377305967 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12944360000 ps |
| CPU time | 49.94 seconds |
| Started | May 19 01:25:37 PM PDT 24 |
| Finished | May 19 01:27:15 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-20b98e27-6e90-4910-9000-f9ce479e044f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377305967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2377305967 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.4040527643 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4581800000 ps |
| CPU time | 16.43 seconds |
| Started | May 19 01:25:41 PM PDT 24 |
| Finished | May 19 01:26:15 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-b0d24f0d-3270-412e-8c73-b2e4ad525fbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040527643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4040527643 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2424458473 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7826880000 ps |
| CPU time | 26.03 seconds |
| Started | May 19 01:25:31 PM PDT 24 |
| Finished | May 19 01:26:20 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-296fdf57-1e81-42e3-b880-ec9254d7cfd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424458473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2424458473 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1476011401 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6000360000 ps |
| CPU time | 21.91 seconds |
| Started | May 19 01:25:32 PM PDT 24 |
| Finished | May 19 01:26:14 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-e694854a-7023-47a4-a285-c94040112eda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476011401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1476011401 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3793415497 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4059140000 ps |
| CPU time | 13.02 seconds |
| Started | May 19 01:25:32 PM PDT 24 |
| Finished | May 19 01:25:57 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-787cf5ab-c6d8-4059-bf07-71d51dc76f4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3793415497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3793415497 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1283277121 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3323820000 ps |
| CPU time | 11.54 seconds |
| Started | May 19 01:25:37 PM PDT 24 |
| Finished | May 19 01:25:59 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-4f784b32-e664-4464-ae0c-3afda0d84e29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283277121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1283277121 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2938558315 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14603480000 ps |
| CPU time | 53.48 seconds |
| Started | May 19 01:25:32 PM PDT 24 |
| Finished | May 19 01:27:18 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-e34d6158-4cbd-4194-ba0f-9e70c04d8bbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2938558315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2938558315 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |