| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3512392247 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3213529739 |
| /workspace/coverage/default/1.prim_present_test.3912499441 |
| /workspace/coverage/default/11.prim_present_test.1636423850 |
| /workspace/coverage/default/12.prim_present_test.1751539890 |
| /workspace/coverage/default/13.prim_present_test.1946444367 |
| /workspace/coverage/default/14.prim_present_test.13694205 |
| /workspace/coverage/default/15.prim_present_test.2625246436 |
| /workspace/coverage/default/16.prim_present_test.1794364804 |
| /workspace/coverage/default/17.prim_present_test.1850792348 |
| /workspace/coverage/default/18.prim_present_test.3468755030 |
| /workspace/coverage/default/19.prim_present_test.888647025 |
| /workspace/coverage/default/2.prim_present_test.260698037 |
| /workspace/coverage/default/20.prim_present_test.800924968 |
| /workspace/coverage/default/21.prim_present_test.2245854949 |
| /workspace/coverage/default/22.prim_present_test.119799553 |
| /workspace/coverage/default/23.prim_present_test.1488507799 |
| /workspace/coverage/default/24.prim_present_test.1244953114 |
| /workspace/coverage/default/25.prim_present_test.1891452297 |
| /workspace/coverage/default/26.prim_present_test.2428189882 |
| /workspace/coverage/default/27.prim_present_test.1693452099 |
| /workspace/coverage/default/28.prim_present_test.2687476711 |
| /workspace/coverage/default/29.prim_present_test.1871826360 |
| /workspace/coverage/default/3.prim_present_test.4036545609 |
| /workspace/coverage/default/30.prim_present_test.3456924652 |
| /workspace/coverage/default/31.prim_present_test.981905167 |
| /workspace/coverage/default/32.prim_present_test.4086246996 |
| /workspace/coverage/default/33.prim_present_test.492001950 |
| /workspace/coverage/default/34.prim_present_test.3586725367 |
| /workspace/coverage/default/35.prim_present_test.441236376 |
| /workspace/coverage/default/36.prim_present_test.2820284831 |
| /workspace/coverage/default/37.prim_present_test.3148741635 |
| /workspace/coverage/default/38.prim_present_test.336227090 |
| /workspace/coverage/default/39.prim_present_test.1142887597 |
| /workspace/coverage/default/4.prim_present_test.4206972066 |
| /workspace/coverage/default/40.prim_present_test.497435325 |
| /workspace/coverage/default/41.prim_present_test.1457797018 |
| /workspace/coverage/default/42.prim_present_test.2174190132 |
| /workspace/coverage/default/43.prim_present_test.3496794522 |
| /workspace/coverage/default/44.prim_present_test.1426000133 |
| /workspace/coverage/default/45.prim_present_test.2032571523 |
| /workspace/coverage/default/46.prim_present_test.1252711447 |
| /workspace/coverage/default/47.prim_present_test.3235365570 |
| /workspace/coverage/default/48.prim_present_test.3229299642 |
| /workspace/coverage/default/49.prim_present_test.2391523245 |
| /workspace/coverage/default/5.prim_present_test.1450029297 |
| /workspace/coverage/default/6.prim_present_test.3277605279 |
| /workspace/coverage/default/7.prim_present_test.1584301181 |
| /workspace/coverage/default/8.prim_present_test.1479914486 |
| /workspace/coverage/default/9.prim_present_test.3489592182 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/28.prim_present_test.2687476711 | May 21 01:04:03 PM PDT 24 | May 21 01:04:42 PM PDT 24 | 5152200000 ps | ||
| T2 | /workspace/coverage/default/10.prim_present_test.3512392247 | May 21 01:03:55 PM PDT 24 | May 21 01:05:09 PM PDT 24 | 10510240000 ps | ||
| T3 | /workspace/coverage/default/41.prim_present_test.1457797018 | May 21 01:04:08 PM PDT 24 | May 21 01:04:35 PM PDT 24 | 4265600000 ps | ||
| T4 | /workspace/coverage/default/14.prim_present_test.13694205 | May 21 01:03:55 PM PDT 24 | May 21 01:05:30 PM PDT 24 | 12652340000 ps | ||
| T5 | /workspace/coverage/default/33.prim_present_test.492001950 | May 21 01:04:02 PM PDT 24 | May 21 01:05:38 PM PDT 24 | 12257400000 ps | ||
| T6 | /workspace/coverage/default/11.prim_present_test.1636423850 | May 21 01:03:57 PM PDT 24 | May 21 01:04:40 PM PDT 24 | 5473360000 ps | ||
| T7 | /workspace/coverage/default/40.prim_present_test.497435325 | May 21 01:04:08 PM PDT 24 | May 21 01:05:08 PM PDT 24 | 8589480000 ps | ||
| T8 | /workspace/coverage/default/44.prim_present_test.1426000133 | May 21 01:04:08 PM PDT 24 | May 21 01:05:49 PM PDT 24 | 14320140000 ps | ||
| T9 | /workspace/coverage/default/18.prim_present_test.3468755030 | May 21 01:04:04 PM PDT 24 | May 21 01:04:52 PM PDT 24 | 6673680000 ps | ||
| T10 | /workspace/coverage/default/35.prim_present_test.441236376 | May 21 01:04:13 PM PDT 24 | May 21 01:05:44 PM PDT 24 | 14948200000 ps | ||
| T11 | /workspace/coverage/default/15.prim_present_test.2625246436 | May 21 01:03:55 PM PDT 24 | May 21 01:04:58 PM PDT 24 | 10257900000 ps | ||
| T12 | /workspace/coverage/default/27.prim_present_test.1693452099 | May 21 01:04:03 PM PDT 24 | May 21 01:04:33 PM PDT 24 | 5458480000 ps | ||
| T13 | /workspace/coverage/default/13.prim_present_test.1946444367 | May 21 01:03:56 PM PDT 24 | May 21 01:04:55 PM PDT 24 | 7701020000 ps | ||
| T14 | /workspace/coverage/default/49.prim_present_test.2391523245 | May 21 01:04:10 PM PDT 24 | May 21 01:04:38 PM PDT 24 | 3334360000 ps | ||
| T15 | /workspace/coverage/default/4.prim_present_test.4206972066 | May 21 01:03:52 PM PDT 24 | May 21 01:05:17 PM PDT 24 | 15264400000 ps | ||
| T16 | /workspace/coverage/default/39.prim_present_test.1142887597 | May 21 01:04:08 PM PDT 24 | May 21 01:04:51 PM PDT 24 | 6309120000 ps | ||
| T17 | /workspace/coverage/default/26.prim_present_test.2428189882 | May 21 01:04:01 PM PDT 24 | May 21 01:04:55 PM PDT 24 | 8166020000 ps | ||
| T18 | /workspace/coverage/default/47.prim_present_test.3235365570 | May 21 01:04:08 PM PDT 24 | May 21 01:05:08 PM PDT 24 | 7753100000 ps | ||
| T19 | /workspace/coverage/default/0.prim_present_test.3213529739 | May 21 01:03:45 PM PDT 24 | May 21 01:05:18 PM PDT 24 | 13197320000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.1751539890 | May 21 01:03:59 PM PDT 24 | May 21 01:05:09 PM PDT 24 | 9589540000 ps | ||
| T21 | /workspace/coverage/default/20.prim_present_test.800924968 | May 21 01:04:04 PM PDT 24 | May 21 01:04:44 PM PDT 24 | 4982320000 ps | ||
| T22 | /workspace/coverage/default/6.prim_present_test.3277605279 | May 21 01:04:00 PM PDT 24 | May 21 01:05:08 PM PDT 24 | 9452520000 ps | ||
| T23 | /workspace/coverage/default/17.prim_present_test.1850792348 | May 21 01:04:03 PM PDT 24 | May 21 01:05:40 PM PDT 24 | 13458960000 ps | ||
| T24 | /workspace/coverage/default/32.prim_present_test.4086246996 | May 21 01:04:01 PM PDT 24 | May 21 01:05:18 PM PDT 24 | 9559160000 ps | ||
| T25 | /workspace/coverage/default/42.prim_present_test.2174190132 | May 21 01:04:09 PM PDT 24 | May 21 01:04:47 PM PDT 24 | 4429900000 ps | ||
| T26 | /workspace/coverage/default/24.prim_present_test.1244953114 | May 21 01:04:02 PM PDT 24 | May 21 01:04:48 PM PDT 24 | 6552780000 ps | ||
| T27 | /workspace/coverage/default/43.prim_present_test.3496794522 | May 21 01:04:08 PM PDT 24 | May 21 01:05:45 PM PDT 24 | 13852660000 ps | ||
| T28 | /workspace/coverage/default/48.prim_present_test.3229299642 | May 21 01:04:08 PM PDT 24 | May 21 01:05:19 PM PDT 24 | 10284560000 ps | ||
| T29 | /workspace/coverage/default/19.prim_present_test.888647025 | May 21 01:04:02 PM PDT 24 | May 21 01:04:56 PM PDT 24 | 6875800000 ps | ||
| T30 | /workspace/coverage/default/29.prim_present_test.1871826360 | May 21 01:04:02 PM PDT 24 | May 21 01:04:40 PM PDT 24 | 5035020000 ps | ||
| T31 | /workspace/coverage/default/31.prim_present_test.981905167 | May 21 01:04:03 PM PDT 24 | May 21 01:05:39 PM PDT 24 | 15233400000 ps | ||
| T32 | /workspace/coverage/default/25.prim_present_test.1891452297 | May 21 01:04:02 PM PDT 24 | May 21 01:04:45 PM PDT 24 | 5323320000 ps | ||
| T33 | /workspace/coverage/default/5.prim_present_test.1450029297 | May 21 01:03:51 PM PDT 24 | May 21 01:04:56 PM PDT 24 | 11480540000 ps | ||
| T34 | /workspace/coverage/default/2.prim_present_test.260698037 | May 21 01:03:45 PM PDT 24 | May 21 01:04:05 PM PDT 24 | 3535240000 ps | ||
| T35 | /workspace/coverage/default/22.prim_present_test.119799553 | May 21 01:04:03 PM PDT 24 | May 21 01:05:20 PM PDT 24 | 12883600000 ps | ||
| T36 | /workspace/coverage/default/23.prim_present_test.1488507799 | May 21 01:04:03 PM PDT 24 | May 21 01:05:15 PM PDT 24 | 7617940000 ps | ||
| T37 | /workspace/coverage/default/34.prim_present_test.3586725367 | May 21 01:04:09 PM PDT 24 | May 21 01:05:40 PM PDT 24 | 10019820000 ps | ||
| T38 | /workspace/coverage/default/16.prim_present_test.1794364804 | May 21 01:03:55 PM PDT 24 | May 21 01:04:31 PM PDT 24 | 4747960000 ps | ||
| T39 | /workspace/coverage/default/37.prim_present_test.3148741635 | May 21 01:04:09 PM PDT 24 | May 21 01:05:28 PM PDT 24 | 13675340000 ps | ||
| T40 | /workspace/coverage/default/3.prim_present_test.4036545609 | May 21 01:03:50 PM PDT 24 | May 21 01:05:29 PM PDT 24 | 13948760000 ps | ||
| T41 | /workspace/coverage/default/1.prim_present_test.3912499441 | May 21 01:03:44 PM PDT 24 | May 21 01:04:44 PM PDT 24 | 9389280000 ps | ||
| T42 | /workspace/coverage/default/21.prim_present_test.2245854949 | May 21 01:04:02 PM PDT 24 | May 21 01:05:09 PM PDT 24 | 10492880000 ps | ||
| T43 | /workspace/coverage/default/8.prim_present_test.1479914486 | May 21 01:04:00 PM PDT 24 | May 21 01:05:05 PM PDT 24 | 8838100000 ps | ||
| T44 | /workspace/coverage/default/7.prim_present_test.1584301181 | May 21 01:04:00 PM PDT 24 | May 21 01:04:27 PM PDT 24 | 3505480000 ps | ||
| T45 | /workspace/coverage/default/38.prim_present_test.336227090 | May 21 01:04:08 PM PDT 24 | May 21 01:06:06 PM PDT 24 | 14475140000 ps | ||
| T46 | /workspace/coverage/default/9.prim_present_test.3489592182 | May 21 01:03:56 PM PDT 24 | May 21 01:05:01 PM PDT 24 | 10342220000 ps | ||
| T47 | /workspace/coverage/default/36.prim_present_test.2820284831 | May 21 01:04:08 PM PDT 24 | May 21 01:05:36 PM PDT 24 | 11624380000 ps | ||
| T48 | /workspace/coverage/default/45.prim_present_test.2032571523 | May 21 01:04:08 PM PDT 24 | May 21 01:05:23 PM PDT 24 | 12112940000 ps | ||
| T49 | /workspace/coverage/default/46.prim_present_test.1252711447 | May 21 01:04:08 PM PDT 24 | May 21 01:05:06 PM PDT 24 | 6190080000 ps | ||
| T50 | /workspace/coverage/default/30.prim_present_test.3456924652 | May 21 01:04:05 PM PDT 24 | May 21 01:05:42 PM PDT 24 | 14483200000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3512392247 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10510240000 ps |
| CPU time | 39.61 seconds |
| Started | May 21 01:03:55 PM PDT 24 |
| Finished | May 21 01:05:09 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-bc0a289c-1839-4a3f-b001-2e9289013c47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3512392247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3512392247 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3213529739 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13197320000 ps |
| CPU time | 48.74 seconds |
| Started | May 21 01:03:45 PM PDT 24 |
| Finished | May 21 01:05:18 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-a3f044e4-6d23-496e-bc85-3c9f6ad7328e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213529739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3213529739 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3912499441 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9389280000 ps |
| CPU time | 31.95 seconds |
| Started | May 21 01:03:44 PM PDT 24 |
| Finished | May 21 01:04:44 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-160a6778-aa9f-40c6-bbe7-ca20b25190a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912499441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3912499441 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1636423850 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5473360000 ps |
| CPU time | 21.01 seconds |
| Started | May 21 01:03:57 PM PDT 24 |
| Finished | May 21 01:04:40 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-573f66c5-c9d9-4203-afdd-5373f29d8d4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636423850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1636423850 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1751539890 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9589540000 ps |
| CPU time | 35.48 seconds |
| Started | May 21 01:03:59 PM PDT 24 |
| Finished | May 21 01:05:09 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-15c22871-5caa-4736-a7b2-a73f8aaa26b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751539890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1751539890 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1946444367 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7701020000 ps |
| CPU time | 29.08 seconds |
| Started | May 21 01:03:56 PM PDT 24 |
| Finished | May 21 01:04:55 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-351321ab-1848-48c3-9a7f-e3353de4079f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946444367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1946444367 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.13694205 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12652340000 ps |
| CPU time | 49.88 seconds |
| Started | May 21 01:03:55 PM PDT 24 |
| Finished | May 21 01:05:30 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-6b549b8e-87bc-4542-98eb-d945cb1b53b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13694205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.13694205 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2625246436 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10257900000 ps |
| CPU time | 33.54 seconds |
| Started | May 21 01:03:55 PM PDT 24 |
| Finished | May 21 01:04:58 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-78a174d9-4446-4c1e-bb83-062dc7722fee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625246436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2625246436 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1794364804 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4747960000 ps |
| CPU time | 18.79 seconds |
| Started | May 21 01:03:55 PM PDT 24 |
| Finished | May 21 01:04:31 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-d1e12cf3-27b8-4399-8fcb-6207875fd2cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1794364804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1794364804 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1850792348 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13458960000 ps |
| CPU time | 50.38 seconds |
| Started | May 21 01:04:03 PM PDT 24 |
| Finished | May 21 01:05:40 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-b45e9712-fdc8-4936-8a50-3c1d76525196 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850792348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1850792348 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3468755030 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6673680000 ps |
| CPU time | 25.06 seconds |
| Started | May 21 01:04:04 PM PDT 24 |
| Finished | May 21 01:04:52 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-706bd904-b455-40cb-bf78-6ba6517711cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468755030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3468755030 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.888647025 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6875800000 ps |
| CPU time | 27.59 seconds |
| Started | May 21 01:04:02 PM PDT 24 |
| Finished | May 21 01:04:56 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-c366b652-a4ae-45fd-8e9e-8debaccb83ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888647025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.888647025 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.260698037 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3535240000 ps |
| CPU time | 10.56 seconds |
| Started | May 21 01:03:45 PM PDT 24 |
| Finished | May 21 01:04:05 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-8a3257db-1622-48ae-ad18-97eeb0a3ad4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260698037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.260698037 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.800924968 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4982320000 ps |
| CPU time | 20.21 seconds |
| Started | May 21 01:04:04 PM PDT 24 |
| Finished | May 21 01:04:44 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c81d9320-356f-497d-82fc-4b00c861106d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800924968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.800924968 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2245854949 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10492880000 ps |
| CPU time | 34.71 seconds |
| Started | May 21 01:04:02 PM PDT 24 |
| Finished | May 21 01:05:09 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-8e4d1bdb-4559-490b-94dd-fd5b23b9dfd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245854949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2245854949 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.119799553 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12883600000 ps |
| CPU time | 41.35 seconds |
| Started | May 21 01:04:03 PM PDT 24 |
| Finished | May 21 01:05:20 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-dd6f9a55-0ccd-4f90-82f4-50c6c8564dd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119799553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.119799553 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1488507799 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7617940000 ps |
| CPU time | 33.86 seconds |
| Started | May 21 01:04:03 PM PDT 24 |
| Finished | May 21 01:05:15 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-f0153015-3d7a-4ea2-8aac-11e72b47fa64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488507799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1488507799 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1244953114 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6552780000 ps |
| CPU time | 23.6 seconds |
| Started | May 21 01:04:02 PM PDT 24 |
| Finished | May 21 01:04:48 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-4a090c64-015f-4cc2-8944-32c3a7c3e5e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244953114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1244953114 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1891452297 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5323320000 ps |
| CPU time | 21.81 seconds |
| Started | May 21 01:04:02 PM PDT 24 |
| Finished | May 21 01:04:45 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-a3b1645d-8e7e-4aa5-a07e-d4a21b7486f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891452297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1891452297 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2428189882 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8166020000 ps |
| CPU time | 28.08 seconds |
| Started | May 21 01:04:01 PM PDT 24 |
| Finished | May 21 01:04:55 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-02fff441-300a-4763-a6bb-f8d26102c3cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428189882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2428189882 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1693452099 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5458480000 ps |
| CPU time | 15.65 seconds |
| Started | May 21 01:04:03 PM PDT 24 |
| Finished | May 21 01:04:33 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-37122527-aae2-4311-abe7-ed9c3c6f5802 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693452099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1693452099 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2687476711 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5152200000 ps |
| CPU time | 19.72 seconds |
| Started | May 21 01:04:03 PM PDT 24 |
| Finished | May 21 01:04:42 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-d5786b1b-5983-4c1c-ad44-06794f6e49f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687476711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2687476711 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1871826360 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5035020000 ps |
| CPU time | 19.89 seconds |
| Started | May 21 01:04:02 PM PDT 24 |
| Finished | May 21 01:04:40 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-03755316-5536-42a8-912a-83903fa53c5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871826360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1871826360 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.4036545609 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13948760000 ps |
| CPU time | 50.84 seconds |
| Started | May 21 01:03:50 PM PDT 24 |
| Finished | May 21 01:05:29 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-1e5ef1af-56da-4630-83ac-aa16487b99a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036545609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.4036545609 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3456924652 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14483200000 ps |
| CPU time | 50.8 seconds |
| Started | May 21 01:04:05 PM PDT 24 |
| Finished | May 21 01:05:42 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-11bc544c-28c3-482e-835a-fa9c8ee6200f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456924652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3456924652 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.981905167 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15233400000 ps |
| CPU time | 50.8 seconds |
| Started | May 21 01:04:03 PM PDT 24 |
| Finished | May 21 01:05:39 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-bdc826ea-7f5f-40ed-9393-a3dd0ead6d89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981905167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.981905167 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4086246996 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9559160000 ps |
| CPU time | 39.27 seconds |
| Started | May 21 01:04:01 PM PDT 24 |
| Finished | May 21 01:05:18 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-41e3ddf1-30ed-44b9-b9bb-87ec347c6824 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086246996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4086246996 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.492001950 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12257400000 ps |
| CPU time | 50.48 seconds |
| Started | May 21 01:04:02 PM PDT 24 |
| Finished | May 21 01:05:38 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-eac612b2-ca17-4c86-b18a-17c87ad8f038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=492001950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.492001950 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3586725367 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10019820000 ps |
| CPU time | 43.31 seconds |
| Started | May 21 01:04:09 PM PDT 24 |
| Finished | May 21 01:05:40 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-4421b078-6ffb-4fac-a2db-6896830ae7da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586725367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3586725367 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.441236376 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 14948200000 ps |
| CPU time | 48.35 seconds |
| Started | May 21 01:04:13 PM PDT 24 |
| Finished | May 21 01:05:44 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-3af7c58a-6bc3-4528-aed3-ba9c05266e60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441236376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.441236376 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2820284831 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11624380000 ps |
| CPU time | 45.19 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:05:36 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-d87f0380-8730-46cb-84a8-1c2d5e97cf3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820284831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2820284831 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3148741635 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13675340000 ps |
| CPU time | 41.65 seconds |
| Started | May 21 01:04:09 PM PDT 24 |
| Finished | May 21 01:05:28 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-1e727ac4-6c2d-48b0-ac12-ccda76276cc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148741635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3148741635 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.336227090 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14475140000 ps |
| CPU time | 60.16 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:06:06 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-8cda67fd-42b7-4a6a-810d-bfc5808e3c45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336227090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.336227090 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1142887597 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6309120000 ps |
| CPU time | 22.12 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:04:51 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-67da780c-e172-4751-bec2-9583706e9f28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142887597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1142887597 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4206972066 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15264400000 ps |
| CPU time | 45.59 seconds |
| Started | May 21 01:03:52 PM PDT 24 |
| Finished | May 21 01:05:17 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-0ae76525-16c0-4f3c-a91b-77e240faac2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206972066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4206972066 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.497435325 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8589480000 ps |
| CPU time | 31.04 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:05:08 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-3209b9f9-88a1-4a3b-ac10-73de390d4c7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497435325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.497435325 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1457797018 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4265600000 ps |
| CPU time | 13.58 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:04:35 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-31885c2e-518c-448a-93ea-d51d611bfcd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457797018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1457797018 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2174190132 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4429900000 ps |
| CPU time | 18.72 seconds |
| Started | May 21 01:04:09 PM PDT 24 |
| Finished | May 21 01:04:47 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ed65513e-1018-4606-9d65-d1d46e3fe6a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174190132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2174190132 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3496794522 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13852660000 ps |
| CPU time | 50.28 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:05:45 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-12b6b03b-f1de-4509-8933-69c254e55477 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496794522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3496794522 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1426000133 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14320140000 ps |
| CPU time | 52.21 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:05:49 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-895362e4-2170-472c-b50f-8b4b9b96a7ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426000133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1426000133 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2032571523 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12112940000 ps |
| CPU time | 39.28 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:05:23 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-c3614ff1-d3eb-4b26-bf45-2efb08774833 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032571523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2032571523 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1252711447 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6190080000 ps |
| CPU time | 28.88 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:05:06 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-a7f9e47f-3c4f-440f-a4d0-03c529f28ff9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252711447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1252711447 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3235365570 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7753100000 ps |
| CPU time | 31.1 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:05:08 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-5889d2f8-dba0-4b24-b1c4-46dce6a72c1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235365570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3235365570 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3229299642 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10284560000 ps |
| CPU time | 36.86 seconds |
| Started | May 21 01:04:08 PM PDT 24 |
| Finished | May 21 01:05:19 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-8055b0d8-47b2-455e-92ff-8a1c8d81ea7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229299642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3229299642 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2391523245 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3334360000 ps |
| CPU time | 13.79 seconds |
| Started | May 21 01:04:10 PM PDT 24 |
| Finished | May 21 01:04:38 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-7703076f-8d44-4e66-bc12-58a9cba7fa95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391523245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2391523245 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1450029297 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11480540000 ps |
| CPU time | 34.57 seconds |
| Started | May 21 01:03:51 PM PDT 24 |
| Finished | May 21 01:04:56 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-99365cf0-9b98-4e55-84af-5811c18364fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450029297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1450029297 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3277605279 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9452520000 ps |
| CPU time | 34.58 seconds |
| Started | May 21 01:04:00 PM PDT 24 |
| Finished | May 21 01:05:08 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-6f78e054-ddf0-4b0a-b2e8-fcd757edadfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277605279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3277605279 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1584301181 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3505480000 ps |
| CPU time | 13.46 seconds |
| Started | May 21 01:04:00 PM PDT 24 |
| Finished | May 21 01:04:27 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-70871946-60bf-46f0-ada6-30d8718119b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584301181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1584301181 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1479914486 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8838100000 ps |
| CPU time | 32.37 seconds |
| Started | May 21 01:04:00 PM PDT 24 |
| Finished | May 21 01:05:05 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-c6ff9a2a-b899-40f0-994f-2a8cffb1dd34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479914486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1479914486 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3489592182 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10342220000 ps |
| CPU time | 34.77 seconds |
| Started | May 21 01:03:56 PM PDT 24 |
| Finished | May 21 01:05:01 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-4af3bbec-2541-429e-8712-64c51bdd5a99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489592182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3489592182 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |