| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.794072748 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2874500917 |
| /workspace/coverage/default/1.prim_present_test.2146306757 |
| /workspace/coverage/default/10.prim_present_test.210003626 |
| /workspace/coverage/default/12.prim_present_test.4254407140 |
| /workspace/coverage/default/13.prim_present_test.3335562449 |
| /workspace/coverage/default/14.prim_present_test.4247731881 |
| /workspace/coverage/default/15.prim_present_test.217142946 |
| /workspace/coverage/default/16.prim_present_test.3594641670 |
| /workspace/coverage/default/17.prim_present_test.2999791513 |
| /workspace/coverage/default/18.prim_present_test.3590629075 |
| /workspace/coverage/default/19.prim_present_test.1564117034 |
| /workspace/coverage/default/2.prim_present_test.2061523468 |
| /workspace/coverage/default/20.prim_present_test.3523015137 |
| /workspace/coverage/default/21.prim_present_test.3123382420 |
| /workspace/coverage/default/22.prim_present_test.3123214324 |
| /workspace/coverage/default/23.prim_present_test.2670914317 |
| /workspace/coverage/default/24.prim_present_test.706081098 |
| /workspace/coverage/default/25.prim_present_test.1176721389 |
| /workspace/coverage/default/26.prim_present_test.2952432873 |
| /workspace/coverage/default/27.prim_present_test.916473514 |
| /workspace/coverage/default/28.prim_present_test.2129182769 |
| /workspace/coverage/default/29.prim_present_test.4260913285 |
| /workspace/coverage/default/3.prim_present_test.3195349523 |
| /workspace/coverage/default/30.prim_present_test.3304150415 |
| /workspace/coverage/default/31.prim_present_test.1295965951 |
| /workspace/coverage/default/32.prim_present_test.3727194724 |
| /workspace/coverage/default/33.prim_present_test.2121300817 |
| /workspace/coverage/default/34.prim_present_test.183675921 |
| /workspace/coverage/default/35.prim_present_test.1171756703 |
| /workspace/coverage/default/36.prim_present_test.2615831326 |
| /workspace/coverage/default/37.prim_present_test.993053886 |
| /workspace/coverage/default/38.prim_present_test.3314497682 |
| /workspace/coverage/default/39.prim_present_test.2703781080 |
| /workspace/coverage/default/4.prim_present_test.1242721486 |
| /workspace/coverage/default/40.prim_present_test.2027889787 |
| /workspace/coverage/default/41.prim_present_test.679692742 |
| /workspace/coverage/default/42.prim_present_test.3046725197 |
| /workspace/coverage/default/43.prim_present_test.1588027748 |
| /workspace/coverage/default/44.prim_present_test.3719847159 |
| /workspace/coverage/default/45.prim_present_test.3193406507 |
| /workspace/coverage/default/46.prim_present_test.161382066 |
| /workspace/coverage/default/47.prim_present_test.2936440137 |
| /workspace/coverage/default/48.prim_present_test.2968695312 |
| /workspace/coverage/default/49.prim_present_test.1848569319 |
| /workspace/coverage/default/5.prim_present_test.1910791318 |
| /workspace/coverage/default/6.prim_present_test.1394347538 |
| /workspace/coverage/default/7.prim_present_test.2783441871 |
| /workspace/coverage/default/8.prim_present_test.1632816131 |
| /workspace/coverage/default/9.prim_present_test.644232782 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_present_test.2783441871 | May 23 02:58:01 PM PDT 24 | May 23 02:58:51 PM PDT 24 | 6478380000 ps | ||
| T2 | /workspace/coverage/default/15.prim_present_test.217142946 | May 23 02:58:04 PM PDT 24 | May 23 02:59:34 PM PDT 24 | 10639200000 ps | ||
| T3 | /workspace/coverage/default/16.prim_present_test.3594641670 | May 23 02:58:04 PM PDT 24 | May 23 02:59:21 PM PDT 24 | 8600640000 ps | ||
| T4 | /workspace/coverage/default/41.prim_present_test.679692742 | May 23 02:58:13 PM PDT 24 | May 23 02:58:53 PM PDT 24 | 5885660000 ps | ||
| T5 | /workspace/coverage/default/11.prim_present_test.794072748 | May 23 02:58:01 PM PDT 24 | May 23 02:59:46 PM PDT 24 | 15466520000 ps | ||
| T6 | /workspace/coverage/default/26.prim_present_test.2952432873 | May 23 02:58:15 PM PDT 24 | May 23 02:59:50 PM PDT 24 | 13982240000 ps | ||
| T7 | /workspace/coverage/default/24.prim_present_test.706081098 | May 23 02:58:13 PM PDT 24 | May 23 03:00:10 PM PDT 24 | 13865680000 ps | ||
| T8 | /workspace/coverage/default/22.prim_present_test.3123214324 | May 23 02:58:16 PM PDT 24 | May 23 02:59:54 PM PDT 24 | 12718680000 ps | ||
| T9 | /workspace/coverage/default/40.prim_present_test.2027889787 | May 23 02:58:19 PM PDT 24 | May 23 02:58:55 PM PDT 24 | 3906000000 ps | ||
| T10 | /workspace/coverage/default/46.prim_present_test.161382066 | May 23 02:58:14 PM PDT 24 | May 23 02:59:08 PM PDT 24 | 7522460000 ps | ||
| T11 | /workspace/coverage/default/31.prim_present_test.1295965951 | May 23 02:58:15 PM PDT 24 | May 23 02:59:43 PM PDT 24 | 10779940000 ps | ||
| T12 | /workspace/coverage/default/14.prim_present_test.4247731881 | May 23 02:58:06 PM PDT 24 | May 23 02:59:15 PM PDT 24 | 8545460000 ps | ||
| T13 | /workspace/coverage/default/29.prim_present_test.4260913285 | May 23 02:58:19 PM PDT 24 | May 23 02:59:07 PM PDT 24 | 5384080000 ps | ||
| T14 | /workspace/coverage/default/32.prim_present_test.3727194724 | May 23 02:58:15 PM PDT 24 | May 23 03:00:03 PM PDT 24 | 13888620000 ps | ||
| T15 | /workspace/coverage/default/5.prim_present_test.1910791318 | May 23 02:58:02 PM PDT 24 | May 23 02:58:43 PM PDT 24 | 4302180000 ps | ||
| T16 | /workspace/coverage/default/20.prim_present_test.3523015137 | May 23 02:58:04 PM PDT 24 | May 23 02:59:45 PM PDT 24 | 12724260000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.2703781080 | May 23 02:58:13 PM PDT 24 | May 23 02:58:53 PM PDT 24 | 5184440000 ps | ||
| T18 | /workspace/coverage/default/18.prim_present_test.3590629075 | May 23 02:58:05 PM PDT 24 | May 23 02:59:31 PM PDT 24 | 8531820000 ps | ||
| T19 | /workspace/coverage/default/38.prim_present_test.3314497682 | May 23 02:58:12 PM PDT 24 | May 23 02:59:37 PM PDT 24 | 10554880000 ps | ||
| T20 | /workspace/coverage/default/19.prim_present_test.1564117034 | May 23 02:58:05 PM PDT 24 | May 23 02:59:19 PM PDT 24 | 7146120000 ps | ||
| T21 | /workspace/coverage/default/28.prim_present_test.2129182769 | May 23 02:58:17 PM PDT 24 | May 23 02:58:51 PM PDT 24 | 4551420000 ps | ||
| T22 | /workspace/coverage/default/13.prim_present_test.3335562449 | May 23 02:58:05 PM PDT 24 | May 23 02:59:33 PM PDT 24 | 9959680000 ps | ||
| T23 | /workspace/coverage/default/42.prim_present_test.3046725197 | May 23 02:58:13 PM PDT 24 | May 23 02:59:47 PM PDT 24 | 12166880000 ps | ||
| T24 | /workspace/coverage/default/4.prim_present_test.1242721486 | May 23 02:58:02 PM PDT 24 | May 23 02:58:37 PM PDT 24 | 3993420000 ps | ||
| T25 | /workspace/coverage/default/47.prim_present_test.2936440137 | May 23 02:58:16 PM PDT 24 | May 23 02:59:18 PM PDT 24 | 7903760000 ps | ||
| T26 | /workspace/coverage/default/45.prim_present_test.3193406507 | May 23 02:58:16 PM PDT 24 | May 23 03:00:08 PM PDT 24 | 15250140000 ps | ||
| T27 | /workspace/coverage/default/37.prim_present_test.993053886 | May 23 02:58:13 PM PDT 24 | May 23 02:59:17 PM PDT 24 | 7794640000 ps | ||
| T28 | /workspace/coverage/default/17.prim_present_test.2999791513 | May 23 02:58:05 PM PDT 24 | May 23 02:59:08 PM PDT 24 | 6001600000 ps | ||
| T29 | /workspace/coverage/default/1.prim_present_test.2146306757 | May 23 02:58:04 PM PDT 24 | May 23 02:59:03 PM PDT 24 | 5581860000 ps | ||
| T30 | /workspace/coverage/default/2.prim_present_test.2061523468 | May 23 02:58:03 PM PDT 24 | May 23 02:59:03 PM PDT 24 | 7477200000 ps | ||
| T31 | /workspace/coverage/default/23.prim_present_test.2670914317 | May 23 02:58:14 PM PDT 24 | May 23 03:00:13 PM PDT 24 | 15451640000 ps | ||
| T32 | /workspace/coverage/default/21.prim_present_test.3123382420 | May 23 02:58:13 PM PDT 24 | May 23 02:59:57 PM PDT 24 | 12909640000 ps | ||
| T33 | /workspace/coverage/default/8.prim_present_test.1632816131 | May 23 02:58:01 PM PDT 24 | May 23 02:58:43 PM PDT 24 | 4811200000 ps | ||
| T34 | /workspace/coverage/default/25.prim_present_test.1176721389 | May 23 02:58:16 PM PDT 24 | May 23 02:59:55 PM PDT 24 | 10908280000 ps | ||
| T35 | /workspace/coverage/default/48.prim_present_test.2968695312 | May 23 02:58:12 PM PDT 24 | May 23 02:59:58 PM PDT 24 | 14287280000 ps | ||
| T36 | /workspace/coverage/default/33.prim_present_test.2121300817 | May 23 02:58:12 PM PDT 24 | May 23 02:59:07 PM PDT 24 | 8213760000 ps | ||
| T37 | /workspace/coverage/default/6.prim_present_test.1394347538 | May 23 02:58:03 PM PDT 24 | May 23 02:59:47 PM PDT 24 | 14588600000 ps | ||
| T38 | /workspace/coverage/default/44.prim_present_test.3719847159 | May 23 02:58:14 PM PDT 24 | May 23 02:58:48 PM PDT 24 | 3616460000 ps | ||
| T39 | /workspace/coverage/default/9.prim_present_test.644232782 | May 23 02:58:01 PM PDT 24 | May 23 02:59:14 PM PDT 24 | 7720860000 ps | ||
| T40 | /workspace/coverage/default/3.prim_present_test.3195349523 | May 23 02:58:00 PM PDT 24 | May 23 02:59:37 PM PDT 24 | 10859300000 ps | ||
| T41 | /workspace/coverage/default/35.prim_present_test.1171756703 | May 23 02:58:19 PM PDT 24 | May 23 03:00:04 PM PDT 24 | 13199180000 ps | ||
| T42 | /workspace/coverage/default/30.prim_present_test.3304150415 | May 23 02:58:13 PM PDT 24 | May 23 02:59:54 PM PDT 24 | 11306320000 ps | ||
| T43 | /workspace/coverage/default/34.prim_present_test.183675921 | May 23 02:58:16 PM PDT 24 | May 23 02:59:01 PM PDT 24 | 4803760000 ps | ||
| T44 | /workspace/coverage/default/43.prim_present_test.1588027748 | May 23 02:58:13 PM PDT 24 | May 23 02:59:24 PM PDT 24 | 9777400000 ps | ||
| T45 | /workspace/coverage/default/0.prim_present_test.2874500917 | May 23 02:58:01 PM PDT 24 | May 23 02:59:26 PM PDT 24 | 10967180000 ps | ||
| T46 | /workspace/coverage/default/12.prim_present_test.4254407140 | May 23 02:58:04 PM PDT 24 | May 23 02:59:09 PM PDT 24 | 7144880000 ps | ||
| T47 | /workspace/coverage/default/10.prim_present_test.210003626 | May 23 02:58:03 PM PDT 24 | May 23 02:58:58 PM PDT 24 | 6595560000 ps | ||
| T48 | /workspace/coverage/default/27.prim_present_test.916473514 | May 23 02:58:13 PM PDT 24 | May 23 02:59:01 PM PDT 24 | 5969980000 ps | ||
| T49 | /workspace/coverage/default/36.prim_present_test.2615831326 | May 23 02:58:12 PM PDT 24 | May 23 02:58:46 PM PDT 24 | 4306520000 ps | ||
| T50 | /workspace/coverage/default/49.prim_present_test.1848569319 | May 23 02:58:19 PM PDT 24 | May 23 02:58:55 PM PDT 24 | 3912820000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.794072748 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 15466520000 ps |
| CPU time | 52.37 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 02:59:46 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-d54bcccc-802c-4bb0-a67c-1074334e998e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=794072748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.794072748 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2874500917 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10967180000 ps |
| CPU time | 39.9 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 02:59:26 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-254f5de3-d784-4fac-998b-3b220e7de28b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874500917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2874500917 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2146306757 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5581860000 ps |
| CPU time | 25.64 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 02:59:03 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-070f5df0-375d-489b-bf16-efcb61fca994 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146306757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2146306757 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.210003626 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6595560000 ps |
| CPU time | 24.66 seconds |
| Started | May 23 02:58:03 PM PDT 24 |
| Finished | May 23 02:58:58 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-70e8d19e-684a-44ea-99bc-c4711b411e3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210003626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.210003626 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4254407140 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7144880000 ps |
| CPU time | 28.83 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 02:59:09 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-d303597c-c81f-439d-98f4-ba9fe6cf1161 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254407140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4254407140 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3335562449 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9959680000 ps |
| CPU time | 40.36 seconds |
| Started | May 23 02:58:05 PM PDT 24 |
| Finished | May 23 02:59:33 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-4c851a7d-f7a3-4400-8ab1-647c807704e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335562449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3335562449 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4247731881 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8545460000 ps |
| CPU time | 31.46 seconds |
| Started | May 23 02:58:06 PM PDT 24 |
| Finished | May 23 02:59:15 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-f8afcdc5-e926-4ab3-8691-3a0885a2f38a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247731881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4247731881 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.217142946 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10639200000 ps |
| CPU time | 41.37 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 02:59:34 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-ca4cc6ab-884a-4986-b7c6-1e76c8ec0606 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217142946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.217142946 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3594641670 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8600640000 ps |
| CPU time | 34.87 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 02:59:21 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-b1225290-b41f-4297-8937-345a86c17ea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594641670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3594641670 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2999791513 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6001600000 ps |
| CPU time | 27.56 seconds |
| Started | May 23 02:58:05 PM PDT 24 |
| Finished | May 23 02:59:08 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-e57bdf14-ecbc-4e49-a851-8656a7fe2acf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2999791513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2999791513 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3590629075 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8531820000 ps |
| CPU time | 38.35 seconds |
| Started | May 23 02:58:05 PM PDT 24 |
| Finished | May 23 02:59:31 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-d866174c-0391-4523-9b0c-a017f8da6d12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590629075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3590629075 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1564117034 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7146120000 ps |
| CPU time | 32.78 seconds |
| Started | May 23 02:58:05 PM PDT 24 |
| Finished | May 23 02:59:19 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-20e4621e-e474-463e-a784-dba08d723d02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564117034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1564117034 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2061523468 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7477200000 ps |
| CPU time | 26.8 seconds |
| Started | May 23 02:58:03 PM PDT 24 |
| Finished | May 23 02:59:03 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-a88982b3-ac5a-42cf-8351-2590d8137612 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061523468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2061523468 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3523015137 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12724260000 ps |
| CPU time | 47.74 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 02:59:45 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-64a45160-9c59-4fac-810e-aafea4ddb4a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523015137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3523015137 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3123382420 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12909640000 ps |
| CPU time | 53.96 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 02:59:57 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-856bd13e-b11f-4ae7-adbc-52dd7146eee6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123382420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3123382420 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3123214324 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12718680000 ps |
| CPU time | 48.1 seconds |
| Started | May 23 02:58:16 PM PDT 24 |
| Finished | May 23 02:59:54 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-62474f65-9268-4cd6-84f0-07119ae102b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123214324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3123214324 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2670914317 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15451640000 ps |
| CPU time | 59.7 seconds |
| Started | May 23 02:58:14 PM PDT 24 |
| Finished | May 23 03:00:13 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-97530687-a4c3-494b-a32e-ba04939a3743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670914317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2670914317 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.706081098 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13865680000 ps |
| CPU time | 59.32 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 03:00:10 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-7faaebf0-b8fa-4eee-a0ed-a2f805e8b9c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706081098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.706081098 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1176721389 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10908280000 ps |
| CPU time | 49.11 seconds |
| Started | May 23 02:58:16 PM PDT 24 |
| Finished | May 23 02:59:55 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-2d24007b-e365-42da-95e9-b7e948b72224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176721389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1176721389 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2952432873 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13982240000 ps |
| CPU time | 49.85 seconds |
| Started | May 23 02:58:15 PM PDT 24 |
| Finished | May 23 02:59:50 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-01114261-c813-4492-8ebb-7222d888914b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952432873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2952432873 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.916473514 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5969980000 ps |
| CPU time | 23.95 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 02:59:01 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-7720416c-e454-4ca5-b7d3-275e2ab8f2c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916473514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.916473514 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2129182769 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4551420000 ps |
| CPU time | 16.63 seconds |
| Started | May 23 02:58:17 PM PDT 24 |
| Finished | May 23 02:58:51 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-c0aec650-0128-4a5b-9614-62e4ee965c06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129182769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2129182769 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4260913285 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5384080000 ps |
| CPU time | 22.23 seconds |
| Started | May 23 02:58:19 PM PDT 24 |
| Finished | May 23 02:59:07 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-bbe6bc7a-2cc6-4364-a41f-9faf9cc645d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4260913285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4260913285 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3195349523 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10859300000 ps |
| CPU time | 44.27 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 02:59:37 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-95472c0a-0a69-44d4-9cce-48c2e3d6e834 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195349523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3195349523 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3304150415 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11306320000 ps |
| CPU time | 49.36 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 02:59:54 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-14b863fe-46f8-4ecc-9a24-64a662c9633e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304150415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3304150415 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1295965951 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10779940000 ps |
| CPU time | 41.25 seconds |
| Started | May 23 02:58:15 PM PDT 24 |
| Finished | May 23 02:59:43 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-9b5c37a9-4568-4b11-87fa-9fd3cd19585c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1295965951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1295965951 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3727194724 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13888620000 ps |
| CPU time | 52.89 seconds |
| Started | May 23 02:58:15 PM PDT 24 |
| Finished | May 23 03:00:03 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-ffa11569-4f85-4519-b4d6-3739d4509102 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727194724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3727194724 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2121300817 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8213760000 ps |
| CPU time | 27.61 seconds |
| Started | May 23 02:58:12 PM PDT 24 |
| Finished | May 23 02:59:07 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-954cfc09-3e54-4f17-9393-23933f34f29e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121300817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2121300817 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.183675921 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4803760000 ps |
| CPU time | 21.54 seconds |
| Started | May 23 02:58:16 PM PDT 24 |
| Finished | May 23 02:59:01 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-00ca9278-ca6f-4118-aca6-f0267ea5d006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183675921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.183675921 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1171756703 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13199180000 ps |
| CPU time | 52.5 seconds |
| Started | May 23 02:58:19 PM PDT 24 |
| Finished | May 23 03:00:04 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c9d24b38-7ea9-443a-aebe-9309d3bbaf85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171756703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1171756703 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2615831326 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4306520000 ps |
| CPU time | 16.53 seconds |
| Started | May 23 02:58:12 PM PDT 24 |
| Finished | May 23 02:58:46 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-aa9cc989-a8a6-436e-be66-9058c75f1a64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615831326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2615831326 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.993053886 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7794640000 ps |
| CPU time | 30.5 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 02:59:17 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-b6d66340-e62c-4c44-abe3-47661711de83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993053886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.993053886 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3314497682 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10554880000 ps |
| CPU time | 41.36 seconds |
| Started | May 23 02:58:12 PM PDT 24 |
| Finished | May 23 02:59:37 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-54e2dfe5-5af3-4c7b-b437-07f537b3c2a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314497682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3314497682 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2703781080 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5184440000 ps |
| CPU time | 19.22 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 02:58:53 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-8a06d39b-fb72-4a6f-9833-24bd01869783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703781080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2703781080 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1242721486 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3993420000 ps |
| CPU time | 14.92 seconds |
| Started | May 23 02:58:02 PM PDT 24 |
| Finished | May 23 02:58:37 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-30bddcd9-19a5-4372-b8ca-fbdfbd3d48eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242721486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1242721486 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2027889787 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3906000000 ps |
| CPU time | 16.39 seconds |
| Started | May 23 02:58:19 PM PDT 24 |
| Finished | May 23 02:58:55 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-ac9ec0d9-044e-40c1-9a29-6bb8acad8d79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027889787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2027889787 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.679692742 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5885660000 ps |
| CPU time | 20.54 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 02:58:53 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-27e4717e-c1ff-4117-afbc-433636ca20e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679692742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.679692742 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3046725197 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12166880000 ps |
| CPU time | 47.07 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 02:59:47 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-e313eae2-b8a6-4999-993d-66c16bd7bd61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046725197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3046725197 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1588027748 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 9777400000 ps |
| CPU time | 34.39 seconds |
| Started | May 23 02:58:13 PM PDT 24 |
| Finished | May 23 02:59:24 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-28a4536e-2bdb-4c2d-8278-2b08f2b26896 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588027748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1588027748 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3719847159 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3616460000 ps |
| CPU time | 15.68 seconds |
| Started | May 23 02:58:14 PM PDT 24 |
| Finished | May 23 02:58:48 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-43297140-b276-468a-ac27-6abec20c6ba5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719847159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3719847159 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3193406507 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15250140000 ps |
| CPU time | 55.66 seconds |
| Started | May 23 02:58:16 PM PDT 24 |
| Finished | May 23 03:00:08 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-02a393e9-d4d8-4262-8907-88a3725087c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193406507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3193406507 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.161382066 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7522460000 ps |
| CPU time | 26.73 seconds |
| Started | May 23 02:58:14 PM PDT 24 |
| Finished | May 23 02:59:08 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-98d67934-c7f4-4aa9-80d5-2b1f3264c561 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161382066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.161382066 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2936440137 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7903760000 ps |
| CPU time | 31.33 seconds |
| Started | May 23 02:58:16 PM PDT 24 |
| Finished | May 23 02:59:18 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-35135bf6-a027-4701-b495-56d6fdfec0ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2936440137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2936440137 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2968695312 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14287280000 ps |
| CPU time | 54.41 seconds |
| Started | May 23 02:58:12 PM PDT 24 |
| Finished | May 23 02:59:58 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-ddc42fe5-9cd3-4b4f-96eb-8951c7a17041 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968695312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2968695312 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1848569319 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3912820000 ps |
| CPU time | 16.23 seconds |
| Started | May 23 02:58:19 PM PDT 24 |
| Finished | May 23 02:58:55 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-0666d8cb-fc72-4d58-9353-93ce170238d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848569319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1848569319 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1910791318 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4302180000 ps |
| CPU time | 17.87 seconds |
| Started | May 23 02:58:02 PM PDT 24 |
| Finished | May 23 02:58:43 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c07de088-54a9-44b2-b5eb-408b98abb4fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910791318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1910791318 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1394347538 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 14588600000 ps |
| CPU time | 50.7 seconds |
| Started | May 23 02:58:03 PM PDT 24 |
| Finished | May 23 02:59:47 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-25912018-b440-4041-9275-2b4565057f96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394347538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1394347538 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2783441871 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6478380000 ps |
| CPU time | 23 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 02:58:51 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-fc857a75-f720-4189-9000-142ef49ad8b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783441871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2783441871 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1632816131 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4811200000 ps |
| CPU time | 18.09 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 02:58:43 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c2c7b80b-808f-4e9c-a65b-b34d04566e44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632816131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1632816131 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.644232782 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7720860000 ps |
| CPU time | 33.55 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 02:59:14 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-4ca69a93-5b6c-4104-9c48-defc04e95a7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644232782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.644232782 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |