| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.4096298020 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.184827820 |
| /workspace/coverage/default/10.prim_present_test.1289472522 |
| /workspace/coverage/default/11.prim_present_test.27874926 |
| /workspace/coverage/default/12.prim_present_test.3188555049 |
| /workspace/coverage/default/13.prim_present_test.3276322483 |
| /workspace/coverage/default/14.prim_present_test.4050617164 |
| /workspace/coverage/default/15.prim_present_test.1068047771 |
| /workspace/coverage/default/16.prim_present_test.2907599791 |
| /workspace/coverage/default/17.prim_present_test.4130883667 |
| /workspace/coverage/default/18.prim_present_test.2057689217 |
| /workspace/coverage/default/19.prim_present_test.3139135596 |
| /workspace/coverage/default/2.prim_present_test.2199555942 |
| /workspace/coverage/default/20.prim_present_test.465770012 |
| /workspace/coverage/default/21.prim_present_test.3451711442 |
| /workspace/coverage/default/22.prim_present_test.372583565 |
| /workspace/coverage/default/23.prim_present_test.1995479650 |
| /workspace/coverage/default/24.prim_present_test.4063853165 |
| /workspace/coverage/default/25.prim_present_test.865403839 |
| /workspace/coverage/default/26.prim_present_test.875680849 |
| /workspace/coverage/default/27.prim_present_test.666503517 |
| /workspace/coverage/default/28.prim_present_test.492405136 |
| /workspace/coverage/default/29.prim_present_test.2040065392 |
| /workspace/coverage/default/3.prim_present_test.1355069085 |
| /workspace/coverage/default/30.prim_present_test.3143911011 |
| /workspace/coverage/default/31.prim_present_test.1442148766 |
| /workspace/coverage/default/32.prim_present_test.1774617342 |
| /workspace/coverage/default/33.prim_present_test.3563900024 |
| /workspace/coverage/default/34.prim_present_test.1892028477 |
| /workspace/coverage/default/35.prim_present_test.2683631926 |
| /workspace/coverage/default/36.prim_present_test.2468780591 |
| /workspace/coverage/default/37.prim_present_test.2222033443 |
| /workspace/coverage/default/38.prim_present_test.2133736811 |
| /workspace/coverage/default/39.prim_present_test.624820839 |
| /workspace/coverage/default/4.prim_present_test.478090441 |
| /workspace/coverage/default/40.prim_present_test.1188483348 |
| /workspace/coverage/default/41.prim_present_test.3081504191 |
| /workspace/coverage/default/42.prim_present_test.2162678917 |
| /workspace/coverage/default/43.prim_present_test.1764233560 |
| /workspace/coverage/default/44.prim_present_test.2230350352 |
| /workspace/coverage/default/45.prim_present_test.15095260 |
| /workspace/coverage/default/46.prim_present_test.1992069001 |
| /workspace/coverage/default/47.prim_present_test.2065390529 |
| /workspace/coverage/default/48.prim_present_test.2583303062 |
| /workspace/coverage/default/49.prim_present_test.4157649461 |
| /workspace/coverage/default/5.prim_present_test.2898697145 |
| /workspace/coverage/default/6.prim_present_test.4276542546 |
| /workspace/coverage/default/7.prim_present_test.243410201 |
| /workspace/coverage/default/8.prim_present_test.4056485783 |
| /workspace/coverage/default/9.prim_present_test.1374822832 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_present_test.2057689217 | May 26 01:54:05 PM PDT 24 | May 26 01:54:58 PM PDT 24 | 7424500000 ps | ||
| T2 | /workspace/coverage/default/22.prim_present_test.372583565 | May 26 01:54:10 PM PDT 24 | May 26 01:55:16 PM PDT 24 | 7695440000 ps | ||
| T3 | /workspace/coverage/default/30.prim_present_test.3143911011 | May 26 01:54:06 PM PDT 24 | May 26 01:55:18 PM PDT 24 | 10110960000 ps | ||
| T4 | /workspace/coverage/default/1.prim_present_test.4096298020 | May 26 01:54:06 PM PDT 24 | May 26 01:54:42 PM PDT 24 | 4638840000 ps | ||
| T5 | /workspace/coverage/default/24.prim_present_test.4063853165 | May 26 01:54:06 PM PDT 24 | May 26 01:55:38 PM PDT 24 | 11561760000 ps | ||
| T6 | /workspace/coverage/default/3.prim_present_test.1355069085 | May 26 01:54:05 PM PDT 24 | May 26 01:55:46 PM PDT 24 | 13364720000 ps | ||
| T7 | /workspace/coverage/default/23.prim_present_test.1995479650 | May 26 01:54:06 PM PDT 24 | May 26 01:55:36 PM PDT 24 | 12466340000 ps | ||
| T8 | /workspace/coverage/default/14.prim_present_test.4050617164 | May 26 01:54:09 PM PDT 24 | May 26 01:54:58 PM PDT 24 | 6517440000 ps | ||
| T9 | /workspace/coverage/default/20.prim_present_test.465770012 | May 26 01:54:07 PM PDT 24 | May 26 01:55:42 PM PDT 24 | 12067060000 ps | ||
| T10 | /workspace/coverage/default/43.prim_present_test.1764233560 | May 26 01:54:10 PM PDT 24 | May 26 01:54:47 PM PDT 24 | 4566300000 ps | ||
| T11 | /workspace/coverage/default/28.prim_present_test.492405136 | May 26 01:54:16 PM PDT 24 | May 26 01:54:44 PM PDT 24 | 3585460000 ps | ||
| T12 | /workspace/coverage/default/46.prim_present_test.1992069001 | May 26 01:54:08 PM PDT 24 | May 26 01:55:58 PM PDT 24 | 13456480000 ps | ||
| T13 | /workspace/coverage/default/31.prim_present_test.1442148766 | May 26 01:54:07 PM PDT 24 | May 26 01:55:38 PM PDT 24 | 12086900000 ps | ||
| T14 | /workspace/coverage/default/4.prim_present_test.478090441 | May 26 01:54:05 PM PDT 24 | May 26 01:54:37 PM PDT 24 | 3889880000 ps | ||
| T15 | /workspace/coverage/default/12.prim_present_test.3188555049 | May 26 01:54:05 PM PDT 24 | May 26 01:55:46 PM PDT 24 | 14406320000 ps | ||
| T16 | /workspace/coverage/default/21.prim_present_test.3451711442 | May 26 01:54:05 PM PDT 24 | May 26 01:54:33 PM PDT 24 | 4015120000 ps | ||
| T17 | /workspace/coverage/default/0.prim_present_test.184827820 | May 26 01:54:13 PM PDT 24 | May 26 01:56:07 PM PDT 24 | 15366080000 ps | ||
| T18 | /workspace/coverage/default/8.prim_present_test.4056485783 | May 26 01:54:05 PM PDT 24 | May 26 01:54:40 PM PDT 24 | 4437960000 ps | ||
| T19 | /workspace/coverage/default/29.prim_present_test.2040065392 | May 26 01:54:09 PM PDT 24 | May 26 01:55:40 PM PDT 24 | 13031160000 ps | ||
| T20 | /workspace/coverage/default/35.prim_present_test.2683631926 | May 26 01:54:05 PM PDT 24 | May 26 01:55:48 PM PDT 24 | 14103760000 ps | ||
| T21 | /workspace/coverage/default/19.prim_present_test.3139135596 | May 26 01:54:08 PM PDT 24 | May 26 01:54:54 PM PDT 24 | 5053000000 ps | ||
| T22 | /workspace/coverage/default/34.prim_present_test.1892028477 | May 26 01:54:08 PM PDT 24 | May 26 01:55:08 PM PDT 24 | 8833140000 ps | ||
| T23 | /workspace/coverage/default/26.prim_present_test.875680849 | May 26 01:54:08 PM PDT 24 | May 26 01:55:01 PM PDT 24 | 7371800000 ps | ||
| T24 | /workspace/coverage/default/5.prim_present_test.2898697145 | May 26 01:54:12 PM PDT 24 | May 26 01:55:38 PM PDT 24 | 11365840000 ps | ||
| T25 | /workspace/coverage/default/48.prim_present_test.2583303062 | May 26 01:54:06 PM PDT 24 | May 26 01:54:53 PM PDT 24 | 6369880000 ps | ||
| T26 | /workspace/coverage/default/37.prim_present_test.2222033443 | May 26 01:54:04 PM PDT 24 | May 26 01:54:30 PM PDT 24 | 3438520000 ps | ||
| T27 | /workspace/coverage/default/32.prim_present_test.1774617342 | May 26 01:54:03 PM PDT 24 | May 26 01:55:07 PM PDT 24 | 8395420000 ps | ||
| T28 | /workspace/coverage/default/44.prim_present_test.2230350352 | May 26 01:54:09 PM PDT 24 | May 26 01:55:16 PM PDT 24 | 8657060000 ps | ||
| T29 | /workspace/coverage/default/16.prim_present_test.2907599791 | May 26 01:54:07 PM PDT 24 | May 26 01:55:49 PM PDT 24 | 14344940000 ps | ||
| T30 | /workspace/coverage/default/2.prim_present_test.2199555942 | May 26 01:54:02 PM PDT 24 | May 26 01:55:15 PM PDT 24 | 10647880000 ps | ||
| T31 | /workspace/coverage/default/49.prim_present_test.4157649461 | May 26 01:54:10 PM PDT 24 | May 26 01:54:56 PM PDT 24 | 6915480000 ps | ||
| T32 | /workspace/coverage/default/39.prim_present_test.624820839 | May 26 01:54:08 PM PDT 24 | May 26 01:55:07 PM PDT 24 | 6548440000 ps | ||
| T33 | /workspace/coverage/default/36.prim_present_test.2468780591 | May 26 01:54:07 PM PDT 24 | May 26 01:54:52 PM PDT 24 | 5504980000 ps | ||
| T34 | /workspace/coverage/default/17.prim_present_test.4130883667 | May 26 01:54:05 PM PDT 24 | May 26 01:55:48 PM PDT 24 | 12261120000 ps | ||
| T35 | /workspace/coverage/default/7.prim_present_test.243410201 | May 26 01:54:07 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 12315060000 ps | ||
| T36 | /workspace/coverage/default/27.prim_present_test.666503517 | May 26 01:54:08 PM PDT 24 | May 26 01:55:32 PM PDT 24 | 11876720000 ps | ||
| T37 | /workspace/coverage/default/38.prim_present_test.2133736811 | May 26 01:54:13 PM PDT 24 | May 26 01:54:36 PM PDT 24 | 3194860000 ps | ||
| T38 | /workspace/coverage/default/45.prim_present_test.15095260 | May 26 01:54:07 PM PDT 24 | May 26 01:54:41 PM PDT 24 | 5090820000 ps | ||
| T39 | /workspace/coverage/default/33.prim_present_test.3563900024 | May 26 01:54:07 PM PDT 24 | May 26 01:55:09 PM PDT 24 | 7369940000 ps | ||
| T40 | /workspace/coverage/default/6.prim_present_test.4276542546 | May 26 01:54:02 PM PDT 24 | May 26 01:54:43 PM PDT 24 | 5745540000 ps | ||
| T41 | /workspace/coverage/default/13.prim_present_test.3276322483 | May 26 01:54:04 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 13199800000 ps | ||
| T42 | /workspace/coverage/default/47.prim_present_test.2065390529 | May 26 01:54:07 PM PDT 24 | May 26 01:55:40 PM PDT 24 | 12801140000 ps | ||
| T43 | /workspace/coverage/default/9.prim_present_test.1374822832 | May 26 01:54:10 PM PDT 24 | May 26 01:55:00 PM PDT 24 | 6735680000 ps | ||
| T44 | /workspace/coverage/default/11.prim_present_test.27874926 | May 26 01:54:07 PM PDT 24 | May 26 01:55:52 PM PDT 24 | 14624560000 ps | ||
| T45 | /workspace/coverage/default/25.prim_present_test.865403839 | May 26 01:54:13 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 11591520000 ps | ||
| T46 | /workspace/coverage/default/15.prim_present_test.1068047771 | May 26 01:54:06 PM PDT 24 | May 26 01:54:52 PM PDT 24 | 5153440000 ps | ||
| T47 | /workspace/coverage/default/40.prim_present_test.1188483348 | May 26 01:54:08 PM PDT 24 | May 26 01:56:01 PM PDT 24 | 13271720000 ps | ||
| T48 | /workspace/coverage/default/42.prim_present_test.2162678917 | May 26 01:54:08 PM PDT 24 | May 26 01:56:14 PM PDT 24 | 14954400000 ps | ||
| T49 | /workspace/coverage/default/10.prim_present_test.1289472522 | May 26 01:54:06 PM PDT 24 | May 26 01:56:08 PM PDT 24 | 14771500000 ps | ||
| T50 | /workspace/coverage/default/41.prim_present_test.3081504191 | May 26 01:54:07 PM PDT 24 | May 26 01:56:04 PM PDT 24 | 15475200000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.4096298020 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4638840000 ps |
| CPU time | 18.11 seconds |
| Started | May 26 01:54:06 PM PDT 24 |
| Finished | May 26 01:54:42 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-2ced55dd-340b-48a4-8f74-59031a5196cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096298020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4096298020 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.184827820 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 15366080000 ps |
| CPU time | 59.56 seconds |
| Started | May 26 01:54:13 PM PDT 24 |
| Finished | May 26 01:56:07 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-bea49a26-622e-4eef-949a-5b0cc7464c1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184827820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.184827820 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1289472522 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14771500000 ps |
| CPU time | 59.98 seconds |
| Started | May 26 01:54:06 PM PDT 24 |
| Finished | May 26 01:56:08 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-73fc32ac-14df-4e59-a15f-4f77c5021e50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289472522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1289472522 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.27874926 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14624560000 ps |
| CPU time | 53.44 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:55:52 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-753daf28-047b-4b42-afb9-9f2269f9220e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27874926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.27874926 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3188555049 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 14406320000 ps |
| CPU time | 52.28 seconds |
| Started | May 26 01:54:05 PM PDT 24 |
| Finished | May 26 01:55:46 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-d82b46b3-b323-43da-a8f0-3bceedbd95cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188555049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3188555049 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3276322483 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13199800000 ps |
| CPU time | 49.2 seconds |
| Started | May 26 01:54:04 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c5c21da8-4d06-4ab1-a7f9-e7dec58324a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276322483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3276322483 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4050617164 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6517440000 ps |
| CPU time | 24.63 seconds |
| Started | May 26 01:54:09 PM PDT 24 |
| Finished | May 26 01:54:58 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-a36d356b-fe89-4077-be65-29618a00c968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050617164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4050617164 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1068047771 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5153440000 ps |
| CPU time | 22.38 seconds |
| Started | May 26 01:54:06 PM PDT 24 |
| Finished | May 26 01:54:52 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-34057b2c-9058-4d9c-8fd1-ba89f10733a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068047771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1068047771 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2907599791 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14344940000 ps |
| CPU time | 53.61 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-23e3b085-5fd8-4d5e-8a7e-922b48a71480 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907599791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2907599791 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4130883667 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12261120000 ps |
| CPU time | 50.7 seconds |
| Started | May 26 01:54:05 PM PDT 24 |
| Finished | May 26 01:55:48 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-07ad6a28-25a6-438d-83db-3a2c25ac5afd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130883667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4130883667 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2057689217 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7424500000 ps |
| CPU time | 27.78 seconds |
| Started | May 26 01:54:05 PM PDT 24 |
| Finished | May 26 01:54:58 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-01f87aad-e340-49ce-8c80-68e90f44c829 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057689217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2057689217 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3139135596 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5053000000 ps |
| CPU time | 21.66 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:54:54 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-dffa7fd9-2456-4496-b537-2ee73d140fff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139135596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3139135596 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2199555942 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10647880000 ps |
| CPU time | 38.48 seconds |
| Started | May 26 01:54:02 PM PDT 24 |
| Finished | May 26 01:55:15 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-795b2376-e2ea-4f12-893e-97c528becf6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199555942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2199555942 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.465770012 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12067060000 ps |
| CPU time | 46.48 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:55:42 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-34b732a0-4867-4518-bab7-294590924510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465770012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.465770012 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3451711442 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4015120000 ps |
| CPU time | 14.44 seconds |
| Started | May 26 01:54:05 PM PDT 24 |
| Finished | May 26 01:54:33 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-b1e27ce7-fe6b-4015-876b-8bf3cc6cdf64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451711442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3451711442 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.372583565 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7695440000 ps |
| CPU time | 31.41 seconds |
| Started | May 26 01:54:10 PM PDT 24 |
| Finished | May 26 01:55:16 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-ad409973-5184-46d2-9a66-edb36261ee57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372583565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.372583565 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1995479650 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12466340000 ps |
| CPU time | 45.81 seconds |
| Started | May 26 01:54:06 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-14046f27-82fb-4bd8-aa5b-bcdd01f2b22c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995479650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1995479650 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4063853165 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11561760000 ps |
| CPU time | 46.05 seconds |
| Started | May 26 01:54:06 PM PDT 24 |
| Finished | May 26 01:55:38 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-27ffbf74-4191-4703-8d41-b43889e214d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063853165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4063853165 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.865403839 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11591520000 ps |
| CPU time | 42.5 seconds |
| Started | May 26 01:54:13 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-5d4e15dc-98a4-428e-9591-e292441f5a80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865403839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.865403839 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.875680849 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7371800000 ps |
| CPU time | 26.88 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:55:01 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-45adcecb-c481-41dd-9fd8-98ac558452b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875680849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.875680849 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.666503517 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11876720000 ps |
| CPU time | 42.69 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:55:32 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-1eea0b60-97d7-4c81-9257-bc89a32f6b54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666503517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.666503517 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.492405136 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3585460000 ps |
| CPU time | 13.63 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:44 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-c1a68f99-fcb3-49a0-b3bd-2fcb72e70a9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=492405136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.492405136 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2040065392 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13031160000 ps |
| CPU time | 46.9 seconds |
| Started | May 26 01:54:09 PM PDT 24 |
| Finished | May 26 01:55:40 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-1ea145d8-8635-4ab5-b9fe-61a3828eebd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040065392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2040065392 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1355069085 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13364720000 ps |
| CPU time | 51.8 seconds |
| Started | May 26 01:54:05 PM PDT 24 |
| Finished | May 26 01:55:46 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-78e9559f-c21a-49ce-bc76-dfabe3f8f0ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355069085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1355069085 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3143911011 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10110960000 ps |
| CPU time | 36.71 seconds |
| Started | May 26 01:54:06 PM PDT 24 |
| Finished | May 26 01:55:18 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-23502b1b-553d-4da1-a99a-a40222b2078a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143911011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3143911011 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1442148766 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12086900000 ps |
| CPU time | 45.94 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:55:38 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-c98fbda2-9d60-4bc1-870d-775b522cfb7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442148766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1442148766 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1774617342 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8395420000 ps |
| CPU time | 33.11 seconds |
| Started | May 26 01:54:03 PM PDT 24 |
| Finished | May 26 01:55:07 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-7a8dc8ec-ddc9-44cf-854d-8a113c14260d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774617342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1774617342 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3563900024 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7369940000 ps |
| CPU time | 30.83 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:55:09 PM PDT 24 |
| Peak memory | 144612 kb |
| Host | smart-89cdb3c1-cc57-4d1b-a69e-456afeb30801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3563900024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3563900024 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1892028477 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8833140000 ps |
| CPU time | 30.99 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:55:08 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-21401c77-acd0-4b17-9b5f-11d89d71a9af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892028477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1892028477 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2683631926 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14103760000 ps |
| CPU time | 53.1 seconds |
| Started | May 26 01:54:05 PM PDT 24 |
| Finished | May 26 01:55:48 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-47cd6b26-752e-4883-90e6-964e79b0e774 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683631926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2683631926 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2468780591 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5504980000 ps |
| CPU time | 22.34 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:54:52 PM PDT 24 |
| Peak memory | 144584 kb |
| Host | smart-ab464672-ac74-43c5-8a23-e1711bae104e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468780591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2468780591 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2222033443 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3438520000 ps |
| CPU time | 13.33 seconds |
| Started | May 26 01:54:04 PM PDT 24 |
| Finished | May 26 01:54:30 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-860e6225-5af7-4233-9646-9fc9799bd786 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222033443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2222033443 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2133736811 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3194860000 ps |
| CPU time | 11.19 seconds |
| Started | May 26 01:54:13 PM PDT 24 |
| Finished | May 26 01:54:36 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-0c123f93-eebb-488d-8b7a-917749f6b0a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133736811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2133736811 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.624820839 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6548440000 ps |
| CPU time | 28.15 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:55:07 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-3f450600-8104-4c66-a3d7-f68d46d9098f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624820839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.624820839 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.478090441 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3889880000 ps |
| CPU time | 15.77 seconds |
| Started | May 26 01:54:05 PM PDT 24 |
| Finished | May 26 01:54:37 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-236cb9ba-c77c-4d03-ac0a-ed5994f43a23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478090441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.478090441 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1188483348 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13271720000 ps |
| CPU time | 55.42 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:56:01 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-fed5dc8b-956f-4497-9f29-bab111a94136 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188483348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1188483348 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3081504191 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15475200000 ps |
| CPU time | 57.74 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:56:04 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-cd7c61e1-484b-46ed-9c5f-7b993894a89a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081504191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3081504191 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2162678917 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14954400000 ps |
| CPU time | 62.24 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:56:14 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-a015457a-a8a6-4d23-b5a5-82a6f4485389 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162678917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2162678917 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1764233560 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4566300000 ps |
| CPU time | 15.62 seconds |
| Started | May 26 01:54:10 PM PDT 24 |
| Finished | May 26 01:54:47 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-71c75f9a-e81a-4c7f-8675-7951b9def031 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764233560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1764233560 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2230350352 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8657060000 ps |
| CPU time | 32.89 seconds |
| Started | May 26 01:54:09 PM PDT 24 |
| Finished | May 26 01:55:16 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-b59e2a23-84d1-4c6e-b1f8-bd9c645eb279 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230350352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2230350352 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.15095260 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5090820000 ps |
| CPU time | 17.06 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:54:41 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-6a2e0e70-d752-405f-896f-a779dd947e01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15095260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.15095260 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1992069001 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13456480000 ps |
| CPU time | 54.67 seconds |
| Started | May 26 01:54:08 PM PDT 24 |
| Finished | May 26 01:55:58 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-783b4794-e262-4834-b312-0b147fa7c2d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992069001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1992069001 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2065390529 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12801140000 ps |
| CPU time | 48.49 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:55:40 PM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-7ebe989b-fb91-44ae-a11d-71061f0555fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2065390529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2065390529 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2583303062 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6369880000 ps |
| CPU time | 23.79 seconds |
| Started | May 26 01:54:06 PM PDT 24 |
| Finished | May 26 01:54:53 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-324ca819-83fc-4923-99be-92d4091aa3d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583303062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2583303062 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.4157649461 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6915480000 ps |
| CPU time | 22.76 seconds |
| Started | May 26 01:54:10 PM PDT 24 |
| Finished | May 26 01:54:56 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-d8c558eb-ac1a-4a2d-9092-7a1c7c2aa563 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157649461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4157649461 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2898697145 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11365840000 ps |
| CPU time | 43.82 seconds |
| Started | May 26 01:54:12 PM PDT 24 |
| Finished | May 26 01:55:38 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-34c3b470-2384-4dbc-8a5d-01ccc4235285 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898697145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2898697145 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4276542546 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5745540000 ps |
| CPU time | 21.73 seconds |
| Started | May 26 01:54:02 PM PDT 24 |
| Finished | May 26 01:54:43 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-8a938c7c-372d-429c-996d-8fd798dd048d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276542546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4276542546 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.243410201 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12315060000 ps |
| CPU time | 47.5 seconds |
| Started | May 26 01:54:07 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-97122ff0-ca0e-42cb-897f-62b816a401d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243410201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.243410201 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4056485783 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4437960000 ps |
| CPU time | 17.4 seconds |
| Started | May 26 01:54:05 PM PDT 24 |
| Finished | May 26 01:54:40 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-a32d498e-0c59-4c1e-91e2-95d1924936a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056485783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4056485783 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1374822832 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6735680000 ps |
| CPU time | 25.83 seconds |
| Started | May 26 01:54:10 PM PDT 24 |
| Finished | May 26 01:55:00 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-f016f5ef-f326-436e-9659-732c69e8da39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374822832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1374822832 |
| Directory | /workspace/9.prim_present_test/latest |
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