Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.83 90.41 100.00 98.73 100.00 100.00


Total tests in report: 50
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
97.83 97.83 90.41 90.41 100.00 100.00 98.73 98.73 100.00 100.00 100.00 100.00 /workspace/coverage/default/0.prim_present_test.3403939857


Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_present_test.3093090658
/workspace/coverage/default/10.prim_present_test.2756556251
/workspace/coverage/default/11.prim_present_test.3883948420
/workspace/coverage/default/12.prim_present_test.1823490215
/workspace/coverage/default/13.prim_present_test.2152104258
/workspace/coverage/default/14.prim_present_test.1542079287
/workspace/coverage/default/15.prim_present_test.1251591708
/workspace/coverage/default/16.prim_present_test.1399182233
/workspace/coverage/default/17.prim_present_test.1049410689
/workspace/coverage/default/18.prim_present_test.414713625
/workspace/coverage/default/19.prim_present_test.3121927626
/workspace/coverage/default/2.prim_present_test.1751666593
/workspace/coverage/default/20.prim_present_test.1229407209
/workspace/coverage/default/21.prim_present_test.2710150238
/workspace/coverage/default/22.prim_present_test.594430154
/workspace/coverage/default/23.prim_present_test.944784828
/workspace/coverage/default/24.prim_present_test.226605209
/workspace/coverage/default/25.prim_present_test.814088836
/workspace/coverage/default/26.prim_present_test.1275444083
/workspace/coverage/default/27.prim_present_test.997588001
/workspace/coverage/default/28.prim_present_test.985693739
/workspace/coverage/default/29.prim_present_test.1280659721
/workspace/coverage/default/3.prim_present_test.3572422143
/workspace/coverage/default/30.prim_present_test.1234584263
/workspace/coverage/default/31.prim_present_test.37029905
/workspace/coverage/default/32.prim_present_test.3106623448
/workspace/coverage/default/33.prim_present_test.2532048568
/workspace/coverage/default/34.prim_present_test.2207993017
/workspace/coverage/default/35.prim_present_test.196118093
/workspace/coverage/default/36.prim_present_test.3459056901
/workspace/coverage/default/37.prim_present_test.1253023636
/workspace/coverage/default/38.prim_present_test.1728618919
/workspace/coverage/default/39.prim_present_test.2207049414
/workspace/coverage/default/4.prim_present_test.524696579
/workspace/coverage/default/40.prim_present_test.3547445202
/workspace/coverage/default/41.prim_present_test.1243240163
/workspace/coverage/default/42.prim_present_test.562618272
/workspace/coverage/default/43.prim_present_test.2388786118
/workspace/coverage/default/44.prim_present_test.272913313
/workspace/coverage/default/45.prim_present_test.1557966016
/workspace/coverage/default/46.prim_present_test.2541534132
/workspace/coverage/default/47.prim_present_test.2378994687
/workspace/coverage/default/48.prim_present_test.3822429390
/workspace/coverage/default/49.prim_present_test.4191000583
/workspace/coverage/default/5.prim_present_test.1303424877
/workspace/coverage/default/6.prim_present_test.419053969
/workspace/coverage/default/7.prim_present_test.2377843824
/workspace/coverage/default/8.prim_present_test.306132584
/workspace/coverage/default/9.prim_present_test.3632308627




Total test records in report: 50
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/14.prim_present_test.1542079287 May 28 01:10:14 PM PDT 24 May 28 01:11:09 PM PDT 24 8377440000 ps
T2 /workspace/coverage/default/28.prim_present_test.985693739 May 28 01:10:06 PM PDT 24 May 28 01:11:43 PM PDT 24 12993340000 ps
T3 /workspace/coverage/default/24.prim_present_test.226605209 May 28 01:10:09 PM PDT 24 May 28 01:11:11 PM PDT 24 8470440000 ps
T4 /workspace/coverage/default/29.prim_present_test.1280659721 May 28 01:10:11 PM PDT 24 May 28 01:10:44 PM PDT 24 4111220000 ps
T5 /workspace/coverage/default/13.prim_present_test.2152104258 May 28 01:10:09 PM PDT 24 May 28 01:11:23 PM PDT 24 9263420000 ps
T6 /workspace/coverage/default/8.prim_present_test.306132584 May 28 01:10:10 PM PDT 24 May 28 01:11:00 PM PDT 24 5971220000 ps
T7 /workspace/coverage/default/2.prim_present_test.1751666593 May 28 01:10:25 PM PDT 24 May 28 01:11:22 PM PDT 24 7386680000 ps
T8 /workspace/coverage/default/22.prim_present_test.594430154 May 28 01:10:08 PM PDT 24 May 28 01:12:07 PM PDT 24 14388960000 ps
T9 /workspace/coverage/default/0.prim_present_test.3403939857 May 28 01:10:09 PM PDT 24 May 28 01:11:33 PM PDT 24 10648500000 ps
T10 /workspace/coverage/default/4.prim_present_test.524696579 May 28 01:10:09 PM PDT 24 May 28 01:12:08 PM PDT 24 14881860000 ps
T11 /workspace/coverage/default/45.prim_present_test.1557966016 May 28 01:10:08 PM PDT 24 May 28 01:11:14 PM PDT 24 7715900000 ps
T12 /workspace/coverage/default/41.prim_present_test.1243240163 May 28 01:10:08 PM PDT 24 May 28 01:11:03 PM PDT 24 7426980000 ps
T13 /workspace/coverage/default/36.prim_present_test.3459056901 May 28 01:10:15 PM PDT 24 May 28 01:11:41 PM PDT 24 11120940000 ps
T14 /workspace/coverage/default/17.prim_present_test.1049410689 May 28 01:10:09 PM PDT 24 May 28 01:10:35 PM PDT 24 3172540000 ps
T15 /workspace/coverage/default/16.prim_present_test.1399182233 May 28 01:10:11 PM PDT 24 May 28 01:11:14 PM PDT 24 7583840000 ps
T16 /workspace/coverage/default/18.prim_present_test.414713625 May 28 01:10:11 PM PDT 24 May 28 01:12:10 PM PDT 24 12816640000 ps
T17 /workspace/coverage/default/12.prim_present_test.1823490215 May 28 01:10:07 PM PDT 24 May 28 01:11:00 PM PDT 24 6933460000 ps
T18 /workspace/coverage/default/47.prim_present_test.2378994687 May 28 01:10:11 PM PDT 24 May 28 01:12:09 PM PDT 24 12629400000 ps
T19 /workspace/coverage/default/21.prim_present_test.2710150238 May 28 01:10:08 PM PDT 24 May 28 01:11:38 PM PDT 24 12102400000 ps
T20 /workspace/coverage/default/19.prim_present_test.3121927626 May 28 01:10:09 PM PDT 24 May 28 01:11:44 PM PDT 24 14248840000 ps
T21 /workspace/coverage/default/11.prim_present_test.3883948420 May 28 01:10:08 PM PDT 24 May 28 01:12:07 PM PDT 24 15129240000 ps
T22 /workspace/coverage/default/48.prim_present_test.3822429390 May 28 01:10:16 PM PDT 24 May 28 01:11:18 PM PDT 24 7087220000 ps
T23 /workspace/coverage/default/34.prim_present_test.2207993017 May 28 01:10:11 PM PDT 24 May 28 01:12:06 PM PDT 24 12252440000 ps
T24 /workspace/coverage/default/3.prim_present_test.3572422143 May 28 01:10:09 PM PDT 24 May 28 01:11:10 PM PDT 24 7640260000 ps
T25 /workspace/coverage/default/7.prim_present_test.2377843824 May 28 01:10:19 PM PDT 24 May 28 01:11:05 PM PDT 24 5532260000 ps
T26 /workspace/coverage/default/15.prim_present_test.1251591708 May 28 01:10:20 PM PDT 24 May 28 01:10:56 PM PDT 24 5309680000 ps
T27 /workspace/coverage/default/43.prim_present_test.2388786118 May 28 01:10:11 PM PDT 24 May 28 01:12:25 PM PDT 24 14542720000 ps
T28 /workspace/coverage/default/35.prim_present_test.196118093 May 28 01:10:20 PM PDT 24 May 28 01:12:03 PM PDT 24 13764000000 ps
T29 /workspace/coverage/default/46.prim_present_test.2541534132 May 28 01:10:12 PM PDT 24 May 28 01:10:51 PM PDT 24 4036820000 ps
T30 /workspace/coverage/default/9.prim_present_test.3632308627 May 28 01:10:18 PM PDT 24 May 28 01:11:01 PM PDT 24 5973700000 ps
T31 /workspace/coverage/default/40.prim_present_test.3547445202 May 28 01:10:08 PM PDT 24 May 28 01:11:43 PM PDT 24 13248160000 ps
T32 /workspace/coverage/default/32.prim_present_test.3106623448 May 28 01:10:07 PM PDT 24 May 28 01:11:22 PM PDT 24 9644100000 ps
T33 /workspace/coverage/default/20.prim_present_test.1229407209 May 28 01:10:10 PM PDT 24 May 28 01:10:37 PM PDT 24 3641880000 ps
T34 /workspace/coverage/default/49.prim_present_test.4191000583 May 28 01:10:09 PM PDT 24 May 28 01:11:05 PM PDT 24 6325860000 ps
T35 /workspace/coverage/default/33.prim_present_test.2532048568 May 28 01:10:10 PM PDT 24 May 28 01:10:59 PM PDT 24 5943320000 ps
T36 /workspace/coverage/default/23.prim_present_test.944784828 May 28 01:10:12 PM PDT 24 May 28 01:11:47 PM PDT 24 12306380000 ps
T37 /workspace/coverage/default/37.prim_present_test.1253023636 May 28 01:10:12 PM PDT 24 May 28 01:10:42 PM PDT 24 3238880000 ps
T38 /workspace/coverage/default/6.prim_present_test.419053969 May 28 01:10:09 PM PDT 24 May 28 01:11:35 PM PDT 24 10218840000 ps
T39 /workspace/coverage/default/10.prim_present_test.2756556251 May 28 01:10:14 PM PDT 24 May 28 01:10:55 PM PDT 24 5173900000 ps
T40 /workspace/coverage/default/25.prim_present_test.814088836 May 28 01:10:13 PM PDT 24 May 28 01:11:24 PM PDT 24 8601260000 ps
T41 /workspace/coverage/default/30.prim_present_test.1234584263 May 28 01:10:10 PM PDT 24 May 28 01:10:58 PM PDT 24 6477140000 ps
T42 /workspace/coverage/default/42.prim_present_test.562618272 May 28 01:10:08 PM PDT 24 May 28 01:11:37 PM PDT 24 12049700000 ps
T43 /workspace/coverage/default/26.prim_present_test.1275444083 May 28 01:10:10 PM PDT 24 May 28 01:12:24 PM PDT 24 14521640000 ps
T44 /workspace/coverage/default/31.prim_present_test.37029905 May 28 01:10:06 PM PDT 24 May 28 01:11:03 PM PDT 24 7882680000 ps
T45 /workspace/coverage/default/44.prim_present_test.272913313 May 28 01:10:08 PM PDT 24 May 28 01:10:59 PM PDT 24 5799480000 ps
T46 /workspace/coverage/default/38.prim_present_test.1728618919 May 28 01:10:19 PM PDT 24 May 28 01:11:57 PM PDT 24 12819120000 ps
T47 /workspace/coverage/default/27.prim_present_test.997588001 May 28 01:10:09 PM PDT 24 May 28 01:11:39 PM PDT 24 11454500000 ps
T48 /workspace/coverage/default/1.prim_present_test.3093090658 May 28 01:10:08 PM PDT 24 May 28 01:10:51 PM PDT 24 5875740000 ps
T49 /workspace/coverage/default/39.prim_present_test.2207049414 May 28 01:10:12 PM PDT 24 May 28 01:11:56 PM PDT 24 15141020000 ps
T50 /workspace/coverage/default/5.prim_present_test.1303424877 May 28 01:10:20 PM PDT 24 May 28 01:11:10 PM PDT 24 6468460000 ps


Test location /workspace/coverage/default/0.prim_present_test.3403939857
Short name T9
Test name
Test status
Simulation time 10648500000 ps
CPU time 41.12 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:11:33 PM PDT 24
Peak memory 145256 kb
Host smart-d542e7df-ba1e-44bb-b395-a3b02fb969c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403939857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3403939857
Directory /workspace/0.prim_present_test/latest


Test location /workspace/coverage/default/1.prim_present_test.3093090658
Short name T48
Test name
Test status
Simulation time 5875740000 ps
CPU time 20.27 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:51 PM PDT 24
Peak memory 145084 kb
Host smart-1b20b1c9-688b-4367-8bac-3be727956770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093090658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3093090658
Directory /workspace/1.prim_present_test/latest


Test location /workspace/coverage/default/10.prim_present_test.2756556251
Short name T39
Test name
Test status
Simulation time 5173900000 ps
CPU time 17.81 seconds
Started May 28 01:10:14 PM PDT 24
Finished May 28 01:10:55 PM PDT 24
Peak memory 145172 kb
Host smart-916c082a-2846-44b8-8838-a9cedc43b46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756556251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2756556251
Directory /workspace/10.prim_present_test/latest


Test location /workspace/coverage/default/11.prim_present_test.3883948420
Short name T21
Test name
Test status
Simulation time 15129240000 ps
CPU time 58.91 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:12:07 PM PDT 24
Peak memory 145064 kb
Host smart-1afd7d68-154d-468c-8ed7-79922fdfc750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883948420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3883948420
Directory /workspace/11.prim_present_test/latest


Test location /workspace/coverage/default/12.prim_present_test.1823490215
Short name T17
Test name
Test status
Simulation time 6933460000 ps
CPU time 26.04 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:11:00 PM PDT 24
Peak memory 145080 kb
Host smart-3b1c4a05-6fa3-42bd-90d5-deaf6baa98a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823490215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1823490215
Directory /workspace/12.prim_present_test/latest


Test location /workspace/coverage/default/13.prim_present_test.2152104258
Short name T5
Test name
Test status
Simulation time 9263420000 ps
CPU time 35.46 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:11:23 PM PDT 24
Peak memory 145084 kb
Host smart-33d22ad8-bc87-4442-905d-739f1972807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152104258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2152104258
Directory /workspace/13.prim_present_test/latest


Test location /workspace/coverage/default/14.prim_present_test.1542079287
Short name T1
Test name
Test status
Simulation time 8377440000 ps
CPU time 25.98 seconds
Started May 28 01:10:14 PM PDT 24
Finished May 28 01:11:09 PM PDT 24
Peak memory 145080 kb
Host smart-9222f5a2-0cd0-448c-8d1a-32a27b4af13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542079287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1542079287
Directory /workspace/14.prim_present_test/latest


Test location /workspace/coverage/default/15.prim_present_test.1251591708
Short name T26
Test name
Test status
Simulation time 5309680000 ps
CPU time 17.22 seconds
Started May 28 01:10:20 PM PDT 24
Finished May 28 01:10:56 PM PDT 24
Peak memory 145076 kb
Host smart-d6232986-07d0-454a-b42b-9267a8e3a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251591708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1251591708
Directory /workspace/15.prim_present_test/latest


Test location /workspace/coverage/default/16.prim_present_test.1399182233
Short name T15
Test name
Test status
Simulation time 7583840000 ps
CPU time 29.58 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:11:14 PM PDT 24
Peak memory 145080 kb
Host smart-5bbbe048-27e3-4f12-994a-a3ead02ad158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399182233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1399182233
Directory /workspace/16.prim_present_test/latest


Test location /workspace/coverage/default/17.prim_present_test.1049410689
Short name T14
Test name
Test status
Simulation time 3172540000 ps
CPU time 10.69 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:35 PM PDT 24
Peak memory 144900 kb
Host smart-4f16d9dc-9902-443b-b011-6f5c1e065d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049410689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1049410689
Directory /workspace/17.prim_present_test/latest


Test location /workspace/coverage/default/18.prim_present_test.414713625
Short name T16
Test name
Test status
Simulation time 12816640000 ps
CPU time 54.94 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:12:10 PM PDT 24
Peak memory 145164 kb
Host smart-8d688109-2a3b-44c7-ac45-d1ccc78d0768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414713625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.414713625
Directory /workspace/18.prim_present_test/latest


Test location /workspace/coverage/default/19.prim_present_test.3121927626
Short name T20
Test name
Test status
Simulation time 14248840000 ps
CPU time 47.38 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:11:44 PM PDT 24
Peak memory 145076 kb
Host smart-31dc461a-3004-436a-9fdc-583b81ca6ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121927626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3121927626
Directory /workspace/19.prim_present_test/latest


Test location /workspace/coverage/default/2.prim_present_test.1751666593
Short name T7
Test name
Test status
Simulation time 7386680000 ps
CPU time 28.79 seconds
Started May 28 01:10:25 PM PDT 24
Finished May 28 01:11:22 PM PDT 24
Peak memory 145088 kb
Host smart-433502c9-5021-400a-a1ea-b7187262a38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751666593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1751666593
Directory /workspace/2.prim_present_test/latest


Test location /workspace/coverage/default/20.prim_present_test.1229407209
Short name T33
Test name
Test status
Simulation time 3641880000 ps
CPU time 11.29 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:37 PM PDT 24
Peak memory 144928 kb
Host smart-0e280aaa-54fa-4997-b2a1-13b305f1bafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229407209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1229407209
Directory /workspace/20.prim_present_test/latest


Test location /workspace/coverage/default/21.prim_present_test.2710150238
Short name T19
Test name
Test status
Simulation time 12102400000 ps
CPU time 44.63 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:11:38 PM PDT 24
Peak memory 145160 kb
Host smart-737abd82-6e8e-4ade-bd52-fdcc31e41011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710150238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2710150238
Directory /workspace/21.prim_present_test/latest


Test location /workspace/coverage/default/22.prim_present_test.594430154
Short name T8
Test name
Test status
Simulation time 14388960000 ps
CPU time 58.43 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:12:07 PM PDT 24
Peak memory 145088 kb
Host smart-c3fed3b5-3541-4df4-ab19-723d464f3cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594430154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.594430154
Directory /workspace/22.prim_present_test/latest


Test location /workspace/coverage/default/23.prim_present_test.944784828
Short name T36
Test name
Test status
Simulation time 12306380000 ps
CPU time 45.7 seconds
Started May 28 01:10:12 PM PDT 24
Finished May 28 01:11:47 PM PDT 24
Peak memory 145088 kb
Host smart-736f8ffe-6af7-4966-a257-d74dea3acdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944784828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.944784828
Directory /workspace/23.prim_present_test/latest


Test location /workspace/coverage/default/24.prim_present_test.226605209
Short name T3
Test name
Test status
Simulation time 8470440000 ps
CPU time 29.37 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:11:11 PM PDT 24
Peak memory 145160 kb
Host smart-897bd0ef-5986-450b-81a7-50b101a0d494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226605209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.226605209
Directory /workspace/24.prim_present_test/latest


Test location /workspace/coverage/default/25.prim_present_test.814088836
Short name T40
Test name
Test status
Simulation time 8601260000 ps
CPU time 32.52 seconds
Started May 28 01:10:13 PM PDT 24
Finished May 28 01:11:24 PM PDT 24
Peak memory 145088 kb
Host smart-20210564-64f9-4fc2-a45c-f8d665d5d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814088836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.814088836
Directory /workspace/25.prim_present_test/latest


Test location /workspace/coverage/default/26.prim_present_test.1275444083
Short name T43
Test name
Test status
Simulation time 14521640000 ps
CPU time 62.56 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:12:24 PM PDT 24
Peak memory 145160 kb
Host smart-5a8fb3f8-36ba-441c-a529-536438e53418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275444083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1275444083
Directory /workspace/26.prim_present_test/latest


Test location /workspace/coverage/default/27.prim_present_test.997588001
Short name T47
Test name
Test status
Simulation time 11454500000 ps
CPU time 43.37 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:11:39 PM PDT 24
Peak memory 145176 kb
Host smart-1deaeafc-4fd6-409f-9943-854063667f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997588001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.997588001
Directory /workspace/27.prim_present_test/latest


Test location /workspace/coverage/default/28.prim_present_test.985693739
Short name T2
Test name
Test status
Simulation time 12993340000 ps
CPU time 49.05 seconds
Started May 28 01:10:06 PM PDT 24
Finished May 28 01:11:43 PM PDT 24
Peak memory 145088 kb
Host smart-b055a9c8-b561-4540-b8d9-b74e7311263f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985693739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.985693739
Directory /workspace/28.prim_present_test/latest


Test location /workspace/coverage/default/29.prim_present_test.1280659721
Short name T4
Test name
Test status
Simulation time 4111220000 ps
CPU time 13.89 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:10:44 PM PDT 24
Peak memory 144900 kb
Host smart-0627a275-fa4d-4986-b786-e503ef6137fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280659721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1280659721
Directory /workspace/29.prim_present_test/latest


Test location /workspace/coverage/default/3.prim_present_test.3572422143
Short name T24
Test name
Test status
Simulation time 7640260000 ps
CPU time 28.82 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:11:10 PM PDT 24
Peak memory 145168 kb
Host smart-eaf6ca06-234d-4a6d-a19b-58cd9f25ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572422143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3572422143
Directory /workspace/3.prim_present_test/latest


Test location /workspace/coverage/default/30.prim_present_test.1234584263
Short name T41
Test name
Test status
Simulation time 6477140000 ps
CPU time 21.86 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:58 PM PDT 24
Peak memory 145080 kb
Host smart-f4ec396e-aa42-4645-8a08-4b002917fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234584263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1234584263
Directory /workspace/30.prim_present_test/latest


Test location /workspace/coverage/default/31.prim_present_test.37029905
Short name T44
Test name
Test status
Simulation time 7882680000 ps
CPU time 28.69 seconds
Started May 28 01:10:06 PM PDT 24
Finished May 28 01:11:03 PM PDT 24
Peak memory 145184 kb
Host smart-33489ed7-3b85-4252-bf86-28d5cf9702f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37029905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.37029905
Directory /workspace/31.prim_present_test/latest


Test location /workspace/coverage/default/32.prim_present_test.3106623448
Short name T32
Test name
Test status
Simulation time 9644100000 ps
CPU time 36.88 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:11:22 PM PDT 24
Peak memory 145080 kb
Host smart-4a3a1012-9368-4ace-878d-9e9a0272e2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106623448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3106623448
Directory /workspace/32.prim_present_test/latest


Test location /workspace/coverage/default/33.prim_present_test.2532048568
Short name T35
Test name
Test status
Simulation time 5943320000 ps
CPU time 22.07 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:59 PM PDT 24
Peak memory 145168 kb
Host smart-1b9eaef1-e252-4951-ac92-4a365fb4bdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532048568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2532048568
Directory /workspace/33.prim_present_test/latest


Test location /workspace/coverage/default/34.prim_present_test.2207993017
Short name T23
Test name
Test status
Simulation time 12252440000 ps
CPU time 53.23 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:12:06 PM PDT 24
Peak memory 145156 kb
Host smart-2fcf8cbc-14d8-4a99-9080-2c037aba5387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207993017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2207993017
Directory /workspace/34.prim_present_test/latest


Test location /workspace/coverage/default/35.prim_present_test.196118093
Short name T28
Test name
Test status
Simulation time 13764000000 ps
CPU time 51.61 seconds
Started May 28 01:10:20 PM PDT 24
Finished May 28 01:12:03 PM PDT 24
Peak memory 144980 kb
Host smart-ea656459-b6d2-43a8-9fd9-5beea9482e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196118093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.196118093
Directory /workspace/35.prim_present_test/latest


Test location /workspace/coverage/default/36.prim_present_test.3459056901
Short name T13
Test name
Test status
Simulation time 11120940000 ps
CPU time 41.3 seconds
Started May 28 01:10:15 PM PDT 24
Finished May 28 01:11:41 PM PDT 24
Peak memory 145176 kb
Host smart-d3c205c8-dfd1-4d33-ba20-90870cddf72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459056901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3459056901
Directory /workspace/36.prim_present_test/latest


Test location /workspace/coverage/default/37.prim_present_test.1253023636
Short name T37
Test name
Test status
Simulation time 3238880000 ps
CPU time 10.18 seconds
Started May 28 01:10:12 PM PDT 24
Finished May 28 01:10:42 PM PDT 24
Peak memory 145012 kb
Host smart-20411b43-53d9-4b22-a53c-eb373c8c185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253023636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1253023636
Directory /workspace/37.prim_present_test/latest


Test location /workspace/coverage/default/38.prim_present_test.1728618919
Short name T46
Test name
Test status
Simulation time 12819120000 ps
CPU time 49.07 seconds
Started May 28 01:10:19 PM PDT 24
Finished May 28 01:11:57 PM PDT 24
Peak memory 144960 kb
Host smart-c2dd073d-7a82-4d41-907c-e95f318d4b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728618919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1728618919
Directory /workspace/38.prim_present_test/latest


Test location /workspace/coverage/default/39.prim_present_test.2207049414
Short name T49
Test name
Test status
Simulation time 15141020000 ps
CPU time 51.41 seconds
Started May 28 01:10:12 PM PDT 24
Finished May 28 01:11:56 PM PDT 24
Peak memory 145136 kb
Host smart-dd21802a-6c8f-4dce-ae2a-9fc872038179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207049414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2207049414
Directory /workspace/39.prim_present_test/latest


Test location /workspace/coverage/default/4.prim_present_test.524696579
Short name T10
Test name
Test status
Simulation time 14881860000 ps
CPU time 58.01 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:12:08 PM PDT 24
Peak memory 145048 kb
Host smart-e6327be7-cc1c-4c3f-85e8-80faaf47059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524696579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.524696579
Directory /workspace/4.prim_present_test/latest


Test location /workspace/coverage/default/40.prim_present_test.3547445202
Short name T31
Test name
Test status
Simulation time 13248160000 ps
CPU time 44.17 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:11:43 PM PDT 24
Peak memory 145076 kb
Host smart-e0757433-d114-42b6-af19-f79b9f17548d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547445202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3547445202
Directory /workspace/40.prim_present_test/latest


Test location /workspace/coverage/default/41.prim_present_test.1243240163
Short name T12
Test name
Test status
Simulation time 7426980000 ps
CPU time 26.73 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:11:03 PM PDT 24
Peak memory 145076 kb
Host smart-7b4a3afd-4b5f-4f13-be48-86e38b6f9d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243240163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1243240163
Directory /workspace/41.prim_present_test/latest


Test location /workspace/coverage/default/42.prim_present_test.562618272
Short name T42
Test name
Test status
Simulation time 12049700000 ps
CPU time 44.11 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:11:37 PM PDT 24
Peak memory 145176 kb
Host smart-8f6907fa-1eb2-414e-922d-1da6d0485fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562618272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.562618272
Directory /workspace/42.prim_present_test/latest


Test location /workspace/coverage/default/43.prim_present_test.2388786118
Short name T27
Test name
Test status
Simulation time 14542720000 ps
CPU time 62.28 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:12:25 PM PDT 24
Peak memory 145160 kb
Host smart-b13ca663-1674-4136-a83b-c371024d3186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388786118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2388786118
Directory /workspace/43.prim_present_test/latest


Test location /workspace/coverage/default/44.prim_present_test.272913313
Short name T45
Test name
Test status
Simulation time 5799480000 ps
CPU time 23.73 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:59 PM PDT 24
Peak memory 145096 kb
Host smart-978e0242-2bc4-49f4-8641-375fcabf49bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272913313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.272913313
Directory /workspace/44.prim_present_test/latest


Test location /workspace/coverage/default/45.prim_present_test.1557966016
Short name T11
Test name
Test status
Simulation time 7715900000 ps
CPU time 31.82 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:11:14 PM PDT 24
Peak memory 145080 kb
Host smart-4700caea-5a8f-48b3-8e76-d556a0cdd320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557966016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1557966016
Directory /workspace/45.prim_present_test/latest


Test location /workspace/coverage/default/46.prim_present_test.2541534132
Short name T29
Test name
Test status
Simulation time 4036820000 ps
CPU time 15.89 seconds
Started May 28 01:10:12 PM PDT 24
Finished May 28 01:10:51 PM PDT 24
Peak memory 145008 kb
Host smart-5c747f93-2129-4d99-b185-96b97d1d4a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541534132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2541534132
Directory /workspace/46.prim_present_test/latest


Test location /workspace/coverage/default/47.prim_present_test.2378994687
Short name T18
Test name
Test status
Simulation time 12629400000 ps
CPU time 53.74 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:12:09 PM PDT 24
Peak memory 145156 kb
Host smart-58d86c6c-f4b8-42c5-9441-cb85c436354b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378994687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2378994687
Directory /workspace/47.prim_present_test/latest


Test location /workspace/coverage/default/48.prim_present_test.3822429390
Short name T22
Test name
Test status
Simulation time 7087220000 ps
CPU time 28.06 seconds
Started May 28 01:10:16 PM PDT 24
Finished May 28 01:11:18 PM PDT 24
Peak memory 145156 kb
Host smart-5c5b39fe-283d-40f1-b734-25b16b3de0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822429390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3822429390
Directory /workspace/48.prim_present_test/latest


Test location /workspace/coverage/default/49.prim_present_test.4191000583
Short name T34
Test name
Test status
Simulation time 6325860000 ps
CPU time 25.59 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:11:05 PM PDT 24
Peak memory 145156 kb
Host smart-08d8706e-8a6b-416b-b8df-bf145cd56b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191000583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4191000583
Directory /workspace/49.prim_present_test/latest


Test location /workspace/coverage/default/5.prim_present_test.1303424877
Short name T50
Test name
Test status
Simulation time 6468460000 ps
CPU time 22.52 seconds
Started May 28 01:10:20 PM PDT 24
Finished May 28 01:11:10 PM PDT 24
Peak memory 145184 kb
Host smart-625fedf7-013b-4e07-9df2-5dacf5e5e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303424877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1303424877
Directory /workspace/5.prim_present_test/latest


Test location /workspace/coverage/default/6.prim_present_test.419053969
Short name T38
Test name
Test status
Simulation time 10218840000 ps
CPU time 41.26 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:11:35 PM PDT 24
Peak memory 145048 kb
Host smart-119fd26f-613a-498b-8d5f-4bfa4849bbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419053969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.419053969
Directory /workspace/6.prim_present_test/latest


Test location /workspace/coverage/default/7.prim_present_test.2377843824
Short name T25
Test name
Test status
Simulation time 5532260000 ps
CPU time 21.4 seconds
Started May 28 01:10:19 PM PDT 24
Finished May 28 01:11:05 PM PDT 24
Peak memory 144972 kb
Host smart-63915ba0-08ba-4562-a2ba-0928428e7690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377843824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2377843824
Directory /workspace/7.prim_present_test/latest


Test location /workspace/coverage/default/8.prim_present_test.306132584
Short name T6
Test name
Test status
Simulation time 5971220000 ps
CPU time 23.08 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:11:00 PM PDT 24
Peak memory 145096 kb
Host smart-b9c74b1e-7349-41d0-a61e-d28d82a9d27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306132584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.306132584
Directory /workspace/8.prim_present_test/latest


Test location /workspace/coverage/default/9.prim_present_test.3632308627
Short name T30
Test name
Test status
Simulation time 5973700000 ps
CPU time 19.56 seconds
Started May 28 01:10:18 PM PDT 24
Finished May 28 01:11:01 PM PDT 24
Peak memory 145184 kb
Host smart-75bc3f61-8b38-41a0-9e81-20b2844e11be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632308627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3632308627
Directory /workspace/9.prim_present_test/latest
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