| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.1909113626 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.2752431246 |
| /workspace/coverage/default/10.prim_present_test.595817130 |
| /workspace/coverage/default/11.prim_present_test.2134645564 |
| /workspace/coverage/default/12.prim_present_test.1188304106 |
| /workspace/coverage/default/13.prim_present_test.2387673769 |
| /workspace/coverage/default/14.prim_present_test.2619373056 |
| /workspace/coverage/default/15.prim_present_test.171753224 |
| /workspace/coverage/default/16.prim_present_test.3204478607 |
| /workspace/coverage/default/17.prim_present_test.4276528131 |
| /workspace/coverage/default/18.prim_present_test.1766996484 |
| /workspace/coverage/default/19.prim_present_test.2389814978 |
| /workspace/coverage/default/2.prim_present_test.3875906884 |
| /workspace/coverage/default/20.prim_present_test.1281025125 |
| /workspace/coverage/default/21.prim_present_test.3218832551 |
| /workspace/coverage/default/22.prim_present_test.1246126264 |
| /workspace/coverage/default/23.prim_present_test.2220235787 |
| /workspace/coverage/default/24.prim_present_test.4083720550 |
| /workspace/coverage/default/25.prim_present_test.639501181 |
| /workspace/coverage/default/26.prim_present_test.436579210 |
| /workspace/coverage/default/27.prim_present_test.413621600 |
| /workspace/coverage/default/28.prim_present_test.1124847420 |
| /workspace/coverage/default/29.prim_present_test.3948786204 |
| /workspace/coverage/default/3.prim_present_test.3377424198 |
| /workspace/coverage/default/30.prim_present_test.2354153299 |
| /workspace/coverage/default/31.prim_present_test.492905331 |
| /workspace/coverage/default/32.prim_present_test.2566937467 |
| /workspace/coverage/default/33.prim_present_test.212172967 |
| /workspace/coverage/default/34.prim_present_test.3011590824 |
| /workspace/coverage/default/35.prim_present_test.135865011 |
| /workspace/coverage/default/36.prim_present_test.3266037759 |
| /workspace/coverage/default/37.prim_present_test.431867872 |
| /workspace/coverage/default/38.prim_present_test.3076550219 |
| /workspace/coverage/default/39.prim_present_test.1332604466 |
| /workspace/coverage/default/4.prim_present_test.3451666873 |
| /workspace/coverage/default/40.prim_present_test.1066645473 |
| /workspace/coverage/default/41.prim_present_test.2190055284 |
| /workspace/coverage/default/42.prim_present_test.3977859297 |
| /workspace/coverage/default/43.prim_present_test.647308758 |
| /workspace/coverage/default/44.prim_present_test.1942327414 |
| /workspace/coverage/default/45.prim_present_test.1906485583 |
| /workspace/coverage/default/46.prim_present_test.942591733 |
| /workspace/coverage/default/47.prim_present_test.2794492303 |
| /workspace/coverage/default/48.prim_present_test.1417828449 |
| /workspace/coverage/default/49.prim_present_test.3982213854 |
| /workspace/coverage/default/5.prim_present_test.511545903 |
| /workspace/coverage/default/6.prim_present_test.183877809 |
| /workspace/coverage/default/7.prim_present_test.3760604426 |
| /workspace/coverage/default/8.prim_present_test.493070438 |
| /workspace/coverage/default/9.prim_present_test.338622081 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/19.prim_present_test.2389814978 | May 30 12:30:50 PM PDT 24 | May 30 12:32:17 PM PDT 24 | 14845900000 ps | ||
| T2 | /workspace/coverage/default/18.prim_present_test.1766996484 | May 30 12:30:49 PM PDT 24 | May 30 12:31:22 PM PDT 24 | 5126160000 ps | ||
| T3 | /workspace/coverage/default/2.prim_present_test.3875906884 | May 30 12:31:02 PM PDT 24 | May 30 12:31:50 PM PDT 24 | 6361820000 ps | ||
| T4 | /workspace/coverage/default/44.prim_present_test.1942327414 | May 30 12:31:10 PM PDT 24 | May 30 12:32:25 PM PDT 24 | 11959180000 ps | ||
| T5 | /workspace/coverage/default/34.prim_present_test.3011590824 | May 30 12:31:09 PM PDT 24 | May 30 12:32:41 PM PDT 24 | 13103080000 ps | ||
| T6 | /workspace/coverage/default/33.prim_present_test.212172967 | May 30 12:31:10 PM PDT 24 | May 30 12:31:32 PM PDT 24 | 3163860000 ps | ||
| T7 | /workspace/coverage/default/5.prim_present_test.511545903 | May 30 12:30:48 PM PDT 24 | May 30 12:32:08 PM PDT 24 | 12933200000 ps | ||
| T8 | /workspace/coverage/default/20.prim_present_test.1281025125 | May 30 12:31:02 PM PDT 24 | May 30 12:31:45 PM PDT 24 | 5618440000 ps | ||
| T9 | /workspace/coverage/default/15.prim_present_test.171753224 | May 30 12:30:55 PM PDT 24 | May 30 12:31:45 PM PDT 24 | 6842320000 ps | ||
| T10 | /workspace/coverage/default/0.prim_present_test.1909113626 | May 30 12:31:07 PM PDT 24 | May 30 12:31:38 PM PDT 24 | 4206080000 ps | ||
| T11 | /workspace/coverage/default/4.prim_present_test.3451666873 | May 30 12:30:53 PM PDT 24 | May 30 12:32:25 PM PDT 24 | 14849000000 ps | ||
| T12 | /workspace/coverage/default/11.prim_present_test.2134645564 | May 30 12:30:51 PM PDT 24 | May 30 12:31:25 PM PDT 24 | 5487000000 ps | ||
| T13 | /workspace/coverage/default/36.prim_present_test.3266037759 | May 30 12:31:13 PM PDT 24 | May 30 12:32:45 PM PDT 24 | 14857060000 ps | ||
| T14 | /workspace/coverage/default/12.prim_present_test.1188304106 | May 30 12:30:48 PM PDT 24 | May 30 12:31:35 PM PDT 24 | 6947720000 ps | ||
| T15 | /workspace/coverage/default/10.prim_present_test.595817130 | May 30 12:31:04 PM PDT 24 | May 30 12:32:10 PM PDT 24 | 11260440000 ps | ||
| T16 | /workspace/coverage/default/7.prim_present_test.3760604426 | May 30 12:31:08 PM PDT 24 | May 30 12:32:13 PM PDT 24 | 11120940000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.1332604466 | May 30 12:31:08 PM PDT 24 | May 30 12:32:43 PM PDT 24 | 14820480000 ps | ||
| T18 | /workspace/coverage/default/22.prim_present_test.1246126264 | May 30 12:30:48 PM PDT 24 | May 30 12:32:16 PM PDT 24 | 15242700000 ps | ||
| T19 | /workspace/coverage/default/26.prim_present_test.436579210 | May 30 12:30:48 PM PDT 24 | May 30 12:31:07 PM PDT 24 | 3116740000 ps | ||
| T20 | /workspace/coverage/default/23.prim_present_test.2220235787 | May 30 12:31:09 PM PDT 24 | May 30 12:32:29 PM PDT 24 | 14831640000 ps | ||
| T21 | /workspace/coverage/default/16.prim_present_test.3204478607 | May 30 12:31:07 PM PDT 24 | May 30 12:32:13 PM PDT 24 | 9399820000 ps | ||
| T22 | /workspace/coverage/default/35.prim_present_test.135865011 | May 30 12:31:11 PM PDT 24 | May 30 12:31:51 PM PDT 24 | 6994840000 ps | ||
| T23 | /workspace/coverage/default/8.prim_present_test.493070438 | May 30 12:31:00 PM PDT 24 | May 30 12:32:36 PM PDT 24 | 14306500000 ps | ||
| T24 | /workspace/coverage/default/3.prim_present_test.3377424198 | May 30 12:31:01 PM PDT 24 | May 30 12:31:38 PM PDT 24 | 5153440000 ps | ||
| T25 | /workspace/coverage/default/46.prim_present_test.942591733 | May 30 12:31:05 PM PDT 24 | May 30 12:32:02 PM PDT 24 | 8374960000 ps | ||
| T26 | /workspace/coverage/default/1.prim_present_test.2752431246 | May 30 12:30:43 PM PDT 24 | May 30 12:31:07 PM PDT 24 | 3742320000 ps | ||
| T27 | /workspace/coverage/default/40.prim_present_test.1066645473 | May 30 12:31:08 PM PDT 24 | May 30 12:31:44 PM PDT 24 | 5013940000 ps | ||
| T28 | /workspace/coverage/default/29.prim_present_test.3948786204 | May 30 12:31:03 PM PDT 24 | May 30 12:31:28 PM PDT 24 | 4156480000 ps | ||
| T29 | /workspace/coverage/default/27.prim_present_test.413621600 | May 30 12:31:08 PM PDT 24 | May 30 12:31:44 PM PDT 24 | 6555260000 ps | ||
| T30 | /workspace/coverage/default/32.prim_present_test.2566937467 | May 30 12:31:07 PM PDT 24 | May 30 12:31:45 PM PDT 24 | 6526120000 ps | ||
| T31 | /workspace/coverage/default/43.prim_present_test.647308758 | May 30 12:31:09 PM PDT 24 | May 30 12:31:45 PM PDT 24 | 6538520000 ps | ||
| T32 | /workspace/coverage/default/25.prim_present_test.639501181 | May 30 12:30:49 PM PDT 24 | May 30 12:31:12 PM PDT 24 | 3517880000 ps | ||
| T33 | /workspace/coverage/default/13.prim_present_test.2387673769 | May 30 12:31:01 PM PDT 24 | May 30 12:32:16 PM PDT 24 | 10638580000 ps | ||
| T34 | /workspace/coverage/default/37.prim_present_test.431867872 | May 30 12:31:09 PM PDT 24 | May 30 12:32:15 PM PDT 24 | 11608880000 ps | ||
| T35 | /workspace/coverage/default/49.prim_present_test.3982213854 | May 30 12:31:06 PM PDT 24 | May 30 12:31:59 PM PDT 24 | 7643980000 ps | ||
| T36 | /workspace/coverage/default/47.prim_present_test.2794492303 | May 30 12:31:09 PM PDT 24 | May 30 12:32:34 PM PDT 24 | 14080200000 ps | ||
| T37 | /workspace/coverage/default/30.prim_present_test.2354153299 | May 30 12:31:07 PM PDT 24 | May 30 12:32:33 PM PDT 24 | 13146480000 ps | ||
| T38 | /workspace/coverage/default/14.prim_present_test.2619373056 | May 30 12:31:03 PM PDT 24 | May 30 12:31:55 PM PDT 24 | 9002400000 ps | ||
| T39 | /workspace/coverage/default/9.prim_present_test.338622081 | May 30 12:30:59 PM PDT 24 | May 30 12:31:41 PM PDT 24 | 6971900000 ps | ||
| T40 | /workspace/coverage/default/38.prim_present_test.3076550219 | May 30 12:30:56 PM PDT 24 | May 30 12:32:15 PM PDT 24 | 15390880000 ps | ||
| T41 | /workspace/coverage/default/42.prim_present_test.3977859297 | May 30 12:31:01 PM PDT 24 | May 30 12:31:23 PM PDT 24 | 3729300000 ps | ||
| T42 | /workspace/coverage/default/24.prim_present_test.4083720550 | May 30 12:31:06 PM PDT 24 | May 30 12:32:21 PM PDT 24 | 11193480000 ps | ||
| T43 | /workspace/coverage/default/41.prim_present_test.2190055284 | May 30 12:31:08 PM PDT 24 | May 30 12:32:29 PM PDT 24 | 12859420000 ps | ||
| T44 | /workspace/coverage/default/6.prim_present_test.183877809 | May 30 12:31:06 PM PDT 24 | May 30 12:31:40 PM PDT 24 | 5664940000 ps | ||
| T45 | /workspace/coverage/default/28.prim_present_test.1124847420 | May 30 12:31:03 PM PDT 24 | May 30 12:32:25 PM PDT 24 | 13617060000 ps | ||
| T46 | /workspace/coverage/default/17.prim_present_test.4276528131 | May 30 12:30:54 PM PDT 24 | May 30 12:31:57 PM PDT 24 | 10908900000 ps | ||
| T47 | /workspace/coverage/default/21.prim_present_test.3218832551 | May 30 12:30:55 PM PDT 24 | May 30 12:31:41 PM PDT 24 | 7299260000 ps | ||
| T48 | /workspace/coverage/default/48.prim_present_test.1417828449 | May 30 12:31:05 PM PDT 24 | May 30 12:32:18 PM PDT 24 | 12826560000 ps | ||
| T49 | /workspace/coverage/default/31.prim_present_test.492905331 | May 30 12:31:07 PM PDT 24 | May 30 12:32:31 PM PDT 24 | 13678440000 ps | ||
| T50 | /workspace/coverage/default/45.prim_present_test.1906485583 | May 30 12:30:58 PM PDT 24 | May 30 12:32:07 PM PDT 24 | 11670260000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.1909113626 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4206080000 ps |
| CPU time | 16.2 seconds |
| Started | May 30 12:31:07 PM PDT 24 |
| Finished | May 30 12:31:38 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-0d661763-3b73-4a39-96bc-3a5c1f1d3a16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909113626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1909113626 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2752431246 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3742320000 ps |
| CPU time | 12.33 seconds |
| Started | May 30 12:30:43 PM PDT 24 |
| Finished | May 30 12:31:07 PM PDT 24 |
| Peak memory | 144680 kb |
| Host | smart-500a467f-baf4-4518-b3c7-39016ce8263b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752431246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2752431246 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.595817130 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11260440000 ps |
| CPU time | 35.08 seconds |
| Started | May 30 12:31:04 PM PDT 24 |
| Finished | May 30 12:32:10 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-df0d5f31-3207-4c5e-b86e-6cf8e1dda6b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595817130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.595817130 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2134645564 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5487000000 ps |
| CPU time | 17.86 seconds |
| Started | May 30 12:30:51 PM PDT 24 |
| Finished | May 30 12:31:25 PM PDT 24 |
| Peak memory | 144808 kb |
| Host | smart-bf4b5cd1-84bd-4ada-be83-ca85565721dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134645564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2134645564 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1188304106 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6947720000 ps |
| CPU time | 24.89 seconds |
| Started | May 30 12:30:48 PM PDT 24 |
| Finished | May 30 12:31:35 PM PDT 24 |
| Peak memory | 144768 kb |
| Host | smart-e4bd6aa9-9722-4ba8-abfd-af52db4269d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188304106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1188304106 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2387673769 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10638580000 ps |
| CPU time | 38.78 seconds |
| Started | May 30 12:31:01 PM PDT 24 |
| Finished | May 30 12:32:16 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-0b4c457d-5d63-43b0-9d7f-68b6bb8ad16e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387673769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2387673769 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2619373056 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9002400000 ps |
| CPU time | 28.02 seconds |
| Started | May 30 12:31:03 PM PDT 24 |
| Finished | May 30 12:31:55 PM PDT 24 |
| Peak memory | 144788 kb |
| Host | smart-10f9bea3-e991-4471-a29f-9a5114b019cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619373056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2619373056 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.171753224 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6842320000 ps |
| CPU time | 26.36 seconds |
| Started | May 30 12:30:55 PM PDT 24 |
| Finished | May 30 12:31:45 PM PDT 24 |
| Peak memory | 144764 kb |
| Host | smart-3cd0fd8b-9653-4d1e-b2de-cebf69df5c17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171753224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.171753224 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3204478607 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9399820000 ps |
| CPU time | 34.09 seconds |
| Started | May 30 12:31:07 PM PDT 24 |
| Finished | May 30 12:32:13 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-9df6d849-d827-4de0-9784-eb77978f78ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204478607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3204478607 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4276528131 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10908900000 ps |
| CPU time | 33.4 seconds |
| Started | May 30 12:30:54 PM PDT 24 |
| Finished | May 30 12:31:57 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-8d5f4ded-2bab-48dd-9070-06ba3bb8ddfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276528131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4276528131 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1766996484 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5126160000 ps |
| CPU time | 17.53 seconds |
| Started | May 30 12:30:49 PM PDT 24 |
| Finished | May 30 12:31:22 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-194bbad1-f7d3-4d39-96ad-e51b18b2fdd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1766996484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1766996484 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2389814978 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14845900000 ps |
| CPU time | 46.38 seconds |
| Started | May 30 12:30:50 PM PDT 24 |
| Finished | May 30 12:32:17 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-dd62c0d4-45d9-4e00-a00d-8fb4a3f0e180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389814978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2389814978 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3875906884 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6361820000 ps |
| CPU time | 24.23 seconds |
| Started | May 30 12:31:02 PM PDT 24 |
| Finished | May 30 12:31:50 PM PDT 24 |
| Peak memory | 144764 kb |
| Host | smart-33cd33bd-be8b-4a48-b839-1919e8a30476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875906884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3875906884 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1281025125 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5618440000 ps |
| CPU time | 21.94 seconds |
| Started | May 30 12:31:02 PM PDT 24 |
| Finished | May 30 12:31:45 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-d0b086f8-741c-4573-8d66-fc9d8054e5e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281025125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1281025125 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3218832551 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7299260000 ps |
| CPU time | 24.7 seconds |
| Started | May 30 12:30:55 PM PDT 24 |
| Finished | May 30 12:31:41 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-dba3332e-a296-4423-8ece-9f09f84bc12c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218832551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3218832551 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1246126264 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15242700000 ps |
| CPU time | 46.71 seconds |
| Started | May 30 12:30:48 PM PDT 24 |
| Finished | May 30 12:32:16 PM PDT 24 |
| Peak memory | 144792 kb |
| Host | smart-e87ff528-4ef5-4b3c-9d6e-c090e195a98a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246126264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1246126264 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2220235787 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14831640000 ps |
| CPU time | 43.5 seconds |
| Started | May 30 12:31:09 PM PDT 24 |
| Finished | May 30 12:32:29 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-a3cdc616-5774-4805-b06e-d0de4173c25c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220235787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2220235787 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4083720550 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11193480000 ps |
| CPU time | 38.93 seconds |
| Started | May 30 12:31:06 PM PDT 24 |
| Finished | May 30 12:32:21 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-3880b0e2-f1d1-49f6-a0ec-b301f117cd16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083720550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4083720550 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.639501181 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3517880000 ps |
| CPU time | 11.77 seconds |
| Started | May 30 12:30:49 PM PDT 24 |
| Finished | May 30 12:31:12 PM PDT 24 |
| Peak memory | 144680 kb |
| Host | smart-62841385-27b7-44f2-8fc1-31e100336108 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=639501181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.639501181 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.436579210 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3116740000 ps |
| CPU time | 10.31 seconds |
| Started | May 30 12:30:48 PM PDT 24 |
| Finished | May 30 12:31:07 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-6e9aab1e-d85e-4481-b79c-17763b1dfd33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436579210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.436579210 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.413621600 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6555260000 ps |
| CPU time | 19.66 seconds |
| Started | May 30 12:31:08 PM PDT 24 |
| Finished | May 30 12:31:44 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-b63736f2-9634-4ea6-9987-57f1632e6191 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=413621600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.413621600 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1124847420 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13617060000 ps |
| CPU time | 43.47 seconds |
| Started | May 30 12:31:03 PM PDT 24 |
| Finished | May 30 12:32:25 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-65f66955-c534-4937-bd7f-1fce00ab744f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124847420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1124847420 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3948786204 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4156480000 ps |
| CPU time | 12.83 seconds |
| Started | May 30 12:31:03 PM PDT 24 |
| Finished | May 30 12:31:28 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-92af828d-f23a-49bd-a443-21124e70a44f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948786204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3948786204 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3377424198 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5153440000 ps |
| CPU time | 18.89 seconds |
| Started | May 30 12:31:01 PM PDT 24 |
| Finished | May 30 12:31:38 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-cd5c3303-4ed8-4001-b90c-db2e0436ad33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377424198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3377424198 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2354153299 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13146480000 ps |
| CPU time | 44.31 seconds |
| Started | May 30 12:31:07 PM PDT 24 |
| Finished | May 30 12:32:33 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-ad426500-e174-4a68-85bf-6bb81ed548f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354153299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2354153299 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.492905331 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13678440000 ps |
| CPU time | 44.98 seconds |
| Started | May 30 12:31:07 PM PDT 24 |
| Finished | May 30 12:32:31 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-275175cc-0283-4594-905e-3a08d8900e18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=492905331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.492905331 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2566937467 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6526120000 ps |
| CPU time | 19.99 seconds |
| Started | May 30 12:31:07 PM PDT 24 |
| Finished | May 30 12:31:45 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-5a26cba4-0e06-46d3-9901-97ed94facdcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2566937467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2566937467 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.212172967 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3163860000 ps |
| CPU time | 11.66 seconds |
| Started | May 30 12:31:10 PM PDT 24 |
| Finished | May 30 12:31:32 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-c8adde90-4d84-425e-aeae-a87405d68ba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=212172967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.212172967 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3011590824 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13103080000 ps |
| CPU time | 47.39 seconds |
| Started | May 30 12:31:09 PM PDT 24 |
| Finished | May 30 12:32:41 PM PDT 24 |
| Peak memory | 144756 kb |
| Host | smart-85d40a1b-80df-4008-b799-6db835f08c1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011590824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3011590824 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.135865011 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6994840000 ps |
| CPU time | 21.21 seconds |
| Started | May 30 12:31:11 PM PDT 24 |
| Finished | May 30 12:31:51 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-813be5d6-ab70-4079-9740-2f590880f5a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135865011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.135865011 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3266037759 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14857060000 ps |
| CPU time | 48.47 seconds |
| Started | May 30 12:31:13 PM PDT 24 |
| Finished | May 30 12:32:45 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-091a41c4-fe7c-4071-a052-a84aef5a497e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266037759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3266037759 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.431867872 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11608880000 ps |
| CPU time | 35.18 seconds |
| Started | May 30 12:31:09 PM PDT 24 |
| Finished | May 30 12:32:15 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-a7db0540-8209-48d3-ae45-29f57cf94b29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431867872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.431867872 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3076550219 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15390880000 ps |
| CPU time | 42.77 seconds |
| Started | May 30 12:30:56 PM PDT 24 |
| Finished | May 30 12:32:15 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-10b1e1e6-8712-4095-8307-85f18ce72203 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3076550219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3076550219 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1332604466 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14820480000 ps |
| CPU time | 50.63 seconds |
| Started | May 30 12:31:08 PM PDT 24 |
| Finished | May 30 12:32:43 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-3e968ef9-2d0d-4271-afee-ceb90bc8975f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332604466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1332604466 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3451666873 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14849000000 ps |
| CPU time | 48.27 seconds |
| Started | May 30 12:30:53 PM PDT 24 |
| Finished | May 30 12:32:25 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-1df9d4c1-07a8-4ed4-abc1-5e95dcbf5a70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451666873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3451666873 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1066645473 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5013940000 ps |
| CPU time | 19.08 seconds |
| Started | May 30 12:31:08 PM PDT 24 |
| Finished | May 30 12:31:44 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-e40517f7-ada5-4fa3-bdd2-5ef183f2238c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066645473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1066645473 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2190055284 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12859420000 ps |
| CPU time | 42.59 seconds |
| Started | May 30 12:31:08 PM PDT 24 |
| Finished | May 30 12:32:29 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-39e4d14f-54e7-4246-98c2-547900cd7396 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190055284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2190055284 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3977859297 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3729300000 ps |
| CPU time | 11.31 seconds |
| Started | May 30 12:31:01 PM PDT 24 |
| Finished | May 30 12:31:23 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-ed78a707-b012-4c81-81e3-64ee86080bde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977859297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3977859297 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.647308758 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6538520000 ps |
| CPU time | 19.22 seconds |
| Started | May 30 12:31:09 PM PDT 24 |
| Finished | May 30 12:31:45 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-c38007ed-ba65-433d-8647-e445d6f6ae60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647308758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.647308758 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1942327414 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11959180000 ps |
| CPU time | 39.57 seconds |
| Started | May 30 12:31:10 PM PDT 24 |
| Finished | May 30 12:32:25 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-736cb72e-7557-4678-8234-52f3555c9d11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942327414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1942327414 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1906485583 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11670260000 ps |
| CPU time | 36.92 seconds |
| Started | May 30 12:30:58 PM PDT 24 |
| Finished | May 30 12:32:07 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-c4074fb5-6ff5-44b0-a239-52d5ef92c0c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906485583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1906485583 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.942591733 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8374960000 ps |
| CPU time | 29.58 seconds |
| Started | May 30 12:31:05 PM PDT 24 |
| Finished | May 30 12:32:02 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-303b7b40-8372-4841-a05c-aa04b8217930 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=942591733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.942591733 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2794492303 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14080200000 ps |
| CPU time | 45.2 seconds |
| Started | May 30 12:31:09 PM PDT 24 |
| Finished | May 30 12:32:34 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-eca546a0-7ee2-4f41-bfe7-d4f455de434c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794492303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2794492303 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1417828449 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12826560000 ps |
| CPU time | 38.94 seconds |
| Started | May 30 12:31:05 PM PDT 24 |
| Finished | May 30 12:32:18 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-667614fb-2348-412f-9b53-25abf64cdf0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417828449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1417828449 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3982213854 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7643980000 ps |
| CPU time | 27.1 seconds |
| Started | May 30 12:31:06 PM PDT 24 |
| Finished | May 30 12:31:59 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-edc66f96-69cb-46a8-b020-897b005476fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982213854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3982213854 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.511545903 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12933200000 ps |
| CPU time | 42.46 seconds |
| Started | May 30 12:30:48 PM PDT 24 |
| Finished | May 30 12:32:08 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-023dba9e-ad3d-42b2-ad59-e7078eaf78ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511545903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.511545903 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.183877809 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5664940000 ps |
| CPU time | 17.58 seconds |
| Started | May 30 12:31:06 PM PDT 24 |
| Finished | May 30 12:31:40 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-a8100df7-a0df-483e-b6f1-5b75ad11b316 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183877809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.183877809 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3760604426 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11120940000 ps |
| CPU time | 34.36 seconds |
| Started | May 30 12:31:08 PM PDT 24 |
| Finished | May 30 12:32:13 PM PDT 24 |
| Peak memory | 144796 kb |
| Host | smart-734dcd54-9cc0-4b55-8e8a-fbd1aeb5a54e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760604426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3760604426 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.493070438 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14306500000 ps |
| CPU time | 50.71 seconds |
| Started | May 30 12:31:00 PM PDT 24 |
| Finished | May 30 12:32:36 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-f01c3e57-cbdc-470e-b6cf-4cce71308daf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493070438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.493070438 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.338622081 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6971900000 ps |
| CPU time | 21.85 seconds |
| Started | May 30 12:30:59 PM PDT 24 |
| Finished | May 30 12:31:41 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-66ea3fa9-f3e1-4e4d-97b6-1fb12f35059c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338622081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.338622081 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |