| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.943241734 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.461825050 |
| /workspace/coverage/default/10.prim_present_test.2620981840 |
| /workspace/coverage/default/11.prim_present_test.3297350379 |
| /workspace/coverage/default/12.prim_present_test.3837409365 |
| /workspace/coverage/default/13.prim_present_test.3946080695 |
| /workspace/coverage/default/14.prim_present_test.4245858848 |
| /workspace/coverage/default/15.prim_present_test.1008655856 |
| /workspace/coverage/default/16.prim_present_test.2803744077 |
| /workspace/coverage/default/17.prim_present_test.3928485386 |
| /workspace/coverage/default/18.prim_present_test.1348269285 |
| /workspace/coverage/default/19.prim_present_test.2801695692 |
| /workspace/coverage/default/2.prim_present_test.1071672345 |
| /workspace/coverage/default/20.prim_present_test.3491079677 |
| /workspace/coverage/default/21.prim_present_test.598715438 |
| /workspace/coverage/default/22.prim_present_test.2646984855 |
| /workspace/coverage/default/23.prim_present_test.3028854578 |
| /workspace/coverage/default/24.prim_present_test.2321206795 |
| /workspace/coverage/default/25.prim_present_test.3427685947 |
| /workspace/coverage/default/26.prim_present_test.3558877348 |
| /workspace/coverage/default/27.prim_present_test.146922111 |
| /workspace/coverage/default/28.prim_present_test.2666996784 |
| /workspace/coverage/default/29.prim_present_test.2819968230 |
| /workspace/coverage/default/3.prim_present_test.2002777713 |
| /workspace/coverage/default/30.prim_present_test.534822293 |
| /workspace/coverage/default/31.prim_present_test.3600649310 |
| /workspace/coverage/default/32.prim_present_test.4113616032 |
| /workspace/coverage/default/33.prim_present_test.526921618 |
| /workspace/coverage/default/34.prim_present_test.122643306 |
| /workspace/coverage/default/35.prim_present_test.895483257 |
| /workspace/coverage/default/36.prim_present_test.1189549387 |
| /workspace/coverage/default/37.prim_present_test.3803171420 |
| /workspace/coverage/default/38.prim_present_test.3194488058 |
| /workspace/coverage/default/39.prim_present_test.4249709226 |
| /workspace/coverage/default/4.prim_present_test.1765616637 |
| /workspace/coverage/default/40.prim_present_test.917132511 |
| /workspace/coverage/default/41.prim_present_test.3201699745 |
| /workspace/coverage/default/42.prim_present_test.2542192168 |
| /workspace/coverage/default/43.prim_present_test.190144405 |
| /workspace/coverage/default/44.prim_present_test.1519611954 |
| /workspace/coverage/default/45.prim_present_test.4260088434 |
| /workspace/coverage/default/46.prim_present_test.1838562211 |
| /workspace/coverage/default/47.prim_present_test.365546583 |
| /workspace/coverage/default/48.prim_present_test.2076088903 |
| /workspace/coverage/default/49.prim_present_test.1989992042 |
| /workspace/coverage/default/5.prim_present_test.3126017628 |
| /workspace/coverage/default/6.prim_present_test.3577942469 |
| /workspace/coverage/default/7.prim_present_test.1296500639 |
| /workspace/coverage/default/8.prim_present_test.1253822866 |
| /workspace/coverage/default/9.prim_present_test.3291495952 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_present_test.943241734 | Jun 02 02:08:25 PM PDT 24 | Jun 02 02:09:56 PM PDT 24 | 12829040000 ps | ||
| T2 | /workspace/coverage/default/4.prim_present_test.1765616637 | Jun 02 02:08:27 PM PDT 24 | Jun 02 02:10:12 PM PDT 24 | 13363480000 ps | ||
| T3 | /workspace/coverage/default/8.prim_present_test.1253822866 | Jun 02 02:08:24 PM PDT 24 | Jun 02 02:09:15 PM PDT 24 | 6576340000 ps | ||
| T4 | /workspace/coverage/default/2.prim_present_test.1071672345 | Jun 02 02:08:23 PM PDT 24 | Jun 02 02:09:31 PM PDT 24 | 8363800000 ps | ||
| T5 | /workspace/coverage/default/29.prim_present_test.2819968230 | Jun 02 02:08:33 PM PDT 24 | Jun 02 02:09:30 PM PDT 24 | 7710940000 ps | ||
| T6 | /workspace/coverage/default/42.prim_present_test.2542192168 | Jun 02 02:08:44 PM PDT 24 | Jun 02 02:10:07 PM PDT 24 | 10124600000 ps | ||
| T7 | /workspace/coverage/default/32.prim_present_test.4113616032 | Jun 02 02:08:38 PM PDT 24 | Jun 02 02:10:14 PM PDT 24 | 11719240000 ps | ||
| T8 | /workspace/coverage/default/23.prim_present_test.3028854578 | Jun 02 02:08:33 PM PDT 24 | Jun 02 02:09:13 PM PDT 24 | 7143020000 ps | ||
| T9 | /workspace/coverage/default/43.prim_present_test.190144405 | Jun 02 02:08:45 PM PDT 24 | Jun 02 02:09:34 PM PDT 24 | 6426920000 ps | ||
| T10 | /workspace/coverage/default/33.prim_present_test.526921618 | Jun 02 02:08:39 PM PDT 24 | Jun 02 02:09:15 PM PDT 24 | 5175140000 ps | ||
| T11 | /workspace/coverage/default/11.prim_present_test.3297350379 | Jun 02 02:08:30 PM PDT 24 | Jun 02 02:09:04 PM PDT 24 | 4573120000 ps | ||
| T12 | /workspace/coverage/default/41.prim_present_test.3201699745 | Jun 02 02:08:48 PM PDT 24 | Jun 02 02:09:16 PM PDT 24 | 3567480000 ps | ||
| T13 | /workspace/coverage/default/19.prim_present_test.2801695692 | Jun 02 02:08:29 PM PDT 24 | Jun 02 02:10:09 PM PDT 24 | 12969160000 ps | ||
| T14 | /workspace/coverage/default/3.prim_present_test.2002777713 | Jun 02 02:08:22 PM PDT 24 | Jun 02 02:09:49 PM PDT 24 | 12091860000 ps | ||
| T15 | /workspace/coverage/default/35.prim_present_test.895483257 | Jun 02 02:08:39 PM PDT 24 | Jun 02 02:10:24 PM PDT 24 | 13025580000 ps | ||
| T16 | /workspace/coverage/default/5.prim_present_test.3126017628 | Jun 02 02:08:26 PM PDT 24 | Jun 02 02:09:46 PM PDT 24 | 10444520000 ps | ||
| T17 | /workspace/coverage/default/16.prim_present_test.2803744077 | Jun 02 02:08:28 PM PDT 24 | Jun 02 02:09:34 PM PDT 24 | 9977040000 ps | ||
| T18 | /workspace/coverage/default/9.prim_present_test.3291495952 | Jun 02 02:08:23 PM PDT 24 | Jun 02 02:09:58 PM PDT 24 | 11071340000 ps | ||
| T19 | /workspace/coverage/default/28.prim_present_test.2666996784 | Jun 02 02:08:34 PM PDT 24 | Jun 02 02:10:08 PM PDT 24 | 13004500000 ps | ||
| T20 | /workspace/coverage/default/18.prim_present_test.1348269285 | Jun 02 02:08:29 PM PDT 24 | Jun 02 02:09:11 PM PDT 24 | 4999680000 ps | ||
| T21 | /workspace/coverage/default/39.prim_present_test.4249709226 | Jun 02 02:08:39 PM PDT 24 | Jun 02 02:10:17 PM PDT 24 | 13352320000 ps | ||
| T22 | /workspace/coverage/default/7.prim_present_test.1296500639 | Jun 02 02:08:23 PM PDT 24 | Jun 02 02:09:03 PM PDT 24 | 6169000000 ps | ||
| T23 | /workspace/coverage/default/30.prim_present_test.534822293 | Jun 02 02:08:34 PM PDT 24 | Jun 02 02:09:34 PM PDT 24 | 7911200000 ps | ||
| T24 | /workspace/coverage/default/44.prim_present_test.1519611954 | Jun 02 02:08:44 PM PDT 24 | Jun 02 02:10:06 PM PDT 24 | 11217660000 ps | ||
| T25 | /workspace/coverage/default/46.prim_present_test.1838562211 | Jun 02 02:08:49 PM PDT 24 | Jun 02 02:09:48 PM PDT 24 | 8471060000 ps | ||
| T26 | /workspace/coverage/default/36.prim_present_test.1189549387 | Jun 02 02:08:39 PM PDT 24 | Jun 02 02:09:59 PM PDT 24 | 10634860000 ps | ||
| T27 | /workspace/coverage/default/22.prim_present_test.2646984855 | Jun 02 02:08:33 PM PDT 24 | Jun 02 02:10:06 PM PDT 24 | 12161920000 ps | ||
| T28 | /workspace/coverage/default/34.prim_present_test.122643306 | Jun 02 02:08:39 PM PDT 24 | Jun 02 02:09:57 PM PDT 24 | 11316240000 ps | ||
| T29 | /workspace/coverage/default/47.prim_present_test.365546583 | Jun 02 02:08:45 PM PDT 24 | Jun 02 02:09:44 PM PDT 24 | 7214940000 ps | ||
| T30 | /workspace/coverage/default/49.prim_present_test.1989992042 | Jun 02 02:08:45 PM PDT 24 | Jun 02 02:10:20 PM PDT 24 | 14142820000 ps | ||
| T31 | /workspace/coverage/default/25.prim_present_test.3427685947 | Jun 02 02:08:34 PM PDT 24 | Jun 02 02:09:19 PM PDT 24 | 6913000000 ps | ||
| T32 | /workspace/coverage/default/48.prim_present_test.2076088903 | Jun 02 02:08:48 PM PDT 24 | Jun 02 02:10:24 PM PDT 24 | 14796920000 ps | ||
| T33 | /workspace/coverage/default/12.prim_present_test.3837409365 | Jun 02 02:08:27 PM PDT 24 | Jun 02 02:09:06 PM PDT 24 | 5088340000 ps | ||
| T34 | /workspace/coverage/default/20.prim_present_test.3491079677 | Jun 02 02:08:29 PM PDT 24 | Jun 02 02:09:23 PM PDT 24 | 6370500000 ps | ||
| T35 | /workspace/coverage/default/26.prim_present_test.3558877348 | Jun 02 02:08:34 PM PDT 24 | Jun 02 02:10:21 PM PDT 24 | 14346800000 ps | ||
| T36 | /workspace/coverage/default/31.prim_present_test.3600649310 | Jun 02 02:08:38 PM PDT 24 | Jun 02 02:09:52 PM PDT 24 | 10203340000 ps | ||
| T37 | /workspace/coverage/default/24.prim_present_test.2321206795 | Jun 02 02:08:33 PM PDT 24 | Jun 02 02:10:27 PM PDT 24 | 14770880000 ps | ||
| T38 | /workspace/coverage/default/17.prim_present_test.3928485386 | Jun 02 02:08:28 PM PDT 24 | Jun 02 02:09:35 PM PDT 24 | 9489100000 ps | ||
| T39 | /workspace/coverage/default/13.prim_present_test.3946080695 | Jun 02 02:08:29 PM PDT 24 | Jun 02 02:09:07 PM PDT 24 | 4672940000 ps | ||
| T40 | /workspace/coverage/default/37.prim_present_test.3803171420 | Jun 02 02:08:38 PM PDT 24 | Jun 02 02:09:12 PM PDT 24 | 4393940000 ps | ||
| T41 | /workspace/coverage/default/21.prim_present_test.598715438 | Jun 02 02:08:28 PM PDT 24 | Jun 02 02:10:05 PM PDT 24 | 12352880000 ps | ||
| T42 | /workspace/coverage/default/45.prim_present_test.4260088434 | Jun 02 02:08:46 PM PDT 24 | Jun 02 02:10:14 PM PDT 24 | 11499760000 ps | ||
| T43 | /workspace/coverage/default/10.prim_present_test.2620981840 | Jun 02 02:08:24 PM PDT 24 | Jun 02 02:09:58 PM PDT 24 | 11460700000 ps | ||
| T44 | /workspace/coverage/default/40.prim_present_test.917132511 | Jun 02 02:08:39 PM PDT 24 | Jun 02 02:09:28 PM PDT 24 | 5839780000 ps | ||
| T45 | /workspace/coverage/default/15.prim_present_test.1008655856 | Jun 02 02:08:29 PM PDT 24 | Jun 02 02:09:58 PM PDT 24 | 14847140000 ps | ||
| T46 | /workspace/coverage/default/27.prim_present_test.146922111 | Jun 02 02:08:34 PM PDT 24 | Jun 02 02:09:54 PM PDT 24 | 10212640000 ps | ||
| T47 | /workspace/coverage/default/6.prim_present_test.3577942469 | Jun 02 02:08:23 PM PDT 24 | Jun 02 02:10:06 PM PDT 24 | 13223360000 ps | ||
| T48 | /workspace/coverage/default/14.prim_present_test.4245858848 | Jun 02 02:08:28 PM PDT 24 | Jun 02 02:09:32 PM PDT 24 | 8027760000 ps | ||
| T49 | /workspace/coverage/default/1.prim_present_test.461825050 | Jun 02 02:08:23 PM PDT 24 | Jun 02 02:10:07 PM PDT 24 | 13191740000 ps | ||
| T50 | /workspace/coverage/default/38.prim_present_test.3194488058 | Jun 02 02:08:39 PM PDT 24 | Jun 02 02:10:21 PM PDT 24 | 13803060000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.943241734 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12829040000 ps |
| CPU time | 48 seconds |
| Started | Jun 02 02:08:25 PM PDT 24 |
| Finished | Jun 02 02:09:56 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-0749c7b4-e8ba-4ee6-9de3-2454b2d07715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943241734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.943241734 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.461825050 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13191740000 ps |
| CPU time | 53.67 seconds |
| Started | Jun 02 02:08:23 PM PDT 24 |
| Finished | Jun 02 02:10:07 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-0695e494-0667-4b7a-8874-32382ab81bc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461825050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.461825050 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2620981840 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11460700000 ps |
| CPU time | 46.29 seconds |
| Started | Jun 02 02:08:24 PM PDT 24 |
| Finished | Jun 02 02:09:58 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-aab9cf14-0aa4-45a4-883c-5c7bd35e3090 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620981840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2620981840 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3297350379 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4573120000 ps |
| CPU time | 17.52 seconds |
| Started | Jun 02 02:08:30 PM PDT 24 |
| Finished | Jun 02 02:09:04 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-da1efba1-d74f-49a1-8762-eaaa93d81bdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297350379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3297350379 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3837409365 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5088340000 ps |
| CPU time | 19.82 seconds |
| Started | Jun 02 02:08:27 PM PDT 24 |
| Finished | Jun 02 02:09:06 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-7c2f895b-f4e5-45b4-8523-68e889624699 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837409365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3837409365 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3946080695 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4672940000 ps |
| CPU time | 19.06 seconds |
| Started | Jun 02 02:08:29 PM PDT 24 |
| Finished | Jun 02 02:09:07 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-a7d522f0-414c-4284-9276-f574d4ccae5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946080695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3946080695 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4245858848 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8027760000 ps |
| CPU time | 32.46 seconds |
| Started | Jun 02 02:08:28 PM PDT 24 |
| Finished | Jun 02 02:09:32 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-a06b6d42-8b3f-496e-b520-36b2ccfcf5d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245858848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4245858848 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1008655856 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14847140000 ps |
| CPU time | 48.61 seconds |
| Started | Jun 02 02:08:29 PM PDT 24 |
| Finished | Jun 02 02:09:58 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-45b0a4f0-db79-46d7-af10-1445cccea0ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008655856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1008655856 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2803744077 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9977040000 ps |
| CPU time | 34.82 seconds |
| Started | Jun 02 02:08:28 PM PDT 24 |
| Finished | Jun 02 02:09:34 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-023aa099-fd9e-4f84-9621-1254e2c7a541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803744077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2803744077 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3928485386 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9489100000 ps |
| CPU time | 34.59 seconds |
| Started | Jun 02 02:08:28 PM PDT 24 |
| Finished | Jun 02 02:09:35 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-07fb8a6c-a8c1-4818-8c4c-5b29bd3031d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928485386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3928485386 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1348269285 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4999680000 ps |
| CPU time | 20.89 seconds |
| Started | Jun 02 02:08:29 PM PDT 24 |
| Finished | Jun 02 02:09:11 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-4ce468ea-2aaf-45d2-8232-75ab24de2159 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348269285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1348269285 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2801695692 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12969160000 ps |
| CPU time | 50.45 seconds |
| Started | Jun 02 02:08:29 PM PDT 24 |
| Finished | Jun 02 02:10:09 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-d9bd9285-0ab2-4717-abcb-e5ff48a09644 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801695692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2801695692 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1071672345 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8363800000 ps |
| CPU time | 34.24 seconds |
| Started | Jun 02 02:08:23 PM PDT 24 |
| Finished | Jun 02 02:09:31 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-bda8d912-5b98-4c57-bb05-bd88f4e3da4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071672345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1071672345 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3491079677 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6370500000 ps |
| CPU time | 26.74 seconds |
| Started | Jun 02 02:08:29 PM PDT 24 |
| Finished | Jun 02 02:09:23 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-d6e9d007-532c-4de9-81fd-7d5ec0544985 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491079677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3491079677 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.598715438 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12352880000 ps |
| CPU time | 50.23 seconds |
| Started | Jun 02 02:08:28 PM PDT 24 |
| Finished | Jun 02 02:10:05 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-8676c76d-2b4d-40c3-91b4-fe21354658e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598715438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.598715438 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2646984855 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12161920000 ps |
| CPU time | 47.61 seconds |
| Started | Jun 02 02:08:33 PM PDT 24 |
| Finished | Jun 02 02:10:06 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-399738af-a1bd-4ffd-8653-44c80b1f3acf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2646984855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2646984855 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3028854578 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7143020000 ps |
| CPU time | 21.41 seconds |
| Started | Jun 02 02:08:33 PM PDT 24 |
| Finished | Jun 02 02:09:13 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-431f73b1-b2fc-4160-a607-ff6aa0c574ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028854578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3028854578 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2321206795 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 14770880000 ps |
| CPU time | 57.19 seconds |
| Started | Jun 02 02:08:33 PM PDT 24 |
| Finished | Jun 02 02:10:27 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-5d704da5-4e06-4f13-905b-e7f281b88e00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321206795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2321206795 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3427685947 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6913000000 ps |
| CPU time | 23.77 seconds |
| Started | Jun 02 02:08:34 PM PDT 24 |
| Finished | Jun 02 02:09:19 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-4cf9dd77-3bf7-40a0-b986-9e12cece953a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427685947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3427685947 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3558877348 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14346800000 ps |
| CPU time | 55.62 seconds |
| Started | Jun 02 02:08:34 PM PDT 24 |
| Finished | Jun 02 02:10:21 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-db38dcbe-c5a0-4dca-af6a-38da2f9975f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3558877348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3558877348 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.146922111 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10212640000 ps |
| CPU time | 39.21 seconds |
| Started | Jun 02 02:08:34 PM PDT 24 |
| Finished | Jun 02 02:09:54 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-4c380c3b-4eed-4973-a4f6-e1076054c84f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146922111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.146922111 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2666996784 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13004500000 ps |
| CPU time | 48.43 seconds |
| Started | Jun 02 02:08:34 PM PDT 24 |
| Finished | Jun 02 02:10:08 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-eeb33724-6d80-42cc-8c64-9bd8486723da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666996784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2666996784 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2819968230 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7710940000 ps |
| CPU time | 29.42 seconds |
| Started | Jun 02 02:08:33 PM PDT 24 |
| Finished | Jun 02 02:09:30 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-5d54823e-e6d0-4d67-80b1-0a7e1183a361 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819968230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2819968230 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2002777713 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12091860000 ps |
| CPU time | 45.15 seconds |
| Started | Jun 02 02:08:22 PM PDT 24 |
| Finished | Jun 02 02:09:49 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-ef544aba-d098-4927-9659-39ca752fe309 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002777713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2002777713 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.534822293 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7911200000 ps |
| CPU time | 30.44 seconds |
| Started | Jun 02 02:08:34 PM PDT 24 |
| Finished | Jun 02 02:09:34 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-64204e85-840f-40c1-be98-d08328611737 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534822293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.534822293 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3600649310 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10203340000 ps |
| CPU time | 37.66 seconds |
| Started | Jun 02 02:08:38 PM PDT 24 |
| Finished | Jun 02 02:09:52 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-d200806b-493c-4738-af71-32a03d78037c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600649310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3600649310 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4113616032 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11719240000 ps |
| CPU time | 48.43 seconds |
| Started | Jun 02 02:08:38 PM PDT 24 |
| Finished | Jun 02 02:10:14 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-a74cfc9c-b6a2-4b87-bfea-5650a2548450 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113616032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4113616032 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.526921618 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5175140000 ps |
| CPU time | 18.64 seconds |
| Started | Jun 02 02:08:39 PM PDT 24 |
| Finished | Jun 02 02:09:15 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-7a615968-3bec-4081-b712-0415e9ca4e71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526921618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.526921618 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.122643306 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11316240000 ps |
| CPU time | 40.39 seconds |
| Started | Jun 02 02:08:39 PM PDT 24 |
| Finished | Jun 02 02:09:57 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-538091ff-cf35-40d9-8a75-71d588b3fd60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=122643306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.122643306 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.895483257 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13025580000 ps |
| CPU time | 53.1 seconds |
| Started | Jun 02 02:08:39 PM PDT 24 |
| Finished | Jun 02 02:10:24 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-9c5550bc-5614-427c-801c-54a64c9e7830 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895483257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.895483257 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1189549387 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10634860000 ps |
| CPU time | 41.54 seconds |
| Started | Jun 02 02:08:39 PM PDT 24 |
| Finished | Jun 02 02:09:59 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-0cc3917d-f85b-49cc-b456-5d42c1f59b9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189549387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1189549387 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3803171420 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4393940000 ps |
| CPU time | 16.72 seconds |
| Started | Jun 02 02:08:38 PM PDT 24 |
| Finished | Jun 02 02:09:12 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-0d2329be-d428-4954-858d-0b5d8dcc61c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803171420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3803171420 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3194488058 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13803060000 ps |
| CPU time | 53.04 seconds |
| Started | Jun 02 02:08:39 PM PDT 24 |
| Finished | Jun 02 02:10:21 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-13d9cfa3-570f-48af-ab06-5248ee4cdc31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194488058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3194488058 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.4249709226 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13352320000 ps |
| CPU time | 50.32 seconds |
| Started | Jun 02 02:08:39 PM PDT 24 |
| Finished | Jun 02 02:10:17 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-01ab0267-0946-4865-b170-325b990daf58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249709226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4249709226 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1765616637 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13363480000 ps |
| CPU time | 54.13 seconds |
| Started | Jun 02 02:08:27 PM PDT 24 |
| Finished | Jun 02 02:10:12 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-b9e5c505-1114-4250-b094-927bc65b3235 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765616637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1765616637 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.917132511 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5839780000 ps |
| CPU time | 24.99 seconds |
| Started | Jun 02 02:08:39 PM PDT 24 |
| Finished | Jun 02 02:09:28 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-9188bec0-e5b3-42c1-ad0c-894163bc1495 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917132511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.917132511 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3201699745 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3567480000 ps |
| CPU time | 14.19 seconds |
| Started | Jun 02 02:08:48 PM PDT 24 |
| Finished | Jun 02 02:09:16 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-04c50d6a-c273-4d39-b8bb-45a6812ba8db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3201699745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3201699745 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2542192168 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 10124600000 ps |
| CPU time | 40.94 seconds |
| Started | Jun 02 02:08:44 PM PDT 24 |
| Finished | Jun 02 02:10:07 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e4d0b293-9463-4a98-9415-d8786d0f2a9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542192168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2542192168 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.190144405 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6426920000 ps |
| CPU time | 25.1 seconds |
| Started | Jun 02 02:08:45 PM PDT 24 |
| Finished | Jun 02 02:09:34 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-634bcec1-c1c3-49df-b66b-bf523b6d001f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190144405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.190144405 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1519611954 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11217660000 ps |
| CPU time | 42.39 seconds |
| Started | Jun 02 02:08:44 PM PDT 24 |
| Finished | Jun 02 02:10:06 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-d90d6042-45f9-4db1-8d45-66c9a0af7e3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519611954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1519611954 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4260088434 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11499760000 ps |
| CPU time | 45.9 seconds |
| Started | Jun 02 02:08:46 PM PDT 24 |
| Finished | Jun 02 02:10:14 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-984646f5-6449-435a-a455-938fbe2117eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4260088434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4260088434 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1838562211 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8471060000 ps |
| CPU time | 31.11 seconds |
| Started | Jun 02 02:08:49 PM PDT 24 |
| Finished | Jun 02 02:09:48 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-10b4d0de-b313-46eb-af23-3b9740cbab1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838562211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1838562211 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.365546583 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7214940000 ps |
| CPU time | 30.22 seconds |
| Started | Jun 02 02:08:45 PM PDT 24 |
| Finished | Jun 02 02:09:44 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-73454d00-7b89-4f36-a967-60fae7f5c2bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365546583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.365546583 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2076088903 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14796920000 ps |
| CPU time | 50.57 seconds |
| Started | Jun 02 02:08:48 PM PDT 24 |
| Finished | Jun 02 02:10:24 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-48982e24-5865-4d70-95f6-cd3b2c19f4c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076088903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2076088903 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1989992042 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14142820000 ps |
| CPU time | 48.82 seconds |
| Started | Jun 02 02:08:45 PM PDT 24 |
| Finished | Jun 02 02:10:20 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-d32c923f-2777-4568-9a7a-662b0ed74990 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989992042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1989992042 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3126017628 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10444520000 ps |
| CPU time | 41.75 seconds |
| Started | Jun 02 02:08:26 PM PDT 24 |
| Finished | Jun 02 02:09:46 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-8c42d322-b614-428f-8b14-1eaf4e4e09a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126017628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3126017628 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3577942469 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13223360000 ps |
| CPU time | 52.06 seconds |
| Started | Jun 02 02:08:23 PM PDT 24 |
| Finished | Jun 02 02:10:06 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-0f78a92f-12aa-428b-aaaf-ec7096399c9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577942469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3577942469 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1296500639 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6169000000 ps |
| CPU time | 21.48 seconds |
| Started | Jun 02 02:08:23 PM PDT 24 |
| Finished | Jun 02 02:09:03 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-fa0b5059-b95c-43ff-9af6-45cf90d55b55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296500639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1296500639 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1253822866 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6576340000 ps |
| CPU time | 25.42 seconds |
| Started | Jun 02 02:08:24 PM PDT 24 |
| Finished | Jun 02 02:09:15 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-84c3c3ab-400f-4737-81b0-95c62ffc6f26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253822866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1253822866 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3291495952 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11071340000 ps |
| CPU time | 47.94 seconds |
| Started | Jun 02 02:08:23 PM PDT 24 |
| Finished | Jun 02 02:09:58 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-f536290d-b47c-4881-a30c-a8d920b14604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291495952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3291495952 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |