| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.860501013 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.4110144008 |
| /workspace/coverage/default/1.prim_present_test.3013159498 |
| /workspace/coverage/default/11.prim_present_test.1203690215 |
| /workspace/coverage/default/12.prim_present_test.4198277588 |
| /workspace/coverage/default/13.prim_present_test.2224590467 |
| /workspace/coverage/default/14.prim_present_test.3868256487 |
| /workspace/coverage/default/15.prim_present_test.1574645106 |
| /workspace/coverage/default/16.prim_present_test.1071866353 |
| /workspace/coverage/default/17.prim_present_test.2690411594 |
| /workspace/coverage/default/18.prim_present_test.2167619761 |
| /workspace/coverage/default/19.prim_present_test.2933224505 |
| /workspace/coverage/default/2.prim_present_test.1714377199 |
| /workspace/coverage/default/20.prim_present_test.1338592033 |
| /workspace/coverage/default/21.prim_present_test.1544556799 |
| /workspace/coverage/default/22.prim_present_test.1464122878 |
| /workspace/coverage/default/23.prim_present_test.484377314 |
| /workspace/coverage/default/24.prim_present_test.2591791206 |
| /workspace/coverage/default/25.prim_present_test.3323087282 |
| /workspace/coverage/default/26.prim_present_test.627189842 |
| /workspace/coverage/default/27.prim_present_test.818750391 |
| /workspace/coverage/default/28.prim_present_test.2620605340 |
| /workspace/coverage/default/29.prim_present_test.1056926232 |
| /workspace/coverage/default/3.prim_present_test.1340328603 |
| /workspace/coverage/default/30.prim_present_test.674675246 |
| /workspace/coverage/default/31.prim_present_test.2694939914 |
| /workspace/coverage/default/32.prim_present_test.433239355 |
| /workspace/coverage/default/33.prim_present_test.989298444 |
| /workspace/coverage/default/34.prim_present_test.3513395488 |
| /workspace/coverage/default/35.prim_present_test.2445196989 |
| /workspace/coverage/default/36.prim_present_test.4103560232 |
| /workspace/coverage/default/37.prim_present_test.4096279530 |
| /workspace/coverage/default/38.prim_present_test.2803141445 |
| /workspace/coverage/default/39.prim_present_test.4195387314 |
| /workspace/coverage/default/4.prim_present_test.2213534174 |
| /workspace/coverage/default/40.prim_present_test.315512811 |
| /workspace/coverage/default/41.prim_present_test.3436147717 |
| /workspace/coverage/default/42.prim_present_test.2368199752 |
| /workspace/coverage/default/43.prim_present_test.189973917 |
| /workspace/coverage/default/44.prim_present_test.1157513093 |
| /workspace/coverage/default/45.prim_present_test.1433532881 |
| /workspace/coverage/default/46.prim_present_test.922119597 |
| /workspace/coverage/default/47.prim_present_test.698172404 |
| /workspace/coverage/default/48.prim_present_test.3198778159 |
| /workspace/coverage/default/49.prim_present_test.1325670658 |
| /workspace/coverage/default/5.prim_present_test.2428632900 |
| /workspace/coverage/default/6.prim_present_test.782007154 |
| /workspace/coverage/default/7.prim_present_test.2321358075 |
| /workspace/coverage/default/8.prim_present_test.1223578661 |
| /workspace/coverage/default/9.prim_present_test.3043869337 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/44.prim_present_test.1157513093 | Jun 04 12:57:00 PM PDT 24 | Jun 04 12:57:53 PM PDT 24 | 7310420000 ps | ||
| T2 | /workspace/coverage/default/4.prim_present_test.2213534174 | Jun 04 12:56:56 PM PDT 24 | Jun 04 12:57:28 PM PDT 24 | 5225360000 ps | ||
| T3 | /workspace/coverage/default/32.prim_present_test.433239355 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:57:58 PM PDT 24 | 8478500000 ps | ||
| T4 | /workspace/coverage/default/6.prim_present_test.782007154 | Jun 04 12:57:33 PM PDT 24 | Jun 04 12:58:19 PM PDT 24 | 6795200000 ps | ||
| T5 | /workspace/coverage/default/34.prim_present_test.3513395488 | Jun 04 12:57:07 PM PDT 24 | Jun 04 12:58:41 PM PDT 24 | 14054160000 ps | ||
| T6 | /workspace/coverage/default/3.prim_present_test.1340328603 | Jun 04 12:56:52 PM PDT 24 | Jun 04 12:58:37 PM PDT 24 | 15015780000 ps | ||
| T7 | /workspace/coverage/default/10.prim_present_test.860501013 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:58:34 PM PDT 24 | 14212880000 ps | ||
| T8 | /workspace/coverage/default/13.prim_present_test.2224590467 | Jun 04 12:57:00 PM PDT 24 | Jun 04 12:58:15 PM PDT 24 | 11337320000 ps | ||
| T9 | /workspace/coverage/default/23.prim_present_test.484377314 | Jun 04 12:56:57 PM PDT 24 | Jun 04 12:58:31 PM PDT 24 | 13478800000 ps | ||
| T10 | /workspace/coverage/default/33.prim_present_test.989298444 | Jun 04 12:56:51 PM PDT 24 | Jun 04 12:57:50 PM PDT 24 | 9289460000 ps | ||
| T11 | /workspace/coverage/default/49.prim_present_test.1325670658 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:57:49 PM PDT 24 | 7191380000 ps | ||
| T12 | /workspace/coverage/default/8.prim_present_test.1223578661 | Jun 04 12:56:56 PM PDT 24 | Jun 04 12:57:40 PM PDT 24 | 6702200000 ps | ||
| T13 | /workspace/coverage/default/29.prim_present_test.1056926232 | Jun 04 12:56:52 PM PDT 24 | Jun 04 12:58:37 PM PDT 24 | 15414440000 ps | ||
| T14 | /workspace/coverage/default/11.prim_present_test.1203690215 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:57:42 PM PDT 24 | 6741260000 ps | ||
| T15 | /workspace/coverage/default/7.prim_present_test.2321358075 | Jun 04 12:56:54 PM PDT 24 | Jun 04 12:57:48 PM PDT 24 | 7946540000 ps | ||
| T16 | /workspace/coverage/default/39.prim_present_test.4195387314 | Jun 04 12:57:03 PM PDT 24 | Jun 04 12:57:31 PM PDT 24 | 3477580000 ps | ||
| T17 | /workspace/coverage/default/16.prim_present_test.1071866353 | Jun 04 12:56:50 PM PDT 24 | Jun 04 12:57:31 PM PDT 24 | 5885660000 ps | ||
| T18 | /workspace/coverage/default/28.prim_present_test.2620605340 | Jun 04 12:56:56 PM PDT 24 | Jun 04 12:58:27 PM PDT 24 | 12503540000 ps | ||
| T19 | /workspace/coverage/default/31.prim_present_test.2694939914 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:58:34 PM PDT 24 | 12902200000 ps | ||
| T20 | /workspace/coverage/default/17.prim_present_test.2690411594 | Jun 04 12:57:01 PM PDT 24 | Jun 04 12:58:00 PM PDT 24 | 7683660000 ps | ||
| T21 | /workspace/coverage/default/19.prim_present_test.2933224505 | Jun 04 12:56:56 PM PDT 24 | Jun 04 12:57:24 PM PDT 24 | 3681560000 ps | ||
| T22 | /workspace/coverage/default/2.prim_present_test.1714377199 | Jun 04 12:56:56 PM PDT 24 | Jun 04 12:58:04 PM PDT 24 | 10079960000 ps | ||
| T23 | /workspace/coverage/default/27.prim_present_test.818750391 | Jun 04 12:57:02 PM PDT 24 | Jun 04 12:58:17 PM PDT 24 | 14623320000 ps | ||
| T24 | /workspace/coverage/default/47.prim_present_test.698172404 | Jun 04 12:56:57 PM PDT 24 | Jun 04 12:58:12 PM PDT 24 | 10024160000 ps | ||
| T25 | /workspace/coverage/default/12.prim_present_test.4198277588 | Jun 04 12:56:54 PM PDT 24 | Jun 04 12:58:12 PM PDT 24 | 12362800000 ps | ||
| T26 | /workspace/coverage/default/41.prim_present_test.3436147717 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:58:00 PM PDT 24 | 9604420000 ps | ||
| T27 | /workspace/coverage/default/24.prim_present_test.2591791206 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:57:59 PM PDT 24 | 7270740000 ps | ||
| T28 | /workspace/coverage/default/42.prim_present_test.2368199752 | Jun 04 12:56:50 PM PDT 24 | Jun 04 12:58:07 PM PDT 24 | 11309420000 ps | ||
| T29 | /workspace/coverage/default/18.prim_present_test.2167619761 | Jun 04 12:56:54 PM PDT 24 | Jun 04 12:58:06 PM PDT 24 | 12005060000 ps | ||
| T30 | /workspace/coverage/default/14.prim_present_test.3868256487 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:58:42 PM PDT 24 | 14918440000 ps | ||
| T31 | /workspace/coverage/default/22.prim_present_test.1464122878 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:57:40 PM PDT 24 | 5502500000 ps | ||
| T32 | /workspace/coverage/default/40.prim_present_test.315512811 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:58:00 PM PDT 24 | 9020380000 ps | ||
| T33 | /workspace/coverage/default/37.prim_present_test.4096279530 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:57:38 PM PDT 24 | 7053120000 ps | ||
| T34 | /workspace/coverage/default/20.prim_present_test.1338592033 | Jun 04 12:57:05 PM PDT 24 | Jun 04 12:58:22 PM PDT 24 | 11964140000 ps | ||
| T35 | /workspace/coverage/default/36.prim_present_test.4103560232 | Jun 04 12:56:57 PM PDT 24 | Jun 04 12:58:07 PM PDT 24 | 11969100000 ps | ||
| T36 | /workspace/coverage/default/15.prim_present_test.1574645106 | Jun 04 12:56:55 PM PDT 24 | Jun 04 12:58:07 PM PDT 24 | 12417980000 ps | ||
| T37 | /workspace/coverage/default/21.prim_present_test.1544556799 | Jun 04 12:57:07 PM PDT 24 | Jun 04 12:58:43 PM PDT 24 | 15368560000 ps | ||
| T38 | /workspace/coverage/default/30.prim_present_test.674675246 | Jun 04 12:56:57 PM PDT 24 | Jun 04 12:58:23 PM PDT 24 | 11594000000 ps | ||
| T39 | /workspace/coverage/default/43.prim_present_test.189973917 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:57:44 PM PDT 24 | 6664380000 ps | ||
| T40 | /workspace/coverage/default/1.prim_present_test.3013159498 | Jun 04 12:56:52 PM PDT 24 | Jun 04 12:57:54 PM PDT 24 | 8644660000 ps | ||
| T41 | /workspace/coverage/default/45.prim_present_test.1433532881 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:58:12 PM PDT 24 | 11448300000 ps | ||
| T42 | /workspace/coverage/default/9.prim_present_test.3043869337 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:58:11 PM PDT 24 | 10634240000 ps | ||
| T43 | /workspace/coverage/default/35.prim_present_test.2445196989 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:58:14 PM PDT 24 | 11053360000 ps | ||
| T44 | /workspace/coverage/default/46.prim_present_test.922119597 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:58:28 PM PDT 24 | 12294600000 ps | ||
| T45 | /workspace/coverage/default/26.prim_present_test.627189842 | Jun 04 12:56:58 PM PDT 24 | Jun 04 12:57:23 PM PDT 24 | 3298400000 ps | ||
| T46 | /workspace/coverage/default/0.prim_present_test.4110144008 | Jun 04 12:56:45 PM PDT 24 | Jun 04 12:58:33 PM PDT 24 | 15465900000 ps | ||
| T47 | /workspace/coverage/default/38.prim_present_test.2803141445 | Jun 04 12:57:32 PM PDT 24 | Jun 04 12:58:26 PM PDT 24 | 10667720000 ps | ||
| T48 | /workspace/coverage/default/25.prim_present_test.3323087282 | Jun 04 12:56:59 PM PDT 24 | Jun 04 12:58:02 PM PDT 24 | 10569760000 ps | ||
| T49 | /workspace/coverage/default/5.prim_present_test.2428632900 | Jun 04 12:56:57 PM PDT 24 | Jun 04 12:57:29 PM PDT 24 | 4242660000 ps | ||
| T50 | /workspace/coverage/default/48.prim_present_test.3198778159 | Jun 04 12:56:56 PM PDT 24 | Jun 04 12:58:38 PM PDT 24 | 14331920000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.860501013 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14212880000 ps |
| CPU time | 50.3 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:58:34 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-76ac6341-4284-4f0e-bc2c-f3b999fa6493 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860501013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.860501013 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.4110144008 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15465900000 ps |
| CPU time | 57.47 seconds |
| Started | Jun 04 12:56:45 PM PDT 24 |
| Finished | Jun 04 12:58:33 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-2b1ac119-9039-4925-9bb8-147846ef3e58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110144008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.4110144008 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3013159498 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8644660000 ps |
| CPU time | 32.9 seconds |
| Started | Jun 04 12:56:52 PM PDT 24 |
| Finished | Jun 04 12:57:54 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-80d851ed-05f6-4e37-911f-93fb0e37a370 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013159498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3013159498 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1203690215 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6741260000 ps |
| CPU time | 22.76 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:57:42 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-98efeb01-2ef8-44f1-b23e-4798bb57fbdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1203690215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1203690215 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4198277588 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12362800000 ps |
| CPU time | 41.65 seconds |
| Started | Jun 04 12:56:54 PM PDT 24 |
| Finished | Jun 04 12:58:12 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-93304d93-a081-4183-8374-ce3c6e19465d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198277588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4198277588 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2224590467 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11337320000 ps |
| CPU time | 39.57 seconds |
| Started | Jun 04 12:57:00 PM PDT 24 |
| Finished | Jun 04 12:58:15 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-e83496ab-577a-4cd9-924f-e90e6970856a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224590467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2224590467 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3868256487 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14918440000 ps |
| CPU time | 54.88 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:58:42 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-86ba0e7d-e2cf-43e7-8dd4-33f980b5fa63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3868256487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3868256487 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1574645106 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12417980000 ps |
| CPU time | 38.2 seconds |
| Started | Jun 04 12:56:55 PM PDT 24 |
| Finished | Jun 04 12:58:07 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-eeff51cc-35fe-4f97-9e5b-de03c416d3c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574645106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1574645106 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1071866353 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5885660000 ps |
| CPU time | 21.69 seconds |
| Started | Jun 04 12:56:50 PM PDT 24 |
| Finished | Jun 04 12:57:31 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-f472c985-9689-469b-96d3-1536026ff5e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071866353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1071866353 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2690411594 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7683660000 ps |
| CPU time | 30.36 seconds |
| Started | Jun 04 12:57:01 PM PDT 24 |
| Finished | Jun 04 12:58:00 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-2651bd3c-158c-40ee-89d9-fea3dec5b0a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690411594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2690411594 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2167619761 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 12005060000 ps |
| CPU time | 38.74 seconds |
| Started | Jun 04 12:56:54 PM PDT 24 |
| Finished | Jun 04 12:58:06 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-f8c2cbbe-b9a9-4c08-a4b1-e4c0a1531968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167619761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2167619761 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2933224505 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3681560000 ps |
| CPU time | 14.67 seconds |
| Started | Jun 04 12:56:56 PM PDT 24 |
| Finished | Jun 04 12:57:24 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-e7df21ce-70e7-470d-8ddb-4c7effed9cb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933224505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2933224505 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1714377199 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10079960000 ps |
| CPU time | 36.36 seconds |
| Started | Jun 04 12:56:56 PM PDT 24 |
| Finished | Jun 04 12:58:04 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-25edc84b-f2d4-41f0-a1f5-9dbf327ea14a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714377199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1714377199 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1338592033 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11964140000 ps |
| CPU time | 41.33 seconds |
| Started | Jun 04 12:57:05 PM PDT 24 |
| Finished | Jun 04 12:58:22 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-99e305b6-add4-4d47-a320-868d365a3fda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338592033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1338592033 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1544556799 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 15368560000 ps |
| CPU time | 51.25 seconds |
| Started | Jun 04 12:57:07 PM PDT 24 |
| Finished | Jun 04 12:58:43 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-e2ea8207-c636-4999-b5ad-b3fb87362a59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544556799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1544556799 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1464122878 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5502500000 ps |
| CPU time | 20.86 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:57:40 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-ef4a2f09-f987-40f9-a1aa-6a345f50c270 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464122878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1464122878 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.484377314 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13478800000 ps |
| CPU time | 49.48 seconds |
| Started | Jun 04 12:56:57 PM PDT 24 |
| Finished | Jun 04 12:58:31 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-adc01d17-4a83-4ee1-9533-15b83be12ca2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484377314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.484377314 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2591791206 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7270740000 ps |
| CPU time | 30.58 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:57:59 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-0c83e560-407e-4c1e-8a5c-d421ca249292 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591791206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2591791206 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3323087282 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10569760000 ps |
| CPU time | 33.05 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:58:02 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-fbcb8444-2fe9-4b98-af4e-de5484f1cca6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323087282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3323087282 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.627189842 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3298400000 ps |
| CPU time | 12.71 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:57:23 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-59fc98c1-7064-4371-a706-f87ad8b21558 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627189842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.627189842 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.818750391 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14623320000 ps |
| CPU time | 40.39 seconds |
| Started | Jun 04 12:57:02 PM PDT 24 |
| Finished | Jun 04 12:58:17 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-98a08cd4-79e1-4193-9b43-fbfa404c23de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818750391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.818750391 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2620605340 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12503540000 ps |
| CPU time | 47.71 seconds |
| Started | Jun 04 12:56:56 PM PDT 24 |
| Finished | Jun 04 12:58:27 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-50d119f4-ede2-49ad-af65-20f83b2ebba4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620605340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2620605340 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1056926232 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15414440000 ps |
| CPU time | 56.01 seconds |
| Started | Jun 04 12:56:52 PM PDT 24 |
| Finished | Jun 04 12:58:37 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-ea68a483-bf1d-4363-8e7b-00db1b1bbee8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056926232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1056926232 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1340328603 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 15015780000 ps |
| CPU time | 56.32 seconds |
| Started | Jun 04 12:56:52 PM PDT 24 |
| Finished | Jun 04 12:58:37 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-d74c7302-f5fb-4458-833c-18939939f356 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340328603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1340328603 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.674675246 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11594000000 ps |
| CPU time | 44.41 seconds |
| Started | Jun 04 12:56:57 PM PDT 24 |
| Finished | Jun 04 12:58:23 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-be701114-62bc-4f88-b848-b56cc442f7b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674675246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.674675246 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2694939914 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12902200000 ps |
| CPU time | 48.83 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:58:34 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-135b4923-b770-4d60-9148-859b7494ee7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694939914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2694939914 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.433239355 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8478500000 ps |
| CPU time | 30.48 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:57:58 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-838feafa-4cff-4fd3-9026-80e8cf9db376 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433239355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.433239355 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.989298444 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9289460000 ps |
| CPU time | 31.58 seconds |
| Started | Jun 04 12:56:51 PM PDT 24 |
| Finished | Jun 04 12:57:50 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-fe691f99-235e-43f9-a486-a6f4043dd88a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989298444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.989298444 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3513395488 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14054160000 ps |
| CPU time | 48.77 seconds |
| Started | Jun 04 12:57:07 PM PDT 24 |
| Finished | Jun 04 12:58:41 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-8b5aa133-913b-42d6-a091-2e969228a19a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513395488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3513395488 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2445196989 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11053360000 ps |
| CPU time | 40.36 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:58:14 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-b5bc66ee-6663-4ba0-bed6-1d8be98bacb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445196989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2445196989 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4103560232 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11969100000 ps |
| CPU time | 36.9 seconds |
| Started | Jun 04 12:56:57 PM PDT 24 |
| Finished | Jun 04 12:58:07 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-14d0ca90-59bf-4bfd-91d7-346531e9549c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4103560232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4103560232 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.4096279530 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7053120000 ps |
| CPU time | 20.35 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:57:38 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-ecaac6ac-c7b5-44da-b5b1-7d18339fc0be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096279530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.4096279530 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2803141445 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10667720000 ps |
| CPU time | 28.82 seconds |
| Started | Jun 04 12:57:32 PM PDT 24 |
| Finished | Jun 04 12:58:26 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-237ac0e9-7e71-4ca0-a2ae-fab885fa2f4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803141445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2803141445 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.4195387314 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3477580000 ps |
| CPU time | 14.45 seconds |
| Started | Jun 04 12:57:03 PM PDT 24 |
| Finished | Jun 04 12:57:31 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-3b5eaf6a-aba1-4203-bba8-b5eecd85ed72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195387314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4195387314 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2213534174 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5225360000 ps |
| CPU time | 17.17 seconds |
| Started | Jun 04 12:56:56 PM PDT 24 |
| Finished | Jun 04 12:57:28 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-42310423-96cb-4786-9ec8-04bd596393ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213534174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2213534174 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.315512811 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9020380000 ps |
| CPU time | 31.65 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:58:00 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-328948d2-97de-4a20-b572-75e398eb7dcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315512811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.315512811 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3436147717 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9604420000 ps |
| CPU time | 31.92 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:58:00 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-98aff009-46dc-463e-9042-06c0f1a25fb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436147717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3436147717 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2368199752 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11309420000 ps |
| CPU time | 41.19 seconds |
| Started | Jun 04 12:56:50 PM PDT 24 |
| Finished | Jun 04 12:58:07 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-294b7582-423b-4ef1-8e14-38bc8eefd634 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368199752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2368199752 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.189973917 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6664380000 ps |
| CPU time | 23.15 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:57:44 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-b1dfbad5-f0c4-47d4-91bc-bb2ae87b9e09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189973917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.189973917 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1157513093 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7310420000 ps |
| CPU time | 27 seconds |
| Started | Jun 04 12:57:00 PM PDT 24 |
| Finished | Jun 04 12:57:53 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-704f879d-3f60-4143-97e6-055fcb1c5c2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157513093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1157513093 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1433532881 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11448300000 ps |
| CPU time | 37.74 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:58:12 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-03c33aeb-1415-4ff8-9f9f-e10d195c1ce6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433532881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1433532881 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.922119597 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12294600000 ps |
| CPU time | 46.72 seconds |
| Started | Jun 04 12:56:59 PM PDT 24 |
| Finished | Jun 04 12:58:28 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-80ef57b6-bab3-496e-ad65-ff14ebeeddba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922119597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.922119597 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.698172404 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10024160000 ps |
| CPU time | 38.39 seconds |
| Started | Jun 04 12:56:57 PM PDT 24 |
| Finished | Jun 04 12:58:12 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-6447d466-bb25-48a3-9672-e0d43c99e1d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698172404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.698172404 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3198778159 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14331920000 ps |
| CPU time | 53.3 seconds |
| Started | Jun 04 12:56:56 PM PDT 24 |
| Finished | Jun 04 12:58:38 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-aa2cb5c9-d50e-4a27-a5c5-e01129bc1e3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198778159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3198778159 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1325670658 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7191380000 ps |
| CPU time | 26.08 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:57:49 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e319b289-000c-41ec-9089-def83c2c8bd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325670658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1325670658 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2428632900 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4242660000 ps |
| CPU time | 15.82 seconds |
| Started | Jun 04 12:56:57 PM PDT 24 |
| Finished | Jun 04 12:57:29 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-2c414bf2-ca4f-4b46-866e-0ab4e8fe0646 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428632900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2428632900 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.782007154 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6795200000 ps |
| CPU time | 24.46 seconds |
| Started | Jun 04 12:57:33 PM PDT 24 |
| Finished | Jun 04 12:58:19 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-19c36d19-8905-49be-99f2-39631fe6146b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782007154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.782007154 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2321358075 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7946540000 ps |
| CPU time | 28.58 seconds |
| Started | Jun 04 12:56:54 PM PDT 24 |
| Finished | Jun 04 12:57:48 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-92335e99-f3c5-4907-bae2-e0626d536b24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321358075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2321358075 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1223578661 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6702200000 ps |
| CPU time | 23.58 seconds |
| Started | Jun 04 12:56:56 PM PDT 24 |
| Finished | Jun 04 12:57:40 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-7ddac4b7-c461-4b32-877e-6b532239eeb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223578661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1223578661 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3043869337 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10634240000 ps |
| CPU time | 38.04 seconds |
| Started | Jun 04 12:56:58 PM PDT 24 |
| Finished | Jun 04 12:58:11 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-e8773995-a877-428b-ad93-fd87733934ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3043869337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3043869337 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |