| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3298294661 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.1023210797 |
| /workspace/coverage/default/10.prim_present_test.1722972417 |
| /workspace/coverage/default/11.prim_present_test.729382947 |
| /workspace/coverage/default/12.prim_present_test.3452658778 |
| /workspace/coverage/default/13.prim_present_test.2208438791 |
| /workspace/coverage/default/14.prim_present_test.2451124734 |
| /workspace/coverage/default/15.prim_present_test.1377858521 |
| /workspace/coverage/default/16.prim_present_test.1393644113 |
| /workspace/coverage/default/17.prim_present_test.3881082707 |
| /workspace/coverage/default/18.prim_present_test.2854266469 |
| /workspace/coverage/default/19.prim_present_test.400174776 |
| /workspace/coverage/default/2.prim_present_test.1118213305 |
| /workspace/coverage/default/20.prim_present_test.749377213 |
| /workspace/coverage/default/21.prim_present_test.2636965006 |
| /workspace/coverage/default/22.prim_present_test.564242052 |
| /workspace/coverage/default/23.prim_present_test.2494810435 |
| /workspace/coverage/default/24.prim_present_test.1185526243 |
| /workspace/coverage/default/25.prim_present_test.982792487 |
| /workspace/coverage/default/26.prim_present_test.4226654881 |
| /workspace/coverage/default/27.prim_present_test.828717150 |
| /workspace/coverage/default/28.prim_present_test.3944749427 |
| /workspace/coverage/default/29.prim_present_test.1852564688 |
| /workspace/coverage/default/3.prim_present_test.573548012 |
| /workspace/coverage/default/30.prim_present_test.3239753277 |
| /workspace/coverage/default/31.prim_present_test.3063946979 |
| /workspace/coverage/default/32.prim_present_test.833007293 |
| /workspace/coverage/default/33.prim_present_test.2423532167 |
| /workspace/coverage/default/34.prim_present_test.2655725528 |
| /workspace/coverage/default/35.prim_present_test.3648414281 |
| /workspace/coverage/default/36.prim_present_test.1519181699 |
| /workspace/coverage/default/37.prim_present_test.324202425 |
| /workspace/coverage/default/38.prim_present_test.242929206 |
| /workspace/coverage/default/39.prim_present_test.236519405 |
| /workspace/coverage/default/4.prim_present_test.1165821449 |
| /workspace/coverage/default/40.prim_present_test.2516411480 |
| /workspace/coverage/default/41.prim_present_test.1186103388 |
| /workspace/coverage/default/42.prim_present_test.2856796427 |
| /workspace/coverage/default/43.prim_present_test.1184561227 |
| /workspace/coverage/default/44.prim_present_test.577079225 |
| /workspace/coverage/default/45.prim_present_test.2724842659 |
| /workspace/coverage/default/46.prim_present_test.383550661 |
| /workspace/coverage/default/47.prim_present_test.4265400765 |
| /workspace/coverage/default/48.prim_present_test.2603837457 |
| /workspace/coverage/default/49.prim_present_test.672316485 |
| /workspace/coverage/default/5.prim_present_test.3632171998 |
| /workspace/coverage/default/6.prim_present_test.4181255213 |
| /workspace/coverage/default/7.prim_present_test.2167273036 |
| /workspace/coverage/default/8.prim_present_test.31011432 |
| /workspace/coverage/default/9.prim_present_test.2037058667 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_present_test.3881082707 | Jun 05 05:00:57 PM PDT 24 | Jun 05 05:01:23 PM PDT 24 | 3538960000 ps | ||
| T2 | /workspace/coverage/default/20.prim_present_test.749377213 | Jun 05 05:00:58 PM PDT 24 | Jun 05 05:01:34 PM PDT 24 | 4341860000 ps | ||
| T3 | /workspace/coverage/default/35.prim_present_test.3648414281 | Jun 05 05:01:06 PM PDT 24 | Jun 05 05:02:02 PM PDT 24 | 7519980000 ps | ||
| T4 | /workspace/coverage/default/26.prim_present_test.4226654881 | Jun 05 05:01:07 PM PDT 24 | Jun 05 05:02:43 PM PDT 24 | 10414140000 ps | ||
| T5 | /workspace/coverage/default/36.prim_present_test.1519181699 | Jun 05 05:01:03 PM PDT 24 | Jun 05 05:01:51 PM PDT 24 | 5057960000 ps | ||
| T6 | /workspace/coverage/default/45.prim_present_test.2724842659 | Jun 05 05:01:05 PM PDT 24 | Jun 05 05:02:09 PM PDT 24 | 9273340000 ps | ||
| T7 | /workspace/coverage/default/5.prim_present_test.3632171998 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:01:30 PM PDT 24 | 4523520000 ps | ||
| T8 | /workspace/coverage/default/31.prim_present_test.3063946979 | Jun 05 05:01:07 PM PDT 24 | Jun 05 05:02:01 PM PDT 24 | 8588240000 ps | ||
| T9 | /workspace/coverage/default/10.prim_present_test.1722972417 | Jun 05 05:00:57 PM PDT 24 | Jun 05 05:01:32 PM PDT 24 | 3752860000 ps | ||
| T10 | /workspace/coverage/default/0.prim_present_test.3298294661 | Jun 05 05:00:46 PM PDT 24 | Jun 05 05:01:04 PM PDT 24 | 3222140000 ps | ||
| T11 | /workspace/coverage/default/14.prim_present_test.2451124734 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:02:10 PM PDT 24 | 7911820000 ps | ||
| T12 | /workspace/coverage/default/18.prim_present_test.2854266469 | Jun 05 05:00:59 PM PDT 24 | Jun 05 05:01:36 PM PDT 24 | 5308440000 ps | ||
| T13 | /workspace/coverage/default/1.prim_present_test.1023210797 | Jun 05 05:00:47 PM PDT 24 | Jun 05 05:02:54 PM PDT 24 | 14897980000 ps | ||
| T14 | /workspace/coverage/default/47.prim_present_test.4265400765 | Jun 05 05:01:05 PM PDT 24 | Jun 05 05:02:26 PM PDT 24 | 10559220000 ps | ||
| T15 | /workspace/coverage/default/32.prim_present_test.833007293 | Jun 05 05:01:05 PM PDT 24 | Jun 05 05:02:13 PM PDT 24 | 10920680000 ps | ||
| T16 | /workspace/coverage/default/41.prim_present_test.1186103388 | Jun 05 05:01:04 PM PDT 24 | Jun 05 05:02:17 PM PDT 24 | 8309240000 ps | ||
| T17 | /workspace/coverage/default/38.prim_present_test.242929206 | Jun 05 05:01:04 PM PDT 24 | Jun 05 05:02:15 PM PDT 24 | 11845100000 ps | ||
| T18 | /workspace/coverage/default/49.prim_present_test.672316485 | Jun 05 05:01:16 PM PDT 24 | Jun 05 05:01:42 PM PDT 24 | 3955600000 ps | ||
| T19 | /workspace/coverage/default/34.prim_present_test.2655725528 | Jun 05 05:01:05 PM PDT 24 | Jun 05 05:02:20 PM PDT 24 | 8803380000 ps | ||
| T20 | /workspace/coverage/default/40.prim_present_test.2516411480 | Jun 05 05:01:06 PM PDT 24 | Jun 05 05:01:39 PM PDT 24 | 4625200000 ps | ||
| T21 | /workspace/coverage/default/24.prim_present_test.1185526243 | Jun 05 05:00:57 PM PDT 24 | Jun 05 05:02:47 PM PDT 24 | 13705720000 ps | ||
| T22 | /workspace/coverage/default/37.prim_present_test.324202425 | Jun 05 05:01:06 PM PDT 24 | Jun 05 05:01:42 PM PDT 24 | 4565060000 ps | ||
| T23 | /workspace/coverage/default/42.prim_present_test.2856796427 | Jun 05 05:01:04 PM PDT 24 | Jun 05 05:02:01 PM PDT 24 | 6480860000 ps | ||
| T24 | /workspace/coverage/default/11.prim_present_test.729382947 | Jun 05 05:00:59 PM PDT 24 | Jun 05 05:01:57 PM PDT 24 | 6670580000 ps | ||
| T25 | /workspace/coverage/default/8.prim_present_test.31011432 | Jun 05 05:00:59 PM PDT 24 | Jun 05 05:02:52 PM PDT 24 | 13677820000 ps | ||
| T26 | /workspace/coverage/default/9.prim_present_test.2037058667 | Jun 05 05:00:57 PM PDT 24 | Jun 05 05:02:24 PM PDT 24 | 10730340000 ps | ||
| T27 | /workspace/coverage/default/25.prim_present_test.982792487 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:01:40 PM PDT 24 | 7196340000 ps | ||
| T28 | /workspace/coverage/default/48.prim_present_test.2603837457 | Jun 05 05:01:03 PM PDT 24 | Jun 05 05:01:54 PM PDT 24 | 6476520000 ps | ||
| T29 | /workspace/coverage/default/22.prim_present_test.564242052 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:01:17 PM PDT 24 | 3317620000 ps | ||
| T30 | /workspace/coverage/default/33.prim_present_test.2423532167 | Jun 05 05:01:06 PM PDT 24 | Jun 05 05:02:14 PM PDT 24 | 8405960000 ps | ||
| T31 | /workspace/coverage/default/46.prim_present_test.383550661 | Jun 05 05:01:05 PM PDT 24 | Jun 05 05:02:20 PM PDT 24 | 9149340000 ps | ||
| T32 | /workspace/coverage/default/13.prim_present_test.2208438791 | Jun 05 05:00:58 PM PDT 24 | Jun 05 05:01:30 PM PDT 24 | 4451600000 ps | ||
| T33 | /workspace/coverage/default/29.prim_present_test.1852564688 | Jun 05 05:01:05 PM PDT 24 | Jun 05 05:02:33 PM PDT 24 | 13021240000 ps | ||
| T34 | /workspace/coverage/default/15.prim_present_test.1377858521 | Jun 05 05:00:58 PM PDT 24 | Jun 05 05:02:29 PM PDT 24 | 10881000000 ps | ||
| T35 | /workspace/coverage/default/6.prim_present_test.4181255213 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:02:38 PM PDT 24 | 12308240000 ps | ||
| T36 | /workspace/coverage/default/23.prim_present_test.2494810435 | Jun 05 05:01:00 PM PDT 24 | Jun 05 05:01:22 PM PDT 24 | 3424880000 ps | ||
| T37 | /workspace/coverage/default/27.prim_present_test.828717150 | Jun 05 05:01:05 PM PDT 24 | Jun 05 05:01:41 PM PDT 24 | 4719440000 ps | ||
| T38 | /workspace/coverage/default/2.prim_present_test.1118213305 | Jun 05 05:00:58 PM PDT 24 | Jun 05 05:02:08 PM PDT 24 | 7390400000 ps | ||
| T39 | /workspace/coverage/default/12.prim_present_test.3452658778 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:02:53 PM PDT 24 | 14847140000 ps | ||
| T40 | /workspace/coverage/default/7.prim_present_test.2167273036 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:01:31 PM PDT 24 | 3571820000 ps | ||
| T41 | /workspace/coverage/default/39.prim_present_test.236519405 | Jun 05 05:01:04 PM PDT 24 | Jun 05 05:02:12 PM PDT 24 | 10180400000 ps | ||
| T42 | /workspace/coverage/default/16.prim_present_test.1393644113 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:02:05 PM PDT 24 | 10053920000 ps | ||
| T43 | /workspace/coverage/default/30.prim_present_test.3239753277 | Jun 05 05:01:04 PM PDT 24 | Jun 05 05:02:34 PM PDT 24 | 13010700000 ps | ||
| T44 | /workspace/coverage/default/43.prim_present_test.1184561227 | Jun 05 05:01:05 PM PDT 24 | Jun 05 05:01:46 PM PDT 24 | 4614660000 ps | ||
| T45 | /workspace/coverage/default/3.prim_present_test.573548012 | Jun 05 05:00:56 PM PDT 24 | Jun 05 05:02:11 PM PDT 24 | 7943440000 ps | ||
| T46 | /workspace/coverage/default/19.prim_present_test.400174776 | Jun 05 05:00:58 PM PDT 24 | Jun 05 05:02:01 PM PDT 24 | 7044440000 ps | ||
| T47 | /workspace/coverage/default/44.prim_present_test.577079225 | Jun 05 05:01:09 PM PDT 24 | Jun 05 05:01:50 PM PDT 24 | 5082760000 ps | ||
| T48 | /workspace/coverage/default/28.prim_present_test.3944749427 | Jun 05 05:01:03 PM PDT 24 | Jun 05 05:01:37 PM PDT 24 | 5278060000 ps | ||
| T49 | /workspace/coverage/default/4.prim_present_test.1165821449 | Jun 05 05:00:59 PM PDT 24 | Jun 05 05:02:16 PM PDT 24 | 11049640000 ps | ||
| T50 | /workspace/coverage/default/21.prim_present_test.2636965006 | Jun 05 05:00:58 PM PDT 24 | Jun 05 05:02:36 PM PDT 24 | 13659840000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3298294661 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3222140000 ps |
| CPU time | 9.54 seconds |
| Started | Jun 05 05:00:46 PM PDT 24 |
| Finished | Jun 05 05:01:04 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-88da30a6-b05d-4a8d-b77e-7ef25811add7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298294661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3298294661 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1023210797 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14897980000 ps |
| CPU time | 64.43 seconds |
| Started | Jun 05 05:00:47 PM PDT 24 |
| Finished | Jun 05 05:02:54 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-4bb3c4ce-56a5-499a-b2d9-f51e153ef02c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023210797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1023210797 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1722972417 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3752860000 ps |
| CPU time | 17.5 seconds |
| Started | Jun 05 05:00:57 PM PDT 24 |
| Finished | Jun 05 05:01:32 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-fc2e162f-e9cc-4f87-a804-ee7d83eba8e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722972417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1722972417 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.729382947 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6670580000 ps |
| CPU time | 28.22 seconds |
| Started | Jun 05 05:00:59 PM PDT 24 |
| Finished | Jun 05 05:01:57 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-dedd03f4-f943-4a31-99cb-a9682f17dac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729382947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.729382947 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3452658778 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14847140000 ps |
| CPU time | 61.38 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:02:53 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-621ae55e-0466-49ae-a567-b6212d728a6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452658778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3452658778 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2208438791 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4451600000 ps |
| CPU time | 16.45 seconds |
| Started | Jun 05 05:00:58 PM PDT 24 |
| Finished | Jun 05 05:01:30 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-9d99ec40-5505-4fba-8d35-289d9d49dca7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2208438791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2208438791 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2451124734 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7911820000 ps |
| CPU time | 36.18 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:02:10 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-394df0cb-e4a7-400c-8e42-c30113128538 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451124734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2451124734 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1377858521 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10881000000 ps |
| CPU time | 46.33 seconds |
| Started | Jun 05 05:00:58 PM PDT 24 |
| Finished | Jun 05 05:02:29 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-4df644cb-2720-4e76-af7e-308fed3cf0c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377858521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1377858521 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1393644113 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10053920000 ps |
| CPU time | 34.92 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:02:05 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-874af1ef-e0d1-44da-a627-6990996880f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393644113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1393644113 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3881082707 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3538960000 ps |
| CPU time | 13.24 seconds |
| Started | Jun 05 05:00:57 PM PDT 24 |
| Finished | Jun 05 05:01:23 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-9087d9cc-4718-488f-8803-55d509772f64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881082707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3881082707 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2854266469 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5308440000 ps |
| CPU time | 19.38 seconds |
| Started | Jun 05 05:00:59 PM PDT 24 |
| Finished | Jun 05 05:01:36 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-1ac9a342-0f02-45ed-bf66-96c74107d05d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854266469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2854266469 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.400174776 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7044440000 ps |
| CPU time | 30.64 seconds |
| Started | Jun 05 05:00:58 PM PDT 24 |
| Finished | Jun 05 05:02:01 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a269eca0-c270-4331-8d15-c5866d644cde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400174776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.400174776 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1118213305 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7390400000 ps |
| CPU time | 34.44 seconds |
| Started | Jun 05 05:00:58 PM PDT 24 |
| Finished | Jun 05 05:02:08 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-796ea531-cd42-40b1-bdec-4d77d7dcc4b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118213305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1118213305 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.749377213 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4341860000 ps |
| CPU time | 18.63 seconds |
| Started | Jun 05 05:00:58 PM PDT 24 |
| Finished | Jun 05 05:01:34 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-ad0ee2bc-d35b-462e-a990-1aff65143d6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749377213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.749377213 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2636965006 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13659840000 ps |
| CPU time | 52.12 seconds |
| Started | Jun 05 05:00:58 PM PDT 24 |
| Finished | Jun 05 05:02:36 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-d71552c7-a687-4e4a-923b-388fa191bca1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636965006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2636965006 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.564242052 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3317620000 ps |
| CPU time | 10.92 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:01:17 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-e12fa9e3-c235-4bc2-878a-a7702e572b60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=564242052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.564242052 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2494810435 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3424880000 ps |
| CPU time | 11.62 seconds |
| Started | Jun 05 05:01:00 PM PDT 24 |
| Finished | Jun 05 05:01:22 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-e364f3b5-3ee5-4528-ae27-5c6e835375a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494810435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2494810435 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1185526243 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13705720000 ps |
| CPU time | 56.7 seconds |
| Started | Jun 05 05:00:57 PM PDT 24 |
| Finished | Jun 05 05:02:47 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-3642fa08-6d08-4aeb-bd7d-0c3e88cf6047 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185526243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1185526243 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.982792487 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7196340000 ps |
| CPU time | 23.08 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:01:40 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-4e9140ee-e876-4eb4-ae6e-72c45d2ba4b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982792487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.982792487 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.4226654881 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10414140000 ps |
| CPU time | 49.22 seconds |
| Started | Jun 05 05:01:07 PM PDT 24 |
| Finished | Jun 05 05:02:43 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-2ead9122-e2c5-4f31-8e05-0e64ab1e2ad6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226654881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.4226654881 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.828717150 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4719440000 ps |
| CPU time | 18.23 seconds |
| Started | Jun 05 05:01:05 PM PDT 24 |
| Finished | Jun 05 05:01:41 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-0ed03e86-63a3-42d7-9f3c-6d08758ca7c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=828717150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.828717150 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3944749427 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5278060000 ps |
| CPU time | 17.71 seconds |
| Started | Jun 05 05:01:03 PM PDT 24 |
| Finished | Jun 05 05:01:37 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-53ba6071-9c63-4a14-b2c4-603e5f133c96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944749427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3944749427 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1852564688 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13021240000 ps |
| CPU time | 45.93 seconds |
| Started | Jun 05 05:01:05 PM PDT 24 |
| Finished | Jun 05 05:02:33 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-265e6630-4403-484b-8dbc-b021344a3528 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852564688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1852564688 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.573548012 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7943440000 ps |
| CPU time | 39.28 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:02:11 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-d6eac64b-e510-4cda-9ddc-40e2c38d54e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573548012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.573548012 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3239753277 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13010700000 ps |
| CPU time | 46.11 seconds |
| Started | Jun 05 05:01:04 PM PDT 24 |
| Finished | Jun 05 05:02:34 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-0bbc5ca4-0d46-44fe-80e0-1cb3f28ae0b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239753277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3239753277 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3063946979 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8588240000 ps |
| CPU time | 29.01 seconds |
| Started | Jun 05 05:01:07 PM PDT 24 |
| Finished | Jun 05 05:02:01 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-cfdc1619-af74-4385-8500-12c71ec6e92d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063946979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3063946979 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.833007293 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10920680000 ps |
| CPU time | 35.21 seconds |
| Started | Jun 05 05:01:05 PM PDT 24 |
| Finished | Jun 05 05:02:13 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-f9329193-6167-40a5-85e3-7e60993e79a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833007293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.833007293 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2423532167 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8405960000 ps |
| CPU time | 35 seconds |
| Started | Jun 05 05:01:06 PM PDT 24 |
| Finished | Jun 05 05:02:14 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-82e4f996-23c5-4e05-8d57-994f83ae402a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423532167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2423532167 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2655725528 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8803380000 ps |
| CPU time | 38.59 seconds |
| Started | Jun 05 05:01:05 PM PDT 24 |
| Finished | Jun 05 05:02:20 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-af269267-3811-469b-b00e-11cfb7aab986 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655725528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2655725528 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3648414281 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7519980000 ps |
| CPU time | 28.79 seconds |
| Started | Jun 05 05:01:06 PM PDT 24 |
| Finished | Jun 05 05:02:02 PM PDT 24 |
| Peak memory | 144840 kb |
| Host | smart-b2e7e87e-20e9-4e2e-96a7-8c55010da823 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648414281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3648414281 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1519181699 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5057960000 ps |
| CPU time | 23.92 seconds |
| Started | Jun 05 05:01:03 PM PDT 24 |
| Finished | Jun 05 05:01:51 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-e436e08c-4b4d-4a2b-a291-a98247c0f511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519181699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1519181699 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.324202425 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4565060000 ps |
| CPU time | 18.32 seconds |
| Started | Jun 05 05:01:06 PM PDT 24 |
| Finished | Jun 05 05:01:42 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-bb371bd9-494a-4d79-95da-322ac3a651ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=324202425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.324202425 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.242929206 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11845100000 ps |
| CPU time | 37.28 seconds |
| Started | Jun 05 05:01:04 PM PDT 24 |
| Finished | Jun 05 05:02:15 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-533064e8-d5a2-4592-9376-be63bf95d737 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242929206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.242929206 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.236519405 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10180400000 ps |
| CPU time | 35.75 seconds |
| Started | Jun 05 05:01:04 PM PDT 24 |
| Finished | Jun 05 05:02:12 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-1b65a29c-a6f3-455c-80dc-204bab619109 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236519405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.236519405 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1165821449 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11049640000 ps |
| CPU time | 40.71 seconds |
| Started | Jun 05 05:00:59 PM PDT 24 |
| Finished | Jun 05 05:02:16 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-6650453a-537a-4929-ac62-1b8d04d2e669 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165821449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1165821449 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2516411480 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4625200000 ps |
| CPU time | 16.97 seconds |
| Started | Jun 05 05:01:06 PM PDT 24 |
| Finished | Jun 05 05:01:39 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-5eeb1222-f189-460f-bdca-20e69fb7c977 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516411480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2516411480 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1186103388 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8309240000 ps |
| CPU time | 36.97 seconds |
| Started | Jun 05 05:01:04 PM PDT 24 |
| Finished | Jun 05 05:02:17 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-b6697823-7690-4cea-a9f1-d20d2f580d2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186103388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1186103388 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2856796427 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6480860000 ps |
| CPU time | 27.11 seconds |
| Started | Jun 05 05:01:04 PM PDT 24 |
| Finished | Jun 05 05:02:01 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-15b10c7d-a56a-460d-acc5-db31683d801a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856796427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2856796427 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1184561227 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4614660000 ps |
| CPU time | 19.86 seconds |
| Started | Jun 05 05:01:05 PM PDT 24 |
| Finished | Jun 05 05:01:46 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-9dcc2a60-ca74-4140-8663-c26ca43f724e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184561227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1184561227 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.577079225 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5082760000 ps |
| CPU time | 21.38 seconds |
| Started | Jun 05 05:01:09 PM PDT 24 |
| Finished | Jun 05 05:01:50 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-53b62a13-d6d2-41c9-b76c-d07ba03f336c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=577079225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.577079225 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2724842659 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9273340000 ps |
| CPU time | 33.52 seconds |
| Started | Jun 05 05:01:05 PM PDT 24 |
| Finished | Jun 05 05:02:09 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c0182c43-8a37-40cf-8e16-0882850fd2bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724842659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2724842659 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.383550661 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9149340000 ps |
| CPU time | 37.85 seconds |
| Started | Jun 05 05:01:05 PM PDT 24 |
| Finished | Jun 05 05:02:20 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-48b18e9f-31f5-44ce-a90e-0f6a2edab8c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383550661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.383550661 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4265400765 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10559220000 ps |
| CPU time | 41.96 seconds |
| Started | Jun 05 05:01:05 PM PDT 24 |
| Finished | Jun 05 05:02:26 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-c6f4d3d5-9db0-4183-9c54-0fe12f9741de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265400765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4265400765 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2603837457 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6476520000 ps |
| CPU time | 26.59 seconds |
| Started | Jun 05 05:01:03 PM PDT 24 |
| Finished | Jun 05 05:01:54 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-ea71da3c-10b6-4636-b966-e981b876dde3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603837457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2603837457 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.672316485 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3955600000 ps |
| CPU time | 13.51 seconds |
| Started | Jun 05 05:01:16 PM PDT 24 |
| Finished | Jun 05 05:01:42 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-6fe87086-a539-4930-aaea-5e359cdef157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672316485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.672316485 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3632171998 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4523520000 ps |
| CPU time | 17.21 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:01:30 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-58504097-a6e6-42f1-bd51-146ebe123d94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632171998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3632171998 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4181255213 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12308240000 ps |
| CPU time | 53.44 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:02:38 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-d16bb327-7907-4683-8039-607d88526918 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181255213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4181255213 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2167273036 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3571820000 ps |
| CPU time | 17.12 seconds |
| Started | Jun 05 05:00:56 PM PDT 24 |
| Finished | Jun 05 05:01:31 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-801ed7de-c3b1-4fc3-b543-112eb8a7f4c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167273036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2167273036 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.31011432 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13677820000 ps |
| CPU time | 57.29 seconds |
| Started | Jun 05 05:00:59 PM PDT 24 |
| Finished | Jun 05 05:02:52 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-7ea00b88-9a9d-4633-b8ea-077922485e63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31011432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.31011432 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2037058667 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10730340000 ps |
| CPU time | 44.51 seconds |
| Started | Jun 05 05:00:57 PM PDT 24 |
| Finished | Jun 05 05:02:24 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-048974d6-d8ff-44b3-a788-ee4a52e57f85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2037058667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2037058667 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |