| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/12.prim_present_test.302536720 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.339995861 |
| /workspace/coverage/default/1.prim_present_test.596417854 |
| /workspace/coverage/default/10.prim_present_test.4109101782 |
| /workspace/coverage/default/11.prim_present_test.708624186 |
| /workspace/coverage/default/13.prim_present_test.225006137 |
| /workspace/coverage/default/14.prim_present_test.913547008 |
| /workspace/coverage/default/15.prim_present_test.2433721596 |
| /workspace/coverage/default/16.prim_present_test.1626047471 |
| /workspace/coverage/default/17.prim_present_test.4269720324 |
| /workspace/coverage/default/18.prim_present_test.2081107752 |
| /workspace/coverage/default/19.prim_present_test.4098123755 |
| /workspace/coverage/default/2.prim_present_test.3720251817 |
| /workspace/coverage/default/20.prim_present_test.894757676 |
| /workspace/coverage/default/21.prim_present_test.2707244506 |
| /workspace/coverage/default/22.prim_present_test.4243492821 |
| /workspace/coverage/default/23.prim_present_test.2038218984 |
| /workspace/coverage/default/24.prim_present_test.2343422063 |
| /workspace/coverage/default/25.prim_present_test.3871524880 |
| /workspace/coverage/default/26.prim_present_test.1876755674 |
| /workspace/coverage/default/27.prim_present_test.1872724723 |
| /workspace/coverage/default/28.prim_present_test.516053296 |
| /workspace/coverage/default/29.prim_present_test.1735776918 |
| /workspace/coverage/default/3.prim_present_test.3532744995 |
| /workspace/coverage/default/30.prim_present_test.1608750717 |
| /workspace/coverage/default/31.prim_present_test.4192653766 |
| /workspace/coverage/default/32.prim_present_test.3613651354 |
| /workspace/coverage/default/33.prim_present_test.2729348591 |
| /workspace/coverage/default/34.prim_present_test.404700705 |
| /workspace/coverage/default/35.prim_present_test.3117863 |
| /workspace/coverage/default/36.prim_present_test.2244100831 |
| /workspace/coverage/default/37.prim_present_test.598337817 |
| /workspace/coverage/default/38.prim_present_test.720196215 |
| /workspace/coverage/default/39.prim_present_test.1276591027 |
| /workspace/coverage/default/4.prim_present_test.1480764451 |
| /workspace/coverage/default/40.prim_present_test.4074050527 |
| /workspace/coverage/default/41.prim_present_test.262407078 |
| /workspace/coverage/default/42.prim_present_test.690757884 |
| /workspace/coverage/default/43.prim_present_test.2508386620 |
| /workspace/coverage/default/44.prim_present_test.1725971945 |
| /workspace/coverage/default/45.prim_present_test.1174097479 |
| /workspace/coverage/default/46.prim_present_test.827016839 |
| /workspace/coverage/default/47.prim_present_test.2417823936 |
| /workspace/coverage/default/48.prim_present_test.2188652098 |
| /workspace/coverage/default/49.prim_present_test.127287039 |
| /workspace/coverage/default/5.prim_present_test.1612821531 |
| /workspace/coverage/default/6.prim_present_test.2105104281 |
| /workspace/coverage/default/7.prim_present_test.1606207092 |
| /workspace/coverage/default/8.prim_present_test.470602087 |
| /workspace/coverage/default/9.prim_present_test.3184442498 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/26.prim_present_test.1876755674 | Jun 06 02:15:33 PM PDT 24 | Jun 06 02:15:58 PM PDT 24 | 3423640000 ps | ||
| T2 | /workspace/coverage/default/41.prim_present_test.262407078 | Jun 06 02:15:27 PM PDT 24 | Jun 06 02:16:24 PM PDT 24 | 7464800000 ps | ||
| T3 | /workspace/coverage/default/45.prim_present_test.1174097479 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:16:14 PM PDT 24 | 6958260000 ps | ||
| T4 | /workspace/coverage/default/47.prim_present_test.2417823936 | Jun 06 02:15:27 PM PDT 24 | Jun 06 02:16:44 PM PDT 24 | 10470560000 ps | ||
| T5 | /workspace/coverage/default/6.prim_present_test.2105104281 | Jun 06 02:15:27 PM PDT 24 | Jun 06 02:16:12 PM PDT 24 | 6501940000 ps | ||
| T6 | /workspace/coverage/default/38.prim_present_test.720196215 | Jun 06 02:15:30 PM PDT 24 | Jun 06 02:16:30 PM PDT 24 | 9784840000 ps | ||
| T7 | /workspace/coverage/default/12.prim_present_test.302536720 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:16:09 PM PDT 24 | 5681060000 ps | ||
| T8 | /workspace/coverage/default/20.prim_present_test.894757676 | Jun 06 02:15:27 PM PDT 24 | Jun 06 02:15:54 PM PDT 24 | 4131060000 ps | ||
| T9 | /workspace/coverage/default/46.prim_present_test.827016839 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:16:54 PM PDT 24 | 15254480000 ps | ||
| T10 | /workspace/coverage/default/19.prim_present_test.4098123755 | Jun 06 02:15:30 PM PDT 24 | Jun 06 02:16:40 PM PDT 24 | 11824640000 ps | ||
| T11 | /workspace/coverage/default/8.prim_present_test.470602087 | Jun 06 02:15:24 PM PDT 24 | Jun 06 02:15:49 PM PDT 24 | 3178740000 ps | ||
| T12 | /workspace/coverage/default/43.prim_present_test.2508386620 | Jun 06 02:15:27 PM PDT 24 | Jun 06 02:16:01 PM PDT 24 | 5638900000 ps | ||
| T13 | /workspace/coverage/default/0.prim_present_test.339995861 | Jun 06 02:15:18 PM PDT 24 | Jun 06 02:15:55 PM PDT 24 | 5397100000 ps | ||
| T14 | /workspace/coverage/default/36.prim_present_test.2244100831 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:16:58 PM PDT 24 | 13856380000 ps | ||
| T15 | /workspace/coverage/default/32.prim_present_test.3613651354 | Jun 06 02:15:26 PM PDT 24 | Jun 06 02:16:11 PM PDT 24 | 6442420000 ps | ||
| T16 | /workspace/coverage/default/48.prim_present_test.2188652098 | Jun 06 02:15:32 PM PDT 24 | Jun 06 02:16:32 PM PDT 24 | 8394180000 ps | ||
| T17 | /workspace/coverage/default/30.prim_present_test.1608750717 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:16:16 PM PDT 24 | 7596240000 ps | ||
| T18 | /workspace/coverage/default/29.prim_present_test.1735776918 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:16:36 PM PDT 24 | 9459960000 ps | ||
| T19 | /workspace/coverage/default/18.prim_present_test.2081107752 | Jun 06 02:15:24 PM PDT 24 | Jun 06 02:16:18 PM PDT 24 | 9464300000 ps | ||
| T20 | /workspace/coverage/default/3.prim_present_test.3532744995 | Jun 06 02:15:16 PM PDT 24 | Jun 06 02:15:59 PM PDT 24 | 6017100000 ps | ||
| T21 | /workspace/coverage/default/35.prim_present_test.3117863 | Jun 06 02:15:30 PM PDT 24 | Jun 06 02:16:24 PM PDT 24 | 8757500000 ps | ||
| T22 | /workspace/coverage/default/42.prim_present_test.690757884 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:17:05 PM PDT 24 | 14726240000 ps | ||
| T23 | /workspace/coverage/default/37.prim_present_test.598337817 | Jun 06 02:15:27 PM PDT 24 | Jun 06 02:16:57 PM PDT 24 | 11574780000 ps | ||
| T24 | /workspace/coverage/default/4.prim_present_test.1480764451 | Jun 06 02:15:16 PM PDT 24 | Jun 06 02:15:58 PM PDT 24 | 5844120000 ps | ||
| T25 | /workspace/coverage/default/24.prim_present_test.2343422063 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:16:16 PM PDT 24 | 7200060000 ps | ||
| T26 | /workspace/coverage/default/15.prim_present_test.2433721596 | Jun 06 02:15:24 PM PDT 24 | Jun 06 02:16:55 PM PDT 24 | 12725500000 ps | ||
| T27 | /workspace/coverage/default/28.prim_present_test.516053296 | Jun 06 02:15:26 PM PDT 24 | Jun 06 02:16:24 PM PDT 24 | 8611180000 ps | ||
| T28 | /workspace/coverage/default/22.prim_present_test.4243492821 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:16:14 PM PDT 24 | 6132420000 ps | ||
| T29 | /workspace/coverage/default/44.prim_present_test.1725971945 | Jun 06 02:15:26 PM PDT 24 | Jun 06 02:16:15 PM PDT 24 | 6607960000 ps | ||
| T30 | /workspace/coverage/default/7.prim_present_test.1606207092 | Jun 06 02:15:27 PM PDT 24 | Jun 06 02:16:03 PM PDT 24 | 4845920000 ps | ||
| T31 | /workspace/coverage/default/1.prim_present_test.596417854 | Jun 06 02:15:16 PM PDT 24 | Jun 06 02:16:50 PM PDT 24 | 14712600000 ps | ||
| T32 | /workspace/coverage/default/17.prim_present_test.4269720324 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:17:20 PM PDT 24 | 15087080000 ps | ||
| T33 | /workspace/coverage/default/31.prim_present_test.4192653766 | Jun 06 02:15:26 PM PDT 24 | Jun 06 02:16:25 PM PDT 24 | 9450040000 ps | ||
| T34 | /workspace/coverage/default/10.prim_present_test.4109101782 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:16:08 PM PDT 24 | 6707160000 ps | ||
| T35 | /workspace/coverage/default/16.prim_present_test.1626047471 | Jun 06 02:15:32 PM PDT 24 | Jun 06 02:16:06 PM PDT 24 | 4640080000 ps | ||
| T36 | /workspace/coverage/default/2.prim_present_test.3720251817 | Jun 06 02:15:17 PM PDT 24 | Jun 06 02:15:45 PM PDT 24 | 3158900000 ps | ||
| T37 | /workspace/coverage/default/21.prim_present_test.2707244506 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:17:04 PM PDT 24 | 13832820000 ps | ||
| T38 | /workspace/coverage/default/9.prim_present_test.3184442498 | Jun 06 02:15:32 PM PDT 24 | Jun 06 02:16:44 PM PDT 24 | 10104760000 ps | ||
| T39 | /workspace/coverage/default/11.prim_present_test.708624186 | Jun 06 02:15:24 PM PDT 24 | Jun 06 02:16:36 PM PDT 24 | 11872380000 ps | ||
| T40 | /workspace/coverage/default/23.prim_present_test.2038218984 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:17:05 PM PDT 24 | 14222180000 ps | ||
| T41 | /workspace/coverage/default/39.prim_present_test.1276591027 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:16:05 PM PDT 24 | 5124300000 ps | ||
| T42 | /workspace/coverage/default/49.prim_present_test.127287039 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:17:16 PM PDT 24 | 14397020000 ps | ||
| T43 | /workspace/coverage/default/34.prim_present_test.404700705 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:16:03 PM PDT 24 | 4353640000 ps | ||
| T44 | /workspace/coverage/default/33.prim_present_test.2729348591 | Jun 06 02:15:26 PM PDT 24 | Jun 06 02:17:09 PM PDT 24 | 13297760000 ps | ||
| T45 | /workspace/coverage/default/25.prim_present_test.3871524880 | Jun 06 02:15:25 PM PDT 24 | Jun 06 02:16:20 PM PDT 24 | 8268320000 ps | ||
| T46 | /workspace/coverage/default/13.prim_present_test.225006137 | Jun 06 02:15:28 PM PDT 24 | Jun 06 02:16:00 PM PDT 24 | 4638840000 ps | ||
| T47 | /workspace/coverage/default/14.prim_present_test.913547008 | Jun 06 02:15:32 PM PDT 24 | Jun 06 02:16:40 PM PDT 24 | 9308680000 ps | ||
| T48 | /workspace/coverage/default/5.prim_present_test.1612821531 | Jun 06 02:15:27 PM PDT 24 | Jun 06 02:16:44 PM PDT 24 | 12351640000 ps | ||
| T49 | /workspace/coverage/default/40.prim_present_test.4074050527 | Jun 06 02:15:24 PM PDT 24 | Jun 06 02:16:44 PM PDT 24 | 12514080000 ps | ||
| T50 | /workspace/coverage/default/27.prim_present_test.1872724723 | Jun 06 02:15:26 PM PDT 24 | Jun 06 02:16:50 PM PDT 24 | 12969160000 ps |
| Test location | /workspace/coverage/default/12.prim_present_test.302536720 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5681060000 ps |
| CPU time | 22.45 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:16:09 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-663d2637-4e33-46a1-8527-78aeae7a2864 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302536720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.302536720 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.339995861 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5397100000 ps |
| CPU time | 19.63 seconds |
| Started | Jun 06 02:15:18 PM PDT 24 |
| Finished | Jun 06 02:15:55 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-8d185ba6-1106-4948-b6b9-448adcefaa9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339995861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.339995861 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.596417854 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14712600000 ps |
| CPU time | 49.88 seconds |
| Started | Jun 06 02:15:16 PM PDT 24 |
| Finished | Jun 06 02:16:50 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-60f2a89b-9de8-4f16-951e-94655441e73d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596417854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.596417854 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.4109101782 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6707160000 ps |
| CPU time | 22.35 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:16:08 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-48a12c2f-9e30-49d0-a374-841d2258a60a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109101782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.4109101782 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.708624186 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11872380000 ps |
| CPU time | 37.72 seconds |
| Started | Jun 06 02:15:24 PM PDT 24 |
| Finished | Jun 06 02:16:36 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-d52d3525-afe0-451d-9eae-39a50124442d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=708624186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.708624186 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.225006137 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4638840000 ps |
| CPU time | 17.41 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:16:00 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-ed285825-e895-4ac6-85a4-c9d7c2690091 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225006137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.225006137 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.913547008 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9308680000 ps |
| CPU time | 34.74 seconds |
| Started | Jun 06 02:15:32 PM PDT 24 |
| Finished | Jun 06 02:16:40 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-e1720b1d-21f0-4ea8-ad95-bf3b619ffd20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913547008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.913547008 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2433721596 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12725500000 ps |
| CPU time | 47.67 seconds |
| Started | Jun 06 02:15:24 PM PDT 24 |
| Finished | Jun 06 02:16:55 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-41aa30f0-c8e6-448f-b92f-ad6cdb4bb323 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433721596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2433721596 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1626047471 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4640080000 ps |
| CPU time | 16.8 seconds |
| Started | Jun 06 02:15:32 PM PDT 24 |
| Finished | Jun 06 02:16:06 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-0a9a28b7-19a0-4393-98e4-8d289f97e32c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626047471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1626047471 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4269720324 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 15087080000 ps |
| CPU time | 57.54 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:17:20 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-01d1310e-bccc-4ce7-b4ea-c0df8a941e0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269720324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4269720324 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2081107752 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9464300000 ps |
| CPU time | 28.22 seconds |
| Started | Jun 06 02:15:24 PM PDT 24 |
| Finished | Jun 06 02:16:18 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-95c366eb-f1f8-4f68-a491-29126a02690b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081107752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2081107752 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.4098123755 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11824640000 ps |
| CPU time | 37.27 seconds |
| Started | Jun 06 02:15:30 PM PDT 24 |
| Finished | Jun 06 02:16:40 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-f8c128c1-fc68-40bc-b34d-29bc52fe00a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098123755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.4098123755 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3720251817 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3158900000 ps |
| CPU time | 14.34 seconds |
| Started | Jun 06 02:15:17 PM PDT 24 |
| Finished | Jun 06 02:15:45 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-c8d9d54e-3c5a-451a-b286-6d74f0c0e40a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720251817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3720251817 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.894757676 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4131060000 ps |
| CPU time | 14.37 seconds |
| Started | Jun 06 02:15:27 PM PDT 24 |
| Finished | Jun 06 02:15:54 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-bbcd1802-9edb-4dc5-8aa7-fad316048572 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=894757676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.894757676 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2707244506 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13832820000 ps |
| CPU time | 50.28 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:17:04 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-f71bb30a-a1e7-45d8-9415-e1ead0e4bdaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707244506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2707244506 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.4243492821 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6132420000 ps |
| CPU time | 23.3 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:16:14 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-2fddc9e2-1647-457d-bcfb-008eea3d3bf0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243492821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.4243492821 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2038218984 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14222180000 ps |
| CPU time | 52.74 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:17:05 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-54b01dab-1fb7-4c38-9af2-45b706a90eea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038218984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2038218984 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2343422063 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7200060000 ps |
| CPU time | 26.45 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:16:16 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-5868e52b-6acd-4ab7-8939-32ae6877ef15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343422063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2343422063 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3871524880 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8268320000 ps |
| CPU time | 28.93 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:16:20 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-87cb0e15-d3eb-435a-90b6-25269f658403 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871524880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3871524880 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1876755674 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3423640000 ps |
| CPU time | 12.55 seconds |
| Started | Jun 06 02:15:33 PM PDT 24 |
| Finished | Jun 06 02:15:58 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-f0179212-3c8d-4e46-afea-686f2a6f4fa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876755674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1876755674 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1872724723 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12969160000 ps |
| CPU time | 44.73 seconds |
| Started | Jun 06 02:15:26 PM PDT 24 |
| Finished | Jun 06 02:16:50 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a0f41677-bfe9-466d-a9a5-f63f0b02d634 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872724723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1872724723 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.516053296 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8611180000 ps |
| CPU time | 30.27 seconds |
| Started | Jun 06 02:15:26 PM PDT 24 |
| Finished | Jun 06 02:16:24 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-60690f1c-91bb-44ae-ad63-95b8c3b32d37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516053296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.516053296 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1735776918 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9459960000 ps |
| CPU time | 35.39 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:16:36 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-0fc87af7-38aa-4a6f-bb69-2be8f2dbeaec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735776918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1735776918 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3532744995 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6017100000 ps |
| CPU time | 22.23 seconds |
| Started | Jun 06 02:15:16 PM PDT 24 |
| Finished | Jun 06 02:15:59 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-f51a43d1-7d8d-4d37-b481-3d60cebf3856 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532744995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3532744995 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1608750717 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7596240000 ps |
| CPU time | 26.99 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:16:16 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-c6f9528e-4b95-4f06-be69-96c3ea1fb6d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608750717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1608750717 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.4192653766 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9450040000 ps |
| CPU time | 31.35 seconds |
| Started | Jun 06 02:15:26 PM PDT 24 |
| Finished | Jun 06 02:16:25 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-bb7582f5-d5c8-4824-aae2-174e4e53188f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192653766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4192653766 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3613651354 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6442420000 ps |
| CPU time | 23.89 seconds |
| Started | Jun 06 02:15:26 PM PDT 24 |
| Finished | Jun 06 02:16:11 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-2b9cba97-99b0-4f4d-aa81-6cc83b70e429 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3613651354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3613651354 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2729348591 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13297760000 ps |
| CPU time | 52.85 seconds |
| Started | Jun 06 02:15:26 PM PDT 24 |
| Finished | Jun 06 02:17:09 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-0ead3513-4347-468d-bdd1-e173a17c7214 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2729348591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2729348591 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.404700705 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4353640000 ps |
| CPU time | 17.83 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:16:03 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-593e056f-323d-4a8f-898e-ca6deb5b8086 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404700705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.404700705 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3117863 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8757500000 ps |
| CPU time | 29.18 seconds |
| Started | Jun 06 02:15:30 PM PDT 24 |
| Finished | Jun 06 02:16:24 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-e20fcac5-7747-482f-99d3-26743541700f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3117863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3117863 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2244100831 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13856380000 ps |
| CPU time | 48.47 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:16:58 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-e230eff8-e064-4270-971f-f644b2184046 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244100831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2244100831 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.598337817 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11574780000 ps |
| CPU time | 46.41 seconds |
| Started | Jun 06 02:15:27 PM PDT 24 |
| Finished | Jun 06 02:16:57 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-32650484-0300-445f-9808-4b03c82bb7aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598337817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.598337817 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.720196215 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9784840000 ps |
| CPU time | 31.9 seconds |
| Started | Jun 06 02:15:30 PM PDT 24 |
| Finished | Jun 06 02:16:30 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-86606846-319d-4e39-a10f-b033081ac56d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720196215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.720196215 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1276591027 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5124300000 ps |
| CPU time | 18.18 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:16:05 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-840c458c-adf1-499c-8cd1-6e8cdf61979f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276591027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1276591027 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1480764451 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5844120000 ps |
| CPU time | 21.59 seconds |
| Started | Jun 06 02:15:16 PM PDT 24 |
| Finished | Jun 06 02:15:58 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-875a1e49-95c3-4a2c-bbf2-a9ca622187ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1480764451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1480764451 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4074050527 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12514080000 ps |
| CPU time | 42.02 seconds |
| Started | Jun 06 02:15:24 PM PDT 24 |
| Finished | Jun 06 02:16:44 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-39faf6a2-faf2-4a43-87d7-6d2c1e45e1e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074050527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4074050527 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.262407078 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7464800000 ps |
| CPU time | 29.08 seconds |
| Started | Jun 06 02:15:27 PM PDT 24 |
| Finished | Jun 06 02:16:24 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-d2d974df-4d4a-403a-847d-48b4237495ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262407078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.262407078 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.690757884 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14726240000 ps |
| CPU time | 51.86 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:17:05 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-eaa26e99-0002-4068-86f6-99d23ea78d45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690757884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.690757884 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2508386620 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5638900000 ps |
| CPU time | 18.37 seconds |
| Started | Jun 06 02:15:27 PM PDT 24 |
| Finished | Jun 06 02:16:01 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-daa7f4a1-b25f-40d0-b444-37d66ccab118 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508386620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2508386620 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1725971945 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6607960000 ps |
| CPU time | 25.33 seconds |
| Started | Jun 06 02:15:26 PM PDT 24 |
| Finished | Jun 06 02:16:15 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-9e563a21-ad10-432c-9725-0897f9f44255 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725971945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1725971945 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1174097479 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6958260000 ps |
| CPU time | 25.71 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:16:14 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-4106be71-abf1-46b9-b158-920d214bbe93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174097479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1174097479 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.827016839 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 15254480000 ps |
| CPU time | 47.18 seconds |
| Started | Jun 06 02:15:25 PM PDT 24 |
| Finished | Jun 06 02:16:54 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-24d3932a-cf91-46e2-ad53-b1833248d44c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827016839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.827016839 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2417823936 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10470560000 ps |
| CPU time | 40.28 seconds |
| Started | Jun 06 02:15:27 PM PDT 24 |
| Finished | Jun 06 02:16:44 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-c06a25a1-f8da-4ac5-8b08-b7930874ce4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417823936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2417823936 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2188652098 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8394180000 ps |
| CPU time | 30.51 seconds |
| Started | Jun 06 02:15:32 PM PDT 24 |
| Finished | Jun 06 02:16:32 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-a372336b-bc8c-47d6-ab30-cc3ab43a5130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188652098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2188652098 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.127287039 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14397020000 ps |
| CPU time | 55.41 seconds |
| Started | Jun 06 02:15:28 PM PDT 24 |
| Finished | Jun 06 02:17:16 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-1a4e03bb-2d08-4ab5-afed-037788c4983f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=127287039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.127287039 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1612821531 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12351640000 ps |
| CPU time | 39.64 seconds |
| Started | Jun 06 02:15:27 PM PDT 24 |
| Finished | Jun 06 02:16:44 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-0bd46c4c-a870-4b2e-85f7-6a1ea8167483 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612821531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1612821531 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2105104281 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 6501940000 ps |
| CPU time | 23.42 seconds |
| Started | Jun 06 02:15:27 PM PDT 24 |
| Finished | Jun 06 02:16:12 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-80062b14-b9dc-47f8-b5f4-62beb4b291a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105104281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2105104281 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1606207092 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4845920000 ps |
| CPU time | 17.37 seconds |
| Started | Jun 06 02:15:27 PM PDT 24 |
| Finished | Jun 06 02:16:03 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-db2b2dbb-61a8-44ab-b594-7ebf389fa603 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606207092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1606207092 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.470602087 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3178740000 ps |
| CPU time | 12.54 seconds |
| Started | Jun 06 02:15:24 PM PDT 24 |
| Finished | Jun 06 02:15:49 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-9b922a0f-d999-47cd-9fdd-877499b444d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470602087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.470602087 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3184442498 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10104760000 ps |
| CPU time | 36.9 seconds |
| Started | Jun 06 02:15:32 PM PDT 24 |
| Finished | Jun 06 02:16:44 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-aa6d9d74-24d3-41c6-9226-4cee271566f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3184442498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3184442498 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |