| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.2554830726 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3166486390 |
| /workspace/coverage/default/1.prim_present_test.3805533218 |
| /workspace/coverage/default/11.prim_present_test.1657637369 |
| /workspace/coverage/default/12.prim_present_test.2489294972 |
| /workspace/coverage/default/13.prim_present_test.682228965 |
| /workspace/coverage/default/14.prim_present_test.395415507 |
| /workspace/coverage/default/15.prim_present_test.1791879561 |
| /workspace/coverage/default/16.prim_present_test.1234628598 |
| /workspace/coverage/default/17.prim_present_test.638324300 |
| /workspace/coverage/default/18.prim_present_test.366445086 |
| /workspace/coverage/default/19.prim_present_test.1748471672 |
| /workspace/coverage/default/2.prim_present_test.1975262056 |
| /workspace/coverage/default/20.prim_present_test.2700525701 |
| /workspace/coverage/default/21.prim_present_test.3916801070 |
| /workspace/coverage/default/22.prim_present_test.3506782042 |
| /workspace/coverage/default/23.prim_present_test.2606270917 |
| /workspace/coverage/default/24.prim_present_test.3696945826 |
| /workspace/coverage/default/25.prim_present_test.3057725389 |
| /workspace/coverage/default/26.prim_present_test.773863705 |
| /workspace/coverage/default/27.prim_present_test.2387438406 |
| /workspace/coverage/default/28.prim_present_test.2083169884 |
| /workspace/coverage/default/29.prim_present_test.3922464222 |
| /workspace/coverage/default/3.prim_present_test.3132623057 |
| /workspace/coverage/default/30.prim_present_test.3271327409 |
| /workspace/coverage/default/31.prim_present_test.3347098635 |
| /workspace/coverage/default/32.prim_present_test.3852250941 |
| /workspace/coverage/default/33.prim_present_test.1262847481 |
| /workspace/coverage/default/34.prim_present_test.2856033050 |
| /workspace/coverage/default/35.prim_present_test.2700386147 |
| /workspace/coverage/default/36.prim_present_test.3192343941 |
| /workspace/coverage/default/37.prim_present_test.3570986658 |
| /workspace/coverage/default/38.prim_present_test.1310748357 |
| /workspace/coverage/default/39.prim_present_test.3524516385 |
| /workspace/coverage/default/4.prim_present_test.2461807592 |
| /workspace/coverage/default/40.prim_present_test.313115026 |
| /workspace/coverage/default/41.prim_present_test.1123360462 |
| /workspace/coverage/default/42.prim_present_test.3817624230 |
| /workspace/coverage/default/43.prim_present_test.4197696965 |
| /workspace/coverage/default/44.prim_present_test.354167390 |
| /workspace/coverage/default/45.prim_present_test.1847587736 |
| /workspace/coverage/default/46.prim_present_test.2925212267 |
| /workspace/coverage/default/47.prim_present_test.1260524168 |
| /workspace/coverage/default/48.prim_present_test.3651031972 |
| /workspace/coverage/default/49.prim_present_test.499776300 |
| /workspace/coverage/default/5.prim_present_test.2854560028 |
| /workspace/coverage/default/6.prim_present_test.1547386878 |
| /workspace/coverage/default/7.prim_present_test.1780467368 |
| /workspace/coverage/default/8.prim_present_test.2140795950 |
| /workspace/coverage/default/9.prim_present_test.2581246278 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_present_test.2489294972 | Jun 07 07:56:40 PM PDT 24 | Jun 07 07:57:25 PM PDT 24 | 5920380000 ps | ||
| T2 | /workspace/coverage/default/16.prim_present_test.1234628598 | Jun 07 07:56:39 PM PDT 24 | Jun 07 07:58:25 PM PDT 24 | 13926440000 ps | ||
| T3 | /workspace/coverage/default/46.prim_present_test.2925212267 | Jun 07 07:56:49 PM PDT 24 | Jun 07 07:58:50 PM PDT 24 | 14251320000 ps | ||
| T4 | /workspace/coverage/default/34.prim_present_test.2856033050 | Jun 07 07:56:46 PM PDT 24 | Jun 07 07:58:32 PM PDT 24 | 15132340000 ps | ||
| T5 | /workspace/coverage/default/40.prim_present_test.313115026 | Jun 07 07:56:47 PM PDT 24 | Jun 07 07:58:29 PM PDT 24 | 14480100000 ps | ||
| T6 | /workspace/coverage/default/8.prim_present_test.2140795950 | Jun 07 07:56:38 PM PDT 24 | Jun 07 07:58:15 PM PDT 24 | 12894760000 ps | ||
| T7 | /workspace/coverage/default/38.prim_present_test.1310748357 | Jun 07 07:56:46 PM PDT 24 | Jun 07 07:58:07 PM PDT 24 | 10887200000 ps | ||
| T8 | /workspace/coverage/default/10.prim_present_test.2554830726 | Jun 07 07:56:39 PM PDT 24 | Jun 07 07:57:22 PM PDT 24 | 6635240000 ps | ||
| T9 | /workspace/coverage/default/11.prim_present_test.1657637369 | Jun 07 07:56:40 PM PDT 24 | Jun 07 07:57:29 PM PDT 24 | 5883180000 ps | ||
| T10 | /workspace/coverage/default/44.prim_present_test.354167390 | Jun 07 07:56:50 PM PDT 24 | Jun 07 07:58:23 PM PDT 24 | 12089380000 ps | ||
| T11 | /workspace/coverage/default/24.prim_present_test.3696945826 | Jun 07 07:56:44 PM PDT 24 | Jun 07 07:57:51 PM PDT 24 | 9610000000 ps | ||
| T12 | /workspace/coverage/default/39.prim_present_test.3524516385 | Jun 07 07:56:46 PM PDT 24 | Jun 07 07:57:27 PM PDT 24 | 4747960000 ps | ||
| T13 | /workspace/coverage/default/20.prim_present_test.2700525701 | Jun 07 07:56:41 PM PDT 24 | Jun 07 07:58:28 PM PDT 24 | 14326960000 ps | ||
| T14 | /workspace/coverage/default/47.prim_present_test.1260524168 | Jun 07 07:56:49 PM PDT 24 | Jun 07 07:58:18 PM PDT 24 | 9939840000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.1547386878 | Jun 07 07:56:40 PM PDT 24 | Jun 07 07:58:47 PM PDT 24 | 15341900000 ps | ||
| T16 | /workspace/coverage/default/14.prim_present_test.395415507 | Jun 07 07:56:38 PM PDT 24 | Jun 07 07:57:06 PM PDT 24 | 4055420000 ps | ||
| T17 | /workspace/coverage/default/2.prim_present_test.1975262056 | Jun 07 07:56:38 PM PDT 24 | Jun 07 07:57:38 PM PDT 24 | 8241660000 ps | ||
| T18 | /workspace/coverage/default/17.prim_present_test.638324300 | Jun 07 07:56:39 PM PDT 24 | Jun 07 07:57:21 PM PDT 24 | 5903020000 ps | ||
| T19 | /workspace/coverage/default/30.prim_present_test.3271327409 | Jun 07 07:56:50 PM PDT 24 | Jun 07 07:58:44 PM PDT 24 | 14555120000 ps | ||
| T20 | /workspace/coverage/default/13.prim_present_test.682228965 | Jun 07 07:56:39 PM PDT 24 | Jun 07 07:57:37 PM PDT 24 | 9526920000 ps | ||
| T21 | /workspace/coverage/default/27.prim_present_test.2387438406 | Jun 07 07:56:48 PM PDT 24 | Jun 07 07:57:33 PM PDT 24 | 6537280000 ps | ||
| T22 | /workspace/coverage/default/41.prim_present_test.1123360462 | Jun 07 07:56:45 PM PDT 24 | Jun 07 07:57:53 PM PDT 24 | 9192740000 ps | ||
| T23 | /workspace/coverage/default/0.prim_present_test.3166486390 | Jun 07 07:56:38 PM PDT 24 | Jun 07 07:58:09 PM PDT 24 | 12551900000 ps | ||
| T24 | /workspace/coverage/default/37.prim_present_test.3570986658 | Jun 07 07:56:47 PM PDT 24 | Jun 07 07:58:16 PM PDT 24 | 12431620000 ps | ||
| T25 | /workspace/coverage/default/3.prim_present_test.3132623057 | Jun 07 07:56:38 PM PDT 24 | Jun 07 07:57:35 PM PDT 24 | 7986840000 ps | ||
| T26 | /workspace/coverage/default/42.prim_present_test.3817624230 | Jun 07 07:56:48 PM PDT 24 | Jun 07 07:57:23 PM PDT 24 | 4661780000 ps | ||
| T27 | /workspace/coverage/default/28.prim_present_test.2083169884 | Jun 07 07:56:47 PM PDT 24 | Jun 07 07:57:35 PM PDT 24 | 6920440000 ps | ||
| T28 | /workspace/coverage/default/15.prim_present_test.1791879561 | Jun 07 07:56:44 PM PDT 24 | Jun 07 07:58:02 PM PDT 24 | 10808460000 ps | ||
| T29 | /workspace/coverage/default/25.prim_present_test.3057725389 | Jun 07 07:56:41 PM PDT 24 | Jun 07 07:57:10 PM PDT 24 | 4243900000 ps | ||
| T30 | /workspace/coverage/default/48.prim_present_test.3651031972 | Jun 07 07:56:49 PM PDT 24 | Jun 07 07:57:36 PM PDT 24 | 5026960000 ps | ||
| T31 | /workspace/coverage/default/21.prim_present_test.3916801070 | Jun 07 07:56:38 PM PDT 24 | Jun 07 07:57:53 PM PDT 24 | 10865500000 ps | ||
| T32 | /workspace/coverage/default/32.prim_present_test.3852250941 | Jun 07 07:56:48 PM PDT 24 | Jun 07 07:57:49 PM PDT 24 | 7650800000 ps | ||
| T33 | /workspace/coverage/default/26.prim_present_test.773863705 | Jun 07 07:56:50 PM PDT 24 | Jun 07 07:57:56 PM PDT 24 | 7585080000 ps | ||
| T34 | /workspace/coverage/default/19.prim_present_test.1748471672 | Jun 07 07:56:39 PM PDT 24 | Jun 07 07:57:48 PM PDT 24 | 11452640000 ps | ||
| T35 | /workspace/coverage/default/23.prim_present_test.2606270917 | Jun 07 07:56:42 PM PDT 24 | Jun 07 07:58:00 PM PDT 24 | 10083060000 ps | ||
| T36 | /workspace/coverage/default/5.prim_present_test.2854560028 | Jun 07 07:56:39 PM PDT 24 | Jun 07 07:58:33 PM PDT 24 | 14103760000 ps | ||
| T37 | /workspace/coverage/default/9.prim_present_test.2581246278 | Jun 07 07:56:40 PM PDT 24 | Jun 07 07:58:08 PM PDT 24 | 11160000000 ps | ||
| T38 | /workspace/coverage/default/7.prim_present_test.1780467368 | Jun 07 07:56:38 PM PDT 24 | Jun 07 07:57:45 PM PDT 24 | 9177240000 ps | ||
| T39 | /workspace/coverage/default/22.prim_present_test.3506782042 | Jun 07 07:56:40 PM PDT 24 | Jun 07 07:58:15 PM PDT 24 | 12912120000 ps | ||
| T40 | /workspace/coverage/default/31.prim_present_test.3347098635 | Jun 07 07:56:45 PM PDT 24 | Jun 07 07:58:15 PM PDT 24 | 11535100000 ps | ||
| T41 | /workspace/coverage/default/29.prim_present_test.3922464222 | Jun 07 07:56:50 PM PDT 24 | Jun 07 07:57:36 PM PDT 24 | 4862040000 ps | ||
| T42 | /workspace/coverage/default/4.prim_present_test.2461807592 | Jun 07 07:56:40 PM PDT 24 | Jun 07 07:57:55 PM PDT 24 | 8937920000 ps | ||
| T43 | /workspace/coverage/default/36.prim_present_test.3192343941 | Jun 07 07:56:46 PM PDT 24 | Jun 07 07:58:16 PM PDT 24 | 13036120000 ps | ||
| T44 | /workspace/coverage/default/43.prim_present_test.4197696965 | Jun 07 07:56:49 PM PDT 24 | Jun 07 07:58:36 PM PDT 24 | 12461380000 ps | ||
| T45 | /workspace/coverage/default/35.prim_present_test.2700386147 | Jun 07 07:56:47 PM PDT 24 | Jun 07 07:58:45 PM PDT 24 | 15477060000 ps | ||
| T46 | /workspace/coverage/default/1.prim_present_test.3805533218 | Jun 07 07:56:36 PM PDT 24 | Jun 07 07:58:02 PM PDT 24 | 12382020000 ps | ||
| T47 | /workspace/coverage/default/18.prim_present_test.366445086 | Jun 07 07:56:39 PM PDT 24 | Jun 07 07:58:33 PM PDT 24 | 13446560000 ps | ||
| T48 | /workspace/coverage/default/45.prim_present_test.1847587736 | Jun 07 07:56:49 PM PDT 24 | Jun 07 07:58:58 PM PDT 24 | 15434900000 ps | ||
| T49 | /workspace/coverage/default/33.prim_present_test.1262847481 | Jun 07 07:56:47 PM PDT 24 | Jun 07 07:58:12 PM PDT 24 | 10859920000 ps | ||
| T50 | /workspace/coverage/default/49.prim_present_test.499776300 | Jun 07 07:56:49 PM PDT 24 | Jun 07 07:58:55 PM PDT 24 | 14844040000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.2554830726 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6635240000 ps |
| CPU time | 21.27 seconds |
| Started | Jun 07 07:56:39 PM PDT 24 |
| Finished | Jun 07 07:57:22 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-bc51b15a-69bb-4a70-a7c7-931b5fb80d20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554830726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2554830726 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3166486390 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12551900000 ps |
| CPU time | 47.18 seconds |
| Started | Jun 07 07:56:38 PM PDT 24 |
| Finished | Jun 07 07:58:09 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-da2e1001-e89b-4ec7-bbfa-2e440a89397f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166486390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3166486390 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3805533218 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12382020000 ps |
| CPU time | 45.3 seconds |
| Started | Jun 07 07:56:36 PM PDT 24 |
| Finished | Jun 07 07:58:02 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-38cc095a-4305-4718-ad38-c7e02a3edfcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805533218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3805533218 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1657637369 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5883180000 ps |
| CPU time | 24.03 seconds |
| Started | Jun 07 07:56:40 PM PDT 24 |
| Finished | Jun 07 07:57:29 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-1d89345d-75f5-4b58-a09d-aa77aae08133 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657637369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1657637369 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2489294972 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5920380000 ps |
| CPU time | 22 seconds |
| Started | Jun 07 07:56:40 PM PDT 24 |
| Finished | Jun 07 07:57:25 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-c81785b0-39ff-458e-9517-c428b3e70698 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489294972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2489294972 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.682228965 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9526920000 ps |
| CPU time | 29.72 seconds |
| Started | Jun 07 07:56:39 PM PDT 24 |
| Finished | Jun 07 07:57:37 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-32746866-d0f6-4de8-98c4-aae70efe2683 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682228965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.682228965 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.395415507 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4055420000 ps |
| CPU time | 13.69 seconds |
| Started | Jun 07 07:56:38 PM PDT 24 |
| Finished | Jun 07 07:57:06 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-e635e5e0-9e8a-40ce-bab8-b81b5ad084f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=395415507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.395415507 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1791879561 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10808460000 ps |
| CPU time | 40.04 seconds |
| Started | Jun 07 07:56:44 PM PDT 24 |
| Finished | Jun 07 07:58:02 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-6ccee48d-9469-4985-97b1-ac5bf7412514 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791879561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1791879561 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1234628598 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13926440000 ps |
| CPU time | 53.7 seconds |
| Started | Jun 07 07:56:39 PM PDT 24 |
| Finished | Jun 07 07:58:25 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-5285d7e1-a54e-4c32-b89d-d96d082e4c3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234628598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1234628598 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.638324300 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5903020000 ps |
| CPU time | 21.02 seconds |
| Started | Jun 07 07:56:39 PM PDT 24 |
| Finished | Jun 07 07:57:21 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-a579a252-234b-47c0-b7d8-d89c3810b569 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638324300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.638324300 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.366445086 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13446560000 ps |
| CPU time | 55.1 seconds |
| Started | Jun 07 07:56:39 PM PDT 24 |
| Finished | Jun 07 07:58:33 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-0d74f41b-c77e-497b-81be-2c9c4489104c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366445086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.366445086 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1748471672 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11452640000 ps |
| CPU time | 35.38 seconds |
| Started | Jun 07 07:56:39 PM PDT 24 |
| Finished | Jun 07 07:57:48 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-48a06e76-13fa-45e9-bdf8-a14f5d89366f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748471672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1748471672 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1975262056 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8241660000 ps |
| CPU time | 30.66 seconds |
| Started | Jun 07 07:56:38 PM PDT 24 |
| Finished | Jun 07 07:57:38 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-05179405-b385-42b2-a871-cb0bfd7e7827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975262056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1975262056 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2700525701 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14326960000 ps |
| CPU time | 54.72 seconds |
| Started | Jun 07 07:56:41 PM PDT 24 |
| Finished | Jun 07 07:58:28 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-bafc3e2e-ba89-419d-b297-751c37c775da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700525701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2700525701 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3916801070 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10865500000 ps |
| CPU time | 38.67 seconds |
| Started | Jun 07 07:56:38 PM PDT 24 |
| Finished | Jun 07 07:57:53 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-7a51b423-b6b1-41c9-b559-4a1a08eaa9f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916801070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3916801070 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3506782042 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12912120000 ps |
| CPU time | 48.48 seconds |
| Started | Jun 07 07:56:40 PM PDT 24 |
| Finished | Jun 07 07:58:15 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-7a19201e-5ede-426e-a5b0-b0db356e4127 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506782042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3506782042 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2606270917 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10083060000 ps |
| CPU time | 39.02 seconds |
| Started | Jun 07 07:56:42 PM PDT 24 |
| Finished | Jun 07 07:58:00 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-314d3679-b0d0-48ae-91ca-03e9cf6af03c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606270917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2606270917 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3696945826 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9610000000 ps |
| CPU time | 33.56 seconds |
| Started | Jun 07 07:56:44 PM PDT 24 |
| Finished | Jun 07 07:57:51 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-4b5fd83d-d7a2-4fc4-b496-1e1577429515 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696945826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3696945826 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3057725389 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4243900000 ps |
| CPU time | 14.18 seconds |
| Started | Jun 07 07:56:41 PM PDT 24 |
| Finished | Jun 07 07:57:10 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-e60814ae-3922-4581-8ddd-ac67b94383b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057725389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3057725389 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.773863705 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7585080000 ps |
| CPU time | 31.6 seconds |
| Started | Jun 07 07:56:50 PM PDT 24 |
| Finished | Jun 07 07:57:56 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-4cfb1f36-e1ac-40a3-86db-9520cb2b7f0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773863705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.773863705 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2387438406 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6537280000 ps |
| CPU time | 21.9 seconds |
| Started | Jun 07 07:56:48 PM PDT 24 |
| Finished | Jun 07 07:57:33 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-8dbe0b5d-eb76-437b-b3eb-b8ab0078b47c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387438406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2387438406 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2083169884 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6920440000 ps |
| CPU time | 23.7 seconds |
| Started | Jun 07 07:56:47 PM PDT 24 |
| Finished | Jun 07 07:57:35 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-1ba29f34-7b81-4562-8934-1fe038089194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083169884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2083169884 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3922464222 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4862040000 ps |
| CPU time | 21.27 seconds |
| Started | Jun 07 07:56:50 PM PDT 24 |
| Finished | Jun 07 07:57:36 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-74e28d6e-8353-463d-be48-5d1ab231ea89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922464222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3922464222 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3132623057 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7986840000 ps |
| CPU time | 28.74 seconds |
| Started | Jun 07 07:56:38 PM PDT 24 |
| Finished | Jun 07 07:57:35 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-f856fd4f-0109-41e4-b5dd-f8fe810e02f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132623057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3132623057 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3271327409 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14555120000 ps |
| CPU time | 56.7 seconds |
| Started | Jun 07 07:56:50 PM PDT 24 |
| Finished | Jun 07 07:58:44 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-a368aac4-e47f-40ba-8595-b4b38019d4b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271327409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3271327409 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3347098635 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11535100000 ps |
| CPU time | 45.58 seconds |
| Started | Jun 07 07:56:45 PM PDT 24 |
| Finished | Jun 07 07:58:15 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-bede2781-6ef7-40c2-bf8d-e76f290e8e42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347098635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3347098635 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3852250941 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7650800000 ps |
| CPU time | 29.21 seconds |
| Started | Jun 07 07:56:48 PM PDT 24 |
| Finished | Jun 07 07:57:49 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-d7e09717-0f85-4a24-b7ec-63f2726ce812 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852250941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3852250941 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1262847481 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10859920000 ps |
| CPU time | 43.05 seconds |
| Started | Jun 07 07:56:47 PM PDT 24 |
| Finished | Jun 07 07:58:12 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-491313e3-7ff6-43f8-b07b-fecbebcee118 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262847481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1262847481 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2856033050 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15132340000 ps |
| CPU time | 53.07 seconds |
| Started | Jun 07 07:56:46 PM PDT 24 |
| Finished | Jun 07 07:58:32 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-31ce3f6e-38b7-4214-b193-29b19bc680ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856033050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2856033050 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2700386147 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 15477060000 ps |
| CPU time | 60.35 seconds |
| Started | Jun 07 07:56:47 PM PDT 24 |
| Finished | Jun 07 07:58:45 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-9e7a87cf-b3b7-4f1f-866e-c77cb6914fc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700386147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2700386147 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3192343941 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13036120000 ps |
| CPU time | 46.04 seconds |
| Started | Jun 07 07:56:46 PM PDT 24 |
| Finished | Jun 07 07:58:16 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-aff6fd13-cc0e-40c8-8599-82ec36b4e0be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192343941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3192343941 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3570986658 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12431620000 ps |
| CPU time | 45.05 seconds |
| Started | Jun 07 07:56:47 PM PDT 24 |
| Finished | Jun 07 07:58:16 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-f7fb71f5-81ab-487c-a6ed-6ec8ca7e4faf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570986658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3570986658 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1310748357 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10887200000 ps |
| CPU time | 40.59 seconds |
| Started | Jun 07 07:56:46 PM PDT 24 |
| Finished | Jun 07 07:58:07 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-c8078371-ef2f-433e-85da-a006e4497020 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310748357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1310748357 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3524516385 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4747960000 ps |
| CPU time | 18.62 seconds |
| Started | Jun 07 07:56:46 PM PDT 24 |
| Finished | Jun 07 07:57:27 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-8137a1b4-4bad-4429-887f-01ad081b0cfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524516385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3524516385 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2461807592 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8937920000 ps |
| CPU time | 37.93 seconds |
| Started | Jun 07 07:56:40 PM PDT 24 |
| Finished | Jun 07 07:57:55 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-b36efa2e-de70-4646-9af1-3766271bbadf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461807592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2461807592 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.313115026 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14480100000 ps |
| CPU time | 50.91 seconds |
| Started | Jun 07 07:56:47 PM PDT 24 |
| Finished | Jun 07 07:58:29 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-4093dc4b-7c86-41b1-b161-f838b67579d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313115026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.313115026 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1123360462 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9192740000 ps |
| CPU time | 33.71 seconds |
| Started | Jun 07 07:56:45 PM PDT 24 |
| Finished | Jun 07 07:57:53 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-2172d62f-c32f-4bae-90f9-2428cafda01c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123360462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1123360462 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3817624230 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4661780000 ps |
| CPU time | 16.75 seconds |
| Started | Jun 07 07:56:48 PM PDT 24 |
| Finished | Jun 07 07:57:23 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-b4aedb96-4247-4ab3-ae69-5346ea9496da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817624230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3817624230 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4197696965 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12461380000 ps |
| CPU time | 50.47 seconds |
| Started | Jun 07 07:56:49 PM PDT 24 |
| Finished | Jun 07 07:58:36 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-f216b880-344e-41a7-bc9b-5a58e71ded2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197696965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4197696965 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.354167390 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12089380000 ps |
| CPU time | 45.99 seconds |
| Started | Jun 07 07:56:50 PM PDT 24 |
| Finished | Jun 07 07:58:23 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-7c933485-2cfa-4a44-9c93-19df4e04fd83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354167390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.354167390 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1847587736 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 15434900000 ps |
| CPU time | 61.66 seconds |
| Started | Jun 07 07:56:49 PM PDT 24 |
| Finished | Jun 07 07:58:58 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-1b62ad20-ad6f-4b6f-b3b9-2336d2e2ea3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1847587736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1847587736 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2925212267 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 14251320000 ps |
| CPU time | 57.49 seconds |
| Started | Jun 07 07:56:49 PM PDT 24 |
| Finished | Jun 07 07:58:50 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-d908360f-5fb8-4676-8200-24f74bd9cc59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925212267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2925212267 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1260524168 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9939840000 ps |
| CPU time | 41.19 seconds |
| Started | Jun 07 07:56:49 PM PDT 24 |
| Finished | Jun 07 07:58:18 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-a4c6c4c7-b1c1-4e93-ba70-89693cea238c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1260524168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1260524168 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3651031972 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5026960000 ps |
| CPU time | 20.64 seconds |
| Started | Jun 07 07:56:49 PM PDT 24 |
| Finished | Jun 07 07:57:36 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-1d09d6d0-54f8-45ed-a901-c823fd49e1c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651031972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3651031972 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.499776300 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14844040000 ps |
| CPU time | 60.39 seconds |
| Started | Jun 07 07:56:49 PM PDT 24 |
| Finished | Jun 07 07:58:55 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-eaa27da8-be29-462b-a8d0-c2e37e8d9bae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499776300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.499776300 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2854560028 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14103760000 ps |
| CPU time | 57.86 seconds |
| Started | Jun 07 07:56:39 PM PDT 24 |
| Finished | Jun 07 07:58:33 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-be08dc89-aee5-4a25-95aa-2d408e177fef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854560028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2854560028 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1547386878 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15341900000 ps |
| CPU time | 61.84 seconds |
| Started | Jun 07 07:56:40 PM PDT 24 |
| Finished | Jun 07 07:58:47 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-1b79f336-95dc-4214-8534-a7e305e5bbb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547386878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1547386878 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1780467368 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9177240000 ps |
| CPU time | 34.06 seconds |
| Started | Jun 07 07:56:38 PM PDT 24 |
| Finished | Jun 07 07:57:45 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-71fe4c0d-49fa-42f6-9453-89596f655a62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1780467368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1780467368 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2140795950 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12894760000 ps |
| CPU time | 50.2 seconds |
| Started | Jun 07 07:56:38 PM PDT 24 |
| Finished | Jun 07 07:58:15 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-694f2318-9505-47a1-8330-dbebe411ce86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140795950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2140795950 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2581246278 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11160000000 ps |
| CPU time | 44.59 seconds |
| Started | Jun 07 07:56:40 PM PDT 24 |
| Finished | Jun 07 07:58:08 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-7e18fa80-e406-47a2-ae59-0283a0ef2b7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581246278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2581246278 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |