| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/19.prim_present_test.635800674 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3997240554 |
| /workspace/coverage/default/1.prim_present_test.3160450097 |
| /workspace/coverage/default/10.prim_present_test.3235413906 |
| /workspace/coverage/default/11.prim_present_test.2160466362 |
| /workspace/coverage/default/12.prim_present_test.2263748280 |
| /workspace/coverage/default/13.prim_present_test.2914506098 |
| /workspace/coverage/default/14.prim_present_test.3193922079 |
| /workspace/coverage/default/15.prim_present_test.1934979170 |
| /workspace/coverage/default/16.prim_present_test.3109013089 |
| /workspace/coverage/default/17.prim_present_test.3448048386 |
| /workspace/coverage/default/18.prim_present_test.2447313801 |
| /workspace/coverage/default/2.prim_present_test.3408756271 |
| /workspace/coverage/default/20.prim_present_test.3645470405 |
| /workspace/coverage/default/21.prim_present_test.174205619 |
| /workspace/coverage/default/22.prim_present_test.1343343220 |
| /workspace/coverage/default/23.prim_present_test.402078409 |
| /workspace/coverage/default/24.prim_present_test.3648153793 |
| /workspace/coverage/default/25.prim_present_test.1226550347 |
| /workspace/coverage/default/26.prim_present_test.1981106980 |
| /workspace/coverage/default/27.prim_present_test.2967473277 |
| /workspace/coverage/default/28.prim_present_test.2046616730 |
| /workspace/coverage/default/29.prim_present_test.1142456492 |
| /workspace/coverage/default/3.prim_present_test.1132443523 |
| /workspace/coverage/default/30.prim_present_test.295089292 |
| /workspace/coverage/default/31.prim_present_test.1851522678 |
| /workspace/coverage/default/32.prim_present_test.2145868884 |
| /workspace/coverage/default/33.prim_present_test.1100937802 |
| /workspace/coverage/default/34.prim_present_test.3314487685 |
| /workspace/coverage/default/35.prim_present_test.3989088837 |
| /workspace/coverage/default/36.prim_present_test.573970073 |
| /workspace/coverage/default/37.prim_present_test.2713596242 |
| /workspace/coverage/default/38.prim_present_test.1114720606 |
| /workspace/coverage/default/39.prim_present_test.2918831985 |
| /workspace/coverage/default/4.prim_present_test.834055966 |
| /workspace/coverage/default/40.prim_present_test.2514934439 |
| /workspace/coverage/default/41.prim_present_test.253670790 |
| /workspace/coverage/default/42.prim_present_test.462704516 |
| /workspace/coverage/default/43.prim_present_test.4294195827 |
| /workspace/coverage/default/44.prim_present_test.2766486974 |
| /workspace/coverage/default/45.prim_present_test.877918708 |
| /workspace/coverage/default/46.prim_present_test.3619367844 |
| /workspace/coverage/default/47.prim_present_test.1673648737 |
| /workspace/coverage/default/48.prim_present_test.148705657 |
| /workspace/coverage/default/49.prim_present_test.1211300863 |
| /workspace/coverage/default/5.prim_present_test.680120604 |
| /workspace/coverage/default/6.prim_present_test.1774543732 |
| /workspace/coverage/default/7.prim_present_test.1714783195 |
| /workspace/coverage/default/8.prim_present_test.1974486024 |
| /workspace/coverage/default/9.prim_present_test.1606378773 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/37.prim_present_test.2713596242 | Jun 09 12:31:23 PM PDT 24 | Jun 09 12:32:34 PM PDT 24 | 13020000000 ps | ||
| T2 | /workspace/coverage/default/45.prim_present_test.877918708 | Jun 09 12:31:37 PM PDT 24 | Jun 09 12:32:24 PM PDT 24 | 7178980000 ps | ||
| T3 | /workspace/coverage/default/8.prim_present_test.1974486024 | Jun 09 12:31:35 PM PDT 24 | Jun 09 12:32:56 PM PDT 24 | 12883600000 ps | ||
| T4 | /workspace/coverage/default/5.prim_present_test.680120604 | Jun 09 12:31:26 PM PDT 24 | Jun 09 12:31:49 PM PDT 24 | 4305900000 ps | ||
| T5 | /workspace/coverage/default/19.prim_present_test.635800674 | Jun 09 12:31:21 PM PDT 24 | Jun 09 12:31:47 PM PDT 24 | 4367900000 ps | ||
| T6 | /workspace/coverage/default/21.prim_present_test.174205619 | Jun 09 12:31:33 PM PDT 24 | Jun 09 12:33:10 PM PDT 24 | 14899220000 ps | ||
| T7 | /workspace/coverage/default/41.prim_present_test.253670790 | Jun 09 12:31:34 PM PDT 24 | Jun 09 12:32:42 PM PDT 24 | 11055840000 ps | ||
| T8 | /workspace/coverage/default/7.prim_present_test.1714783195 | Jun 09 12:31:34 PM PDT 24 | Jun 09 12:32:53 PM PDT 24 | 11308800000 ps | ||
| T9 | /workspace/coverage/default/35.prim_present_test.3989088837 | Jun 09 12:31:35 PM PDT 24 | Jun 09 12:33:03 PM PDT 24 | 12706900000 ps | ||
| T10 | /workspace/coverage/default/4.prim_present_test.834055966 | Jun 09 12:31:33 PM PDT 24 | Jun 09 12:32:18 PM PDT 24 | 6606100000 ps | ||
| T11 | /workspace/coverage/default/14.prim_present_test.3193922079 | Jun 09 12:31:23 PM PDT 24 | Jun 09 12:32:25 PM PDT 24 | 8835000000 ps | ||
| T12 | /workspace/coverage/default/33.prim_present_test.1100937802 | Jun 09 12:31:29 PM PDT 24 | Jun 09 12:32:15 PM PDT 24 | 6957640000 ps | ||
| T13 | /workspace/coverage/default/22.prim_present_test.1343343220 | Jun 09 12:31:37 PM PDT 24 | Jun 09 12:32:48 PM PDT 24 | 10464360000 ps | ||
| T14 | /workspace/coverage/default/12.prim_present_test.2263748280 | Jun 09 12:31:29 PM PDT 24 | Jun 09 12:32:16 PM PDT 24 | 6620980000 ps | ||
| T15 | /workspace/coverage/default/23.prim_present_test.402078409 | Jun 09 12:31:26 PM PDT 24 | Jun 09 12:32:14 PM PDT 24 | 7857880000 ps | ||
| T16 | /workspace/coverage/default/30.prim_present_test.295089292 | Jun 09 12:31:35 PM PDT 24 | Jun 09 12:32:51 PM PDT 24 | 13117960000 ps | ||
| T17 | /workspace/coverage/default/25.prim_present_test.1226550347 | Jun 09 12:31:30 PM PDT 24 | Jun 09 12:32:45 PM PDT 24 | 10825200000 ps | ||
| T18 | /workspace/coverage/default/13.prim_present_test.2914506098 | Jun 09 12:31:31 PM PDT 24 | Jun 09 12:33:11 PM PDT 24 | 15041820000 ps | ||
| T19 | /workspace/coverage/default/24.prim_present_test.3648153793 | Jun 09 12:31:24 PM PDT 24 | Jun 09 12:32:02 PM PDT 24 | 5094540000 ps | ||
| T20 | /workspace/coverage/default/11.prim_present_test.2160466362 | Jun 09 12:31:24 PM PDT 24 | Jun 09 12:32:11 PM PDT 24 | 7307940000 ps | ||
| T21 | /workspace/coverage/default/42.prim_present_test.462704516 | Jun 09 12:31:33 PM PDT 24 | Jun 09 12:32:44 PM PDT 24 | 10027880000 ps | ||
| T22 | /workspace/coverage/default/17.prim_present_test.3448048386 | Jun 09 12:31:26 PM PDT 24 | Jun 09 12:31:53 PM PDT 24 | 3879960000 ps | ||
| T23 | /workspace/coverage/default/6.prim_present_test.1774543732 | Jun 09 12:31:35 PM PDT 24 | Jun 09 12:32:28 PM PDT 24 | 7898800000 ps | ||
| T24 | /workspace/coverage/default/0.prim_present_test.3997240554 | Jun 09 12:31:24 PM PDT 24 | Jun 09 12:32:08 PM PDT 24 | 6113820000 ps | ||
| T25 | /workspace/coverage/default/20.prim_present_test.3645470405 | Jun 09 12:31:32 PM PDT 24 | Jun 09 12:32:33 PM PDT 24 | 9600700000 ps | ||
| T26 | /workspace/coverage/default/39.prim_present_test.2918831985 | Jun 09 12:31:27 PM PDT 24 | Jun 09 12:32:42 PM PDT 24 | 9760040000 ps | ||
| T27 | /workspace/coverage/default/49.prim_present_test.1211300863 | Jun 09 12:31:34 PM PDT 24 | Jun 09 12:32:00 PM PDT 24 | 4117420000 ps | ||
| T28 | /workspace/coverage/default/3.prim_present_test.1132443523 | Jun 09 12:31:32 PM PDT 24 | Jun 09 12:32:29 PM PDT 24 | 8371860000 ps | ||
| T29 | /workspace/coverage/default/2.prim_present_test.3408756271 | Jun 09 12:31:23 PM PDT 24 | Jun 09 12:32:31 PM PDT 24 | 9734620000 ps | ||
| T30 | /workspace/coverage/default/34.prim_present_test.3314487685 | Jun 09 12:31:35 PM PDT 24 | Jun 09 12:33:12 PM PDT 24 | 15132960000 ps | ||
| T31 | /workspace/coverage/default/38.prim_present_test.1114720606 | Jun 09 12:31:36 PM PDT 24 | Jun 09 12:32:44 PM PDT 24 | 10650360000 ps | ||
| T32 | /workspace/coverage/default/1.prim_present_test.3160450097 | Jun 09 12:31:38 PM PDT 24 | Jun 09 12:33:01 PM PDT 24 | 11197820000 ps | ||
| T33 | /workspace/coverage/default/9.prim_present_test.1606378773 | Jun 09 12:31:23 PM PDT 24 | Jun 09 12:31:59 PM PDT 24 | 5190020000 ps | ||
| T34 | /workspace/coverage/default/47.prim_present_test.1673648737 | Jun 09 12:31:34 PM PDT 24 | Jun 09 12:32:52 PM PDT 24 | 12350400000 ps | ||
| T35 | /workspace/coverage/default/40.prim_present_test.2514934439 | Jun 09 12:31:24 PM PDT 24 | Jun 09 12:33:03 PM PDT 24 | 14909760000 ps | ||
| T36 | /workspace/coverage/default/18.prim_present_test.2447313801 | Jun 09 12:31:28 PM PDT 24 | Jun 09 12:31:55 PM PDT 24 | 3727440000 ps | ||
| T37 | /workspace/coverage/default/27.prim_present_test.2967473277 | Jun 09 12:31:24 PM PDT 24 | Jun 09 12:31:59 PM PDT 24 | 5248300000 ps | ||
| T38 | /workspace/coverage/default/29.prim_present_test.1142456492 | Jun 09 12:31:34 PM PDT 24 | Jun 09 12:32:44 PM PDT 24 | 11996380000 ps | ||
| T39 | /workspace/coverage/default/15.prim_present_test.1934979170 | Jun 09 12:31:23 PM PDT 24 | Jun 09 12:32:48 PM PDT 24 | 13589780000 ps | ||
| T40 | /workspace/coverage/default/16.prim_present_test.3109013089 | Jun 09 12:31:25 PM PDT 24 | Jun 09 12:32:28 PM PDT 24 | 9344020000 ps | ||
| T41 | /workspace/coverage/default/44.prim_present_test.2766486974 | Jun 09 12:31:26 PM PDT 24 | Jun 09 12:31:59 PM PDT 24 | 5159020000 ps | ||
| T42 | /workspace/coverage/default/10.prim_present_test.3235413906 | Jun 09 12:31:32 PM PDT 24 | Jun 09 12:32:37 PM PDT 24 | 9722220000 ps | ||
| T43 | /workspace/coverage/default/36.prim_present_test.573970073 | Jun 09 12:31:33 PM PDT 24 | Jun 09 12:32:21 PM PDT 24 | 7099000000 ps | ||
| T44 | /workspace/coverage/default/32.prim_present_test.2145868884 | Jun 09 12:31:30 PM PDT 24 | Jun 09 12:32:20 PM PDT 24 | 6955160000 ps | ||
| T45 | /workspace/coverage/default/48.prim_present_test.148705657 | Jun 09 12:31:33 PM PDT 24 | Jun 09 12:32:22 PM PDT 24 | 8120140000 ps | ||
| T46 | /workspace/coverage/default/26.prim_present_test.1981106980 | Jun 09 12:31:20 PM PDT 24 | Jun 09 12:32:45 PM PDT 24 | 11598340000 ps | ||
| T47 | /workspace/coverage/default/28.prim_present_test.2046616730 | Jun 09 12:31:30 PM PDT 24 | Jun 09 12:32:32 PM PDT 24 | 9127020000 ps | ||
| T48 | /workspace/coverage/default/43.prim_present_test.4294195827 | Jun 09 12:31:32 PM PDT 24 | Jun 09 12:33:05 PM PDT 24 | 14651220000 ps | ||
| T49 | /workspace/coverage/default/46.prim_present_test.3619367844 | Jun 09 12:31:31 PM PDT 24 | Jun 09 12:32:12 PM PDT 24 | 6594320000 ps | ||
| T50 | /workspace/coverage/default/31.prim_present_test.1851522678 | Jun 09 12:31:26 PM PDT 24 | Jun 09 12:33:05 PM PDT 24 | 14484440000 ps |
| Test location | /workspace/coverage/default/19.prim_present_test.635800674 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4367900000 ps |
| CPU time | 14.14 seconds |
| Started | Jun 09 12:31:21 PM PDT 24 |
| Finished | Jun 09 12:31:47 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-7b9cf1d8-1c4d-4309-a3d8-4cd7682c6bf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635800674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.635800674 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3997240554 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6113820000 ps |
| CPU time | 23.03 seconds |
| Started | Jun 09 12:31:24 PM PDT 24 |
| Finished | Jun 09 12:32:08 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ddddd223-04dc-4e75-a353-d3afd99a649c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997240554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3997240554 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3160450097 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 11197820000 ps |
| CPU time | 43.01 seconds |
| Started | Jun 09 12:31:38 PM PDT 24 |
| Finished | Jun 09 12:33:01 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-08d8ac79-45db-4522-b351-a0cdbaefc49d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160450097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3160450097 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3235413906 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 9722220000 ps |
| CPU time | 34.41 seconds |
| Started | Jun 09 12:31:32 PM PDT 24 |
| Finished | Jun 09 12:32:37 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-358b5cd6-3909-4f45-9db9-005e3155b1e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235413906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3235413906 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2160466362 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7307940000 ps |
| CPU time | 25 seconds |
| Started | Jun 09 12:31:24 PM PDT 24 |
| Finished | Jun 09 12:32:11 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-20c6c7a0-d62d-4aa9-92ee-ba62019cf961 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160466362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2160466362 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2263748280 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6620980000 ps |
| CPU time | 24.62 seconds |
| Started | Jun 09 12:31:29 PM PDT 24 |
| Finished | Jun 09 12:32:16 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-3ceb1f31-0de7-41ae-8c65-9a5fed5d9c1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263748280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2263748280 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2914506098 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15041820000 ps |
| CPU time | 53.31 seconds |
| Started | Jun 09 12:31:31 PM PDT 24 |
| Finished | Jun 09 12:33:11 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-ec21f7ca-817d-4723-aa22-7330a5805a07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914506098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2914506098 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3193922079 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8835000000 ps |
| CPU time | 32.31 seconds |
| Started | Jun 09 12:31:23 PM PDT 24 |
| Finished | Jun 09 12:32:25 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-52ad6ab4-4619-45e4-b85d-14b4717f4804 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193922079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3193922079 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1934979170 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13589780000 ps |
| CPU time | 45.81 seconds |
| Started | Jun 09 12:31:23 PM PDT 24 |
| Finished | Jun 09 12:32:48 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-e8771369-2f1f-4bba-8056-bfd3ee238cc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934979170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1934979170 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3109013089 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9344020000 ps |
| CPU time | 32.82 seconds |
| Started | Jun 09 12:31:25 PM PDT 24 |
| Finished | Jun 09 12:32:28 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-3e90b242-053e-46cd-b44a-37c61b86504f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109013089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3109013089 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3448048386 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3879960000 ps |
| CPU time | 14.51 seconds |
| Started | Jun 09 12:31:26 PM PDT 24 |
| Finished | Jun 09 12:31:53 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-33a30f39-1138-4f42-8024-381536500d0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448048386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3448048386 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2447313801 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3727440000 ps |
| CPU time | 14.12 seconds |
| Started | Jun 09 12:31:28 PM PDT 24 |
| Finished | Jun 09 12:31:55 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-68325a9e-8ec1-42e3-8681-e3980116a220 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447313801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2447313801 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3408756271 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9734620000 ps |
| CPU time | 36.02 seconds |
| Started | Jun 09 12:31:23 PM PDT 24 |
| Finished | Jun 09 12:32:31 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-a5beb8cc-0c49-4dfd-bb8b-e8eb185f9471 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408756271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3408756271 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3645470405 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9600700000 ps |
| CPU time | 32.82 seconds |
| Started | Jun 09 12:31:32 PM PDT 24 |
| Finished | Jun 09 12:32:33 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-f577cc00-034a-42e2-89a3-4e54c9648a01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3645470405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3645470405 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.174205619 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14899220000 ps |
| CPU time | 51.88 seconds |
| Started | Jun 09 12:31:33 PM PDT 24 |
| Finished | Jun 09 12:33:10 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-6f04622c-7203-4035-b37d-0502ac49dbff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=174205619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.174205619 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1343343220 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10464360000 ps |
| CPU time | 36.66 seconds |
| Started | Jun 09 12:31:37 PM PDT 24 |
| Finished | Jun 09 12:32:48 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-12ed21ad-0b92-454a-ae6a-ade2f9ebc60d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343343220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1343343220 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.402078409 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7857880000 ps |
| CPU time | 25.83 seconds |
| Started | Jun 09 12:31:26 PM PDT 24 |
| Finished | Jun 09 12:32:14 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-c416fef7-494a-4b2a-ad44-2ff9ed768ec3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402078409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.402078409 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3648153793 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5094540000 ps |
| CPU time | 19.38 seconds |
| Started | Jun 09 12:31:24 PM PDT 24 |
| Finished | Jun 09 12:32:02 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-163e77d5-9e5f-499d-a37b-f5dfa44e5f25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648153793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3648153793 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1226550347 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10825200000 ps |
| CPU time | 39.57 seconds |
| Started | Jun 09 12:31:30 PM PDT 24 |
| Finished | Jun 09 12:32:45 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-0851ddb2-6490-46eb-a230-0535941f3921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226550347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1226550347 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1981106980 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11598340000 ps |
| CPU time | 44.17 seconds |
| Started | Jun 09 12:31:20 PM PDT 24 |
| Finished | Jun 09 12:32:45 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-12fb5968-9f60-4cff-9d4c-087dd3719930 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981106980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1981106980 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2967473277 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5248300000 ps |
| CPU time | 18.76 seconds |
| Started | Jun 09 12:31:24 PM PDT 24 |
| Finished | Jun 09 12:31:59 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-9e819aa6-b969-495c-91f9-979d1d876c7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967473277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2967473277 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2046616730 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9127020000 ps |
| CPU time | 32.87 seconds |
| Started | Jun 09 12:31:30 PM PDT 24 |
| Finished | Jun 09 12:32:32 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-d2355343-9f08-4b35-94a1-3c73e54ec78a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046616730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2046616730 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1142456492 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11996380000 ps |
| CPU time | 38.45 seconds |
| Started | Jun 09 12:31:34 PM PDT 24 |
| Finished | Jun 09 12:32:44 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-6cc3d763-3e0e-430f-9022-8df5778dc8e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142456492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1142456492 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1132443523 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8371860000 ps |
| CPU time | 30.39 seconds |
| Started | Jun 09 12:31:32 PM PDT 24 |
| Finished | Jun 09 12:32:29 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-625435dc-55d0-45f4-b981-4ffac6e56fc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132443523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1132443523 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.295089292 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13117960000 ps |
| CPU time | 40.89 seconds |
| Started | Jun 09 12:31:35 PM PDT 24 |
| Finished | Jun 09 12:32:51 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-dab7d269-57b0-42e5-a2d9-0d9a8fd13280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295089292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.295089292 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1851522678 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14484440000 ps |
| CPU time | 52.64 seconds |
| Started | Jun 09 12:31:26 PM PDT 24 |
| Finished | Jun 09 12:33:05 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-f328a151-f2b5-4def-b691-cca5cec5361b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851522678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1851522678 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2145868884 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6955160000 ps |
| CPU time | 26.04 seconds |
| Started | Jun 09 12:31:30 PM PDT 24 |
| Finished | Jun 09 12:32:20 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-170bada1-fb8f-4cf5-9079-27468bed349c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145868884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2145868884 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1100937802 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6957640000 ps |
| CPU time | 24.85 seconds |
| Started | Jun 09 12:31:29 PM PDT 24 |
| Finished | Jun 09 12:32:15 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-edd77125-f823-4657-83d0-d1f9da2b4637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100937802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1100937802 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3314487685 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 15132960000 ps |
| CPU time | 51.32 seconds |
| Started | Jun 09 12:31:35 PM PDT 24 |
| Finished | Jun 09 12:33:12 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-e8921fd5-f61e-4001-bd8f-02cdcf9c5456 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314487685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3314487685 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3989088837 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12706900000 ps |
| CPU time | 45.96 seconds |
| Started | Jun 09 12:31:35 PM PDT 24 |
| Finished | Jun 09 12:33:03 PM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-4c6f208b-def5-4bce-9ba4-18da3736fee2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989088837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3989088837 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.573970073 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7099000000 ps |
| CPU time | 26.05 seconds |
| Started | Jun 09 12:31:33 PM PDT 24 |
| Finished | Jun 09 12:32:21 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-76a98f69-b6f4-4fb9-93ed-199d14f61155 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573970073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.573970073 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2713596242 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13020000000 ps |
| CPU time | 39.63 seconds |
| Started | Jun 09 12:31:23 PM PDT 24 |
| Finished | Jun 09 12:32:34 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-99130150-006b-4f64-a506-ec1c522e3277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713596242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2713596242 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1114720606 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10650360000 ps |
| CPU time | 35.79 seconds |
| Started | Jun 09 12:31:36 PM PDT 24 |
| Finished | Jun 09 12:32:44 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-876c0777-8c23-4992-b5d1-9a146f1a5c7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114720606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1114720606 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2918831985 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9760040000 ps |
| CPU time | 39.11 seconds |
| Started | Jun 09 12:31:27 PM PDT 24 |
| Finished | Jun 09 12:32:42 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-49449df7-6d7b-4ea4-b903-2f67830bc0b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918831985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2918831985 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.834055966 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6606100000 ps |
| CPU time | 23.7 seconds |
| Started | Jun 09 12:31:33 PM PDT 24 |
| Finished | Jun 09 12:32:18 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-3cf4f4b2-15e7-4491-b3f1-a07a93871e27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834055966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.834055966 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2514934439 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14909760000 ps |
| CPU time | 52.06 seconds |
| Started | Jun 09 12:31:24 PM PDT 24 |
| Finished | Jun 09 12:33:03 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-1f4f8203-4c3d-470d-a1e7-8d703ce53a30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514934439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2514934439 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.253670790 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11055840000 ps |
| CPU time | 36.62 seconds |
| Started | Jun 09 12:31:34 PM PDT 24 |
| Finished | Jun 09 12:32:42 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-d88e9237-ebe3-472f-9887-1c392abeaca2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253670790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.253670790 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.462704516 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10027880000 ps |
| CPU time | 37 seconds |
| Started | Jun 09 12:31:33 PM PDT 24 |
| Finished | Jun 09 12:32:44 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-3df6da15-5577-4494-87d2-bbbc8a21b507 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462704516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.462704516 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4294195827 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14651220000 ps |
| CPU time | 49.47 seconds |
| Started | Jun 09 12:31:32 PM PDT 24 |
| Finished | Jun 09 12:33:05 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-1813539f-5456-456f-b4b9-795d04e7c295 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294195827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4294195827 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2766486974 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5159020000 ps |
| CPU time | 17.66 seconds |
| Started | Jun 09 12:31:26 PM PDT 24 |
| Finished | Jun 09 12:31:59 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-44c0de90-8856-4a58-a0de-b8ecfc266c79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766486974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2766486974 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.877918708 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7178980000 ps |
| CPU time | 24.92 seconds |
| Started | Jun 09 12:31:37 PM PDT 24 |
| Finished | Jun 09 12:32:24 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-bdce7c4e-edb4-4506-aa5d-e6a9d7ce0e9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877918708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.877918708 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3619367844 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6594320000 ps |
| CPU time | 21.23 seconds |
| Started | Jun 09 12:31:31 PM PDT 24 |
| Finished | Jun 09 12:32:12 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-6ab6d8c5-e9da-4669-9867-e5f1bc4145f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619367844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3619367844 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1673648737 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12350400000 ps |
| CPU time | 41.14 seconds |
| Started | Jun 09 12:31:34 PM PDT 24 |
| Finished | Jun 09 12:32:52 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-022e9245-2960-452a-88fe-e7f0867963bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673648737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1673648737 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.148705657 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8120140000 ps |
| CPU time | 26.38 seconds |
| Started | Jun 09 12:31:33 PM PDT 24 |
| Finished | Jun 09 12:32:22 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-1a177a21-848c-423b-9b12-a94aef4468b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148705657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.148705657 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1211300863 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4117420000 ps |
| CPU time | 13.8 seconds |
| Started | Jun 09 12:31:34 PM PDT 24 |
| Finished | Jun 09 12:32:00 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-de1273f1-0d23-45ee-95ff-cf4a7d6b1d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1211300863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1211300863 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.680120604 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4305900000 ps |
| CPU time | 12.67 seconds |
| Started | Jun 09 12:31:26 PM PDT 24 |
| Finished | Jun 09 12:31:49 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-5259a44e-6d63-42fc-971d-6be8448e3788 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680120604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.680120604 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1774543732 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7898800000 ps |
| CPU time | 27.83 seconds |
| Started | Jun 09 12:31:35 PM PDT 24 |
| Finished | Jun 09 12:32:28 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-480f7f07-b69d-4ef4-916d-71e87032e76a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774543732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1774543732 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1714783195 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11308800000 ps |
| CPU time | 41.41 seconds |
| Started | Jun 09 12:31:34 PM PDT 24 |
| Finished | Jun 09 12:32:53 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-45a4725c-2dce-48cd-a104-659e100296a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714783195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1714783195 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1974486024 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12883600000 ps |
| CPU time | 43.53 seconds |
| Started | Jun 09 12:31:35 PM PDT 24 |
| Finished | Jun 09 12:32:56 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-639592a7-f65a-4fcb-bdcc-61b692b54a66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974486024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1974486024 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1606378773 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5190020000 ps |
| CPU time | 19.84 seconds |
| Started | Jun 09 12:31:23 PM PDT 24 |
| Finished | Jun 09 12:31:59 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-74f4b4f3-4f46-4d04-a22e-b87f3f223820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606378773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1606378773 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |