| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/16.prim_present_test.3031376171 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.799909674 |
| /workspace/coverage/default/1.prim_present_test.3644107605 |
| /workspace/coverage/default/10.prim_present_test.1584396840 |
| /workspace/coverage/default/11.prim_present_test.1501263624 |
| /workspace/coverage/default/12.prim_present_test.3317277944 |
| /workspace/coverage/default/13.prim_present_test.99754459 |
| /workspace/coverage/default/14.prim_present_test.1016104047 |
| /workspace/coverage/default/15.prim_present_test.1813854482 |
| /workspace/coverage/default/17.prim_present_test.2478940689 |
| /workspace/coverage/default/18.prim_present_test.422042009 |
| /workspace/coverage/default/19.prim_present_test.13548704 |
| /workspace/coverage/default/2.prim_present_test.973726550 |
| /workspace/coverage/default/20.prim_present_test.3522933290 |
| /workspace/coverage/default/21.prim_present_test.4152855143 |
| /workspace/coverage/default/22.prim_present_test.1202357634 |
| /workspace/coverage/default/23.prim_present_test.3207065340 |
| /workspace/coverage/default/24.prim_present_test.1247805547 |
| /workspace/coverage/default/25.prim_present_test.1628507323 |
| /workspace/coverage/default/26.prim_present_test.3074287191 |
| /workspace/coverage/default/27.prim_present_test.3361331121 |
| /workspace/coverage/default/28.prim_present_test.2532183492 |
| /workspace/coverage/default/29.prim_present_test.1814760325 |
| /workspace/coverage/default/3.prim_present_test.2785941362 |
| /workspace/coverage/default/30.prim_present_test.2472032728 |
| /workspace/coverage/default/31.prim_present_test.1177058851 |
| /workspace/coverage/default/32.prim_present_test.491102174 |
| /workspace/coverage/default/33.prim_present_test.4259220324 |
| /workspace/coverage/default/34.prim_present_test.3787963346 |
| /workspace/coverage/default/35.prim_present_test.98379491 |
| /workspace/coverage/default/36.prim_present_test.4057376162 |
| /workspace/coverage/default/37.prim_present_test.2777505323 |
| /workspace/coverage/default/38.prim_present_test.837644899 |
| /workspace/coverage/default/39.prim_present_test.3622414551 |
| /workspace/coverage/default/4.prim_present_test.742536769 |
| /workspace/coverage/default/40.prim_present_test.1805219410 |
| /workspace/coverage/default/41.prim_present_test.2397649325 |
| /workspace/coverage/default/42.prim_present_test.2411338722 |
| /workspace/coverage/default/43.prim_present_test.919243351 |
| /workspace/coverage/default/44.prim_present_test.4050930502 |
| /workspace/coverage/default/45.prim_present_test.2827403445 |
| /workspace/coverage/default/46.prim_present_test.2586482687 |
| /workspace/coverage/default/47.prim_present_test.3917281353 |
| /workspace/coverage/default/48.prim_present_test.3232185939 |
| /workspace/coverage/default/49.prim_present_test.1563704417 |
| /workspace/coverage/default/5.prim_present_test.4216108334 |
| /workspace/coverage/default/6.prim_present_test.3551319630 |
| /workspace/coverage/default/7.prim_present_test.3400691800 |
| /workspace/coverage/default/8.prim_present_test.1036486292 |
| /workspace/coverage/default/9.prim_present_test.125422931 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/41.prim_present_test.2397649325 | Jun 10 04:57:59 PM PDT 24 | Jun 10 04:58:59 PM PDT 24 | 7695440000 ps | ||
| T2 | /workspace/coverage/default/18.prim_present_test.422042009 | Jun 10 04:57:58 PM PDT 24 | Jun 10 04:58:46 PM PDT 24 | 5831720000 ps | ||
| T3 | /workspace/coverage/default/35.prim_present_test.98379491 | Jun 10 04:58:02 PM PDT 24 | Jun 10 05:00:03 PM PDT 24 | 14997180000 ps | ||
| T4 | /workspace/coverage/default/43.prim_present_test.919243351 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:58:44 PM PDT 24 | 6195040000 ps | ||
| T5 | /workspace/coverage/default/20.prim_present_test.3522933290 | Jun 10 04:58:15 PM PDT 24 | Jun 10 04:59:43 PM PDT 24 | 11177980000 ps | ||
| T6 | /workspace/coverage/default/5.prim_present_test.4216108334 | Jun 10 04:57:59 PM PDT 24 | Jun 10 04:59:27 PM PDT 24 | 11361500000 ps | ||
| T7 | /workspace/coverage/default/48.prim_present_test.3232185939 | Jun 10 04:58:11 PM PDT 24 | Jun 10 04:59:03 PM PDT 24 | 6214260000 ps | ||
| T8 | /workspace/coverage/default/46.prim_present_test.2586482687 | Jun 10 04:57:52 PM PDT 24 | Jun 10 04:58:31 PM PDT 24 | 5343160000 ps | ||
| T9 | /workspace/coverage/default/31.prim_present_test.1177058851 | Jun 10 04:57:55 PM PDT 24 | Jun 10 04:59:30 PM PDT 24 | 13741060000 ps | ||
| T10 | /workspace/coverage/default/16.prim_present_test.3031376171 | Jun 10 04:58:05 PM PDT 24 | Jun 10 04:58:50 PM PDT 24 | 5761040000 ps | ||
| T11 | /workspace/coverage/default/27.prim_present_test.3361331121 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:54 PM PDT 24 | 13970460000 ps | ||
| T12 | /workspace/coverage/default/33.prim_present_test.4259220324 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:57 PM PDT 24 | 14287900000 ps | ||
| T13 | /workspace/coverage/default/38.prim_present_test.837644899 | Jun 10 04:57:56 PM PDT 24 | Jun 10 04:58:28 PM PDT 24 | 5307820000 ps | ||
| T14 | /workspace/coverage/default/24.prim_present_test.1247805547 | Jun 10 04:57:55 PM PDT 24 | Jun 10 04:59:21 PM PDT 24 | 9972700000 ps | ||
| T15 | /workspace/coverage/default/13.prim_present_test.99754459 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:30 PM PDT 24 | 11339180000 ps | ||
| T16 | /workspace/coverage/default/34.prim_present_test.3787963346 | Jun 10 04:57:56 PM PDT 24 | Jun 10 04:59:31 PM PDT 24 | 12539500000 ps | ||
| T17 | /workspace/coverage/default/42.prim_present_test.2411338722 | Jun 10 04:57:59 PM PDT 24 | Jun 10 04:59:35 PM PDT 24 | 12910260000 ps | ||
| T18 | /workspace/coverage/default/30.prim_present_test.2472032728 | Jun 10 04:57:56 PM PDT 24 | Jun 10 04:59:41 PM PDT 24 | 12709380000 ps | ||
| T19 | /workspace/coverage/default/17.prim_present_test.2478940689 | Jun 10 04:58:05 PM PDT 24 | Jun 10 04:59:30 PM PDT 24 | 10528840000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.2777505323 | Jun 10 04:58:08 PM PDT 24 | Jun 10 04:59:31 PM PDT 24 | 10556740000 ps | ||
| T21 | /workspace/coverage/default/9.prim_present_test.125422931 | Jun 10 04:57:54 PM PDT 24 | Jun 10 04:59:26 PM PDT 24 | 13418660000 ps | ||
| T22 | /workspace/coverage/default/36.prim_present_test.4057376162 | Jun 10 04:57:52 PM PDT 24 | Jun 10 04:59:45 PM PDT 24 | 15191240000 ps | ||
| T23 | /workspace/coverage/default/10.prim_present_test.1584396840 | Jun 10 04:57:52 PM PDT 24 | Jun 10 04:58:34 PM PDT 24 | 5204900000 ps | ||
| T24 | /workspace/coverage/default/21.prim_present_test.4152855143 | Jun 10 04:58:10 PM PDT 24 | Jun 10 04:59:57 PM PDT 24 | 13037360000 ps | ||
| T25 | /workspace/coverage/default/15.prim_present_test.1813854482 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:27 PM PDT 24 | 10959120000 ps | ||
| T26 | /workspace/coverage/default/49.prim_present_test.1563704417 | Jun 10 04:57:57 PM PDT 24 | Jun 10 04:59:17 PM PDT 24 | 10499080000 ps | ||
| T27 | /workspace/coverage/default/26.prim_present_test.3074287191 | Jun 10 04:57:53 PM PDT 24 | Jun 10 04:58:43 PM PDT 24 | 6591840000 ps | ||
| T28 | /workspace/coverage/default/28.prim_present_test.2532183492 | Jun 10 04:57:56 PM PDT 24 | Jun 10 04:58:47 PM PDT 24 | 5989200000 ps | ||
| T29 | /workspace/coverage/default/45.prim_present_test.2827403445 | Jun 10 04:57:57 PM PDT 24 | Jun 10 04:59:29 PM PDT 24 | 13776400000 ps | ||
| T30 | /workspace/coverage/default/3.prim_present_test.2785941362 | Jun 10 04:57:52 PM PDT 24 | Jun 10 04:58:58 PM PDT 24 | 9350220000 ps | ||
| T31 | /workspace/coverage/default/22.prim_present_test.1202357634 | Jun 10 04:57:49 PM PDT 24 | Jun 10 04:58:48 PM PDT 24 | 9270240000 ps | ||
| T32 | /workspace/coverage/default/4.prim_present_test.742536769 | Jun 10 04:58:04 PM PDT 24 | Jun 10 04:59:17 PM PDT 24 | 9419040000 ps | ||
| T33 | /workspace/coverage/default/0.prim_present_test.799909674 | Jun 10 04:57:53 PM PDT 24 | Jun 10 04:58:27 PM PDT 24 | 4482600000 ps | ||
| T34 | /workspace/coverage/default/25.prim_present_test.1628507323 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:32 PM PDT 24 | 10907660000 ps | ||
| T35 | /workspace/coverage/default/29.prim_present_test.1814760325 | Jun 10 04:57:56 PM PDT 24 | Jun 10 04:58:52 PM PDT 24 | 6570760000 ps | ||
| T36 | /workspace/coverage/default/32.prim_present_test.491102174 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:07 PM PDT 24 | 7957700000 ps | ||
| T37 | /workspace/coverage/default/23.prim_present_test.3207065340 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:26 PM PDT 24 | 10514580000 ps | ||
| T38 | /workspace/coverage/default/1.prim_present_test.3644107605 | Jun 10 04:57:50 PM PDT 24 | Jun 10 04:58:54 PM PDT 24 | 9454380000 ps | ||
| T39 | /workspace/coverage/default/44.prim_present_test.4050930502 | Jun 10 04:58:02 PM PDT 24 | Jun 10 04:58:37 PM PDT 24 | 5386560000 ps | ||
| T40 | /workspace/coverage/default/2.prim_present_test.973726550 | Jun 10 04:57:53 PM PDT 24 | Jun 10 04:59:39 PM PDT 24 | 15345620000 ps | ||
| T41 | /workspace/coverage/default/7.prim_present_test.3400691800 | Jun 10 04:58:04 PM PDT 24 | Jun 10 04:59:01 PM PDT 24 | 7355060000 ps | ||
| T42 | /workspace/coverage/default/8.prim_present_test.1036486292 | Jun 10 04:57:55 PM PDT 24 | Jun 10 04:59:20 PM PDT 24 | 13375880000 ps | ||
| T43 | /workspace/coverage/default/11.prim_present_test.1501263624 | Jun 10 04:57:53 PM PDT 24 | Jun 10 04:59:11 PM PDT 24 | 11461320000 ps | ||
| T44 | /workspace/coverage/default/12.prim_present_test.3317277944 | Jun 10 04:57:56 PM PDT 24 | Jun 10 04:59:10 PM PDT 24 | 8638460000 ps | ||
| T45 | /workspace/coverage/default/6.prim_present_test.3551319630 | Jun 10 04:58:06 PM PDT 24 | Jun 10 04:59:21 PM PDT 24 | 9058200000 ps | ||
| T46 | /workspace/coverage/default/19.prim_present_test.13548704 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:47 PM PDT 24 | 12967300000 ps | ||
| T47 | /workspace/coverage/default/47.prim_present_test.3917281353 | Jun 10 04:58:02 PM PDT 24 | Jun 10 04:58:49 PM PDT 24 | 6351900000 ps | ||
| T48 | /workspace/coverage/default/14.prim_present_test.1016104047 | Jun 10 04:58:00 PM PDT 24 | Jun 10 04:59:05 PM PDT 24 | 8095960000 ps | ||
| T49 | /workspace/coverage/default/39.prim_present_test.3622414551 | Jun 10 04:58:07 PM PDT 24 | Jun 10 04:59:50 PM PDT 24 | 13070220000 ps | ||
| T50 | /workspace/coverage/default/40.prim_present_test.1805219410 | Jun 10 04:58:05 PM PDT 24 | Jun 10 04:59:01 PM PDT 24 | 8747580000 ps |
| Test location | /workspace/coverage/default/16.prim_present_test.3031376171 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5761040000 ps |
| CPU time | 22.4 seconds |
| Started | Jun 10 04:58:05 PM PDT 24 |
| Finished | Jun 10 04:58:50 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-3205f8bf-a8e1-4930-b262-fc9a9db8f6d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031376171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3031376171 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.799909674 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4482600000 ps |
| CPU time | 17.08 seconds |
| Started | Jun 10 04:57:53 PM PDT 24 |
| Finished | Jun 10 04:58:27 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-9bb26535-6890-4059-90e1-2ca1318952e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799909674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.799909674 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3644107605 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9454380000 ps |
| CPU time | 33.74 seconds |
| Started | Jun 10 04:57:50 PM PDT 24 |
| Finished | Jun 10 04:58:54 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-35290f97-f314-4999-914c-b00d731dee34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644107605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3644107605 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1584396840 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5204900000 ps |
| CPU time | 21.38 seconds |
| Started | Jun 10 04:57:52 PM PDT 24 |
| Finished | Jun 10 04:58:34 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-f7a2e846-d782-488d-bd56-1693f54e76fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584396840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1584396840 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1501263624 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11461320000 ps |
| CPU time | 40.31 seconds |
| Started | Jun 10 04:57:53 PM PDT 24 |
| Finished | Jun 10 04:59:11 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-1ddd537a-5678-4093-a03e-53ac733b4df8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1501263624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1501263624 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3317277944 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8638460000 ps |
| CPU time | 36.81 seconds |
| Started | Jun 10 04:57:56 PM PDT 24 |
| Finished | Jun 10 04:59:10 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-7cebd125-141b-40cf-870d-c415451f45f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317277944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3317277944 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.99754459 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11339180000 ps |
| CPU time | 45.46 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:30 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-153bf906-342c-4af9-9bbf-cba0e93d701c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99754459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.99754459 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1016104047 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8095960000 ps |
| CPU time | 32.49 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:05 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-42ad01d0-c1c0-4c14-978c-1403259d2bfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1016104047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1016104047 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1813854482 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10959120000 ps |
| CPU time | 43.98 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:27 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-63fd778b-378b-4f0f-ae83-c9e299872256 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813854482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1813854482 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2478940689 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10528840000 ps |
| CPU time | 42.63 seconds |
| Started | Jun 10 04:58:05 PM PDT 24 |
| Finished | Jun 10 04:59:30 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-ea734b4f-c63a-4311-8d10-2bac552bb473 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478940689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2478940689 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.422042009 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5831720000 ps |
| CPU time | 23.85 seconds |
| Started | Jun 10 04:57:58 PM PDT 24 |
| Finished | Jun 10 04:58:46 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-eb3d8238-6285-499f-bdff-3ada0ab36c4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422042009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.422042009 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.13548704 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12967300000 ps |
| CPU time | 52.61 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:47 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-65c4c832-748c-47c9-af8c-c09671259763 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13548704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.13548704 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.973726550 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15345620000 ps |
| CPU time | 55.75 seconds |
| Started | Jun 10 04:57:53 PM PDT 24 |
| Finished | Jun 10 04:59:39 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-e8c2efca-7b48-4f41-a4f1-dd7ac41992bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973726550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.973726550 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3522933290 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11177980000 ps |
| CPU time | 44.57 seconds |
| Started | Jun 10 04:58:15 PM PDT 24 |
| Finished | Jun 10 04:59:43 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-a0499cf2-7557-41a0-9f75-e833e92795b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522933290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3522933290 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4152855143 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 13037360000 ps |
| CPU time | 54.74 seconds |
| Started | Jun 10 04:58:10 PM PDT 24 |
| Finished | Jun 10 04:59:57 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-0aed303b-3af5-4f14-811f-3966d174036f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4152855143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4152855143 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1202357634 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9270240000 ps |
| CPU time | 31.82 seconds |
| Started | Jun 10 04:57:49 PM PDT 24 |
| Finished | Jun 10 04:58:48 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-275718b5-40b2-44ee-90a0-4b3cdef9174f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202357634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1202357634 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3207065340 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10514580000 ps |
| CPU time | 43.41 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:26 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-08c94442-6509-4f86-bf76-df33295cdc3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207065340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3207065340 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1247805547 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9972700000 ps |
| CPU time | 43.27 seconds |
| Started | Jun 10 04:57:55 PM PDT 24 |
| Finished | Jun 10 04:59:21 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-6b4855b0-e799-48ab-b171-0825a2b4bd66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1247805547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1247805547 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1628507323 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10907660000 ps |
| CPU time | 44.69 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:32 PM PDT 24 |
| Peak memory | 144356 kb |
| Host | smart-b3d9ac81-c4eb-4594-9722-35d3494e51c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628507323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1628507323 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3074287191 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6591840000 ps |
| CPU time | 25.35 seconds |
| Started | Jun 10 04:57:53 PM PDT 24 |
| Finished | Jun 10 04:58:43 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-8b69aca7-eed2-45c0-8f7d-c912365076e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074287191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3074287191 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3361331121 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13970460000 ps |
| CPU time | 55.83 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:54 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-77cf9eea-43d1-435d-b826-2542d308125c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361331121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3361331121 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2532183492 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5989200000 ps |
| CPU time | 25.91 seconds |
| Started | Jun 10 04:57:56 PM PDT 24 |
| Finished | Jun 10 04:58:47 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-568b9994-7ac3-46f9-870f-05a0950fa2d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532183492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2532183492 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1814760325 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6570760000 ps |
| CPU time | 28.74 seconds |
| Started | Jun 10 04:57:56 PM PDT 24 |
| Finished | Jun 10 04:58:52 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-d79c3480-ee9b-4089-8394-cc2f6d273698 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814760325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1814760325 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2785941362 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9350220000 ps |
| CPU time | 34.97 seconds |
| Started | Jun 10 04:57:52 PM PDT 24 |
| Finished | Jun 10 04:58:58 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-cd77c4d8-bce1-4d28-b9ed-825fd3efa2ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785941362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2785941362 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2472032728 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12709380000 ps |
| CPU time | 52.26 seconds |
| Started | Jun 10 04:57:56 PM PDT 24 |
| Finished | Jun 10 04:59:41 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-b3a5c7b1-a6d8-4e36-9162-42ac49049c5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2472032728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2472032728 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1177058851 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13741060000 ps |
| CPU time | 50.09 seconds |
| Started | Jun 10 04:57:55 PM PDT 24 |
| Finished | Jun 10 04:59:30 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-e121eee8-1561-4d0f-8849-4e6362734dc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177058851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1177058851 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.491102174 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7957700000 ps |
| CPU time | 32.78 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:07 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-9854e2dc-00fa-4d7a-9cc4-0ae5a3453dc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491102174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.491102174 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.4259220324 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14287900000 ps |
| CPU time | 57.16 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:59:57 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-4af55434-41b2-420f-ba28-39d98a93c53b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259220324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.4259220324 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3787963346 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12539500000 ps |
| CPU time | 49.52 seconds |
| Started | Jun 10 04:57:56 PM PDT 24 |
| Finished | Jun 10 04:59:31 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-c9733334-4742-4f56-8e78-1ee7c32c530c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787963346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3787963346 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.98379491 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 14997180000 ps |
| CPU time | 60.86 seconds |
| Started | Jun 10 04:58:02 PM PDT 24 |
| Finished | Jun 10 05:00:03 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-1f0e0e11-3e56-4a19-ad41-8525f371ab08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98379491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.98379491 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4057376162 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 15191240000 ps |
| CPU time | 58 seconds |
| Started | Jun 10 04:57:52 PM PDT 24 |
| Finished | Jun 10 04:59:45 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-29ccea20-e375-487c-a573-7eb188897002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057376162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4057376162 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2777505323 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10556740000 ps |
| CPU time | 42.3 seconds |
| Started | Jun 10 04:58:08 PM PDT 24 |
| Finished | Jun 10 04:59:31 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-1f457f45-df15-4eb0-9039-286b567f2a0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777505323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2777505323 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.837644899 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5307820000 ps |
| CPU time | 16.6 seconds |
| Started | Jun 10 04:57:56 PM PDT 24 |
| Finished | Jun 10 04:58:28 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-c95560d3-d58d-4e37-b6bc-34123a2ec8de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837644899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.837644899 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3622414551 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13070220000 ps |
| CPU time | 53.92 seconds |
| Started | Jun 10 04:58:07 PM PDT 24 |
| Finished | Jun 10 04:59:50 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-e6b8d44e-99ce-4b79-ba42-c121f019f77f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622414551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3622414551 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.742536769 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9419040000 ps |
| CPU time | 37.28 seconds |
| Started | Jun 10 04:58:04 PM PDT 24 |
| Finished | Jun 10 04:59:17 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-0c08a5df-9b82-4f0e-9fd8-f7adfb04834d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742536769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.742536769 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1805219410 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8747580000 ps |
| CPU time | 29.87 seconds |
| Started | Jun 10 04:58:05 PM PDT 24 |
| Finished | Jun 10 04:59:01 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-511ab3af-d23e-4c12-92db-d83421526a10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805219410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1805219410 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2397649325 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7695440000 ps |
| CPU time | 31.03 seconds |
| Started | Jun 10 04:57:59 PM PDT 24 |
| Finished | Jun 10 04:58:59 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-cc185385-9dee-439d-ab44-fd91481f3238 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397649325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2397649325 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2411338722 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12910260000 ps |
| CPU time | 50.19 seconds |
| Started | Jun 10 04:57:59 PM PDT 24 |
| Finished | Jun 10 04:59:35 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-aa56829a-e9ad-4ddd-80e7-c22bd65da5c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411338722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2411338722 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.919243351 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6195040000 ps |
| CPU time | 23.52 seconds |
| Started | Jun 10 04:58:00 PM PDT 24 |
| Finished | Jun 10 04:58:44 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-2d4e61bb-fde1-4102-98c1-00b008fe1e54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919243351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.919243351 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.4050930502 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5386560000 ps |
| CPU time | 18.52 seconds |
| Started | Jun 10 04:58:02 PM PDT 24 |
| Finished | Jun 10 04:58:37 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-4a19c045-2123-4d7e-b542-3a5595e2e0ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050930502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.4050930502 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2827403445 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13776400000 ps |
| CPU time | 48.21 seconds |
| Started | Jun 10 04:57:57 PM PDT 24 |
| Finished | Jun 10 04:59:29 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-0ae2146c-debf-41f3-88e2-916e552b4825 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827403445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2827403445 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2586482687 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5343160000 ps |
| CPU time | 20.06 seconds |
| Started | Jun 10 04:57:52 PM PDT 24 |
| Finished | Jun 10 04:58:31 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-7615f25c-22f6-4933-80dd-512ab499ce08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586482687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2586482687 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3917281353 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6351900000 ps |
| CPU time | 22.46 seconds |
| Started | Jun 10 04:58:02 PM PDT 24 |
| Finished | Jun 10 04:58:49 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-f166cdec-beb3-4e81-bd17-d7bb99cbb62d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917281353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3917281353 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3232185939 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6214260000 ps |
| CPU time | 25.98 seconds |
| Started | Jun 10 04:58:11 PM PDT 24 |
| Finished | Jun 10 04:59:03 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-d54deb06-e475-4b2b-90e6-ca54f402d8b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232185939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3232185939 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1563704417 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10499080000 ps |
| CPU time | 41.31 seconds |
| Started | Jun 10 04:57:57 PM PDT 24 |
| Finished | Jun 10 04:59:17 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-fdab0393-691f-490a-b715-8997038edc16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563704417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1563704417 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.4216108334 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11361500000 ps |
| CPU time | 44.12 seconds |
| Started | Jun 10 04:57:59 PM PDT 24 |
| Finished | Jun 10 04:59:27 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-8fbcddc3-4fb4-49b1-b456-d4ab8a5f5299 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216108334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.4216108334 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3551319630 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9058200000 ps |
| CPU time | 37.8 seconds |
| Started | Jun 10 04:58:06 PM PDT 24 |
| Finished | Jun 10 04:59:21 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-7c4b549c-9724-4777-8c41-9e6740217015 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551319630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3551319630 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3400691800 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 7355060000 ps |
| CPU time | 28.41 seconds |
| Started | Jun 10 04:58:04 PM PDT 24 |
| Finished | Jun 10 04:59:01 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-983a9ca7-4cfd-4284-9dfa-b9df75b5807f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400691800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3400691800 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1036486292 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13375880000 ps |
| CPU time | 45.37 seconds |
| Started | Jun 10 04:57:55 PM PDT 24 |
| Finished | Jun 10 04:59:20 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-67af771d-daf4-40f4-a96c-cbf889ae0f39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1036486292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1036486292 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.125422931 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13418660000 ps |
| CPU time | 48.31 seconds |
| Started | Jun 10 04:57:54 PM PDT 24 |
| Finished | Jun 10 04:59:26 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-b3750898-9f7c-4e0f-9a57-0d4c7093e667 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125422931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.125422931 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |