| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3180525661 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1267575850 |
| /workspace/coverage/default/1.prim_present_test.1107035873 |
| /workspace/coverage/default/11.prim_present_test.1578475891 |
| /workspace/coverage/default/12.prim_present_test.509248695 |
| /workspace/coverage/default/13.prim_present_test.3117791044 |
| /workspace/coverage/default/14.prim_present_test.3318647771 |
| /workspace/coverage/default/15.prim_present_test.548041784 |
| /workspace/coverage/default/16.prim_present_test.2412222096 |
| /workspace/coverage/default/17.prim_present_test.1290167740 |
| /workspace/coverage/default/18.prim_present_test.3358414908 |
| /workspace/coverage/default/19.prim_present_test.232145024 |
| /workspace/coverage/default/2.prim_present_test.3813435624 |
| /workspace/coverage/default/20.prim_present_test.179370108 |
| /workspace/coverage/default/21.prim_present_test.4158652001 |
| /workspace/coverage/default/22.prim_present_test.2141970842 |
| /workspace/coverage/default/23.prim_present_test.4178460163 |
| /workspace/coverage/default/24.prim_present_test.1603948094 |
| /workspace/coverage/default/25.prim_present_test.4018836436 |
| /workspace/coverage/default/26.prim_present_test.3424002162 |
| /workspace/coverage/default/27.prim_present_test.3298951422 |
| /workspace/coverage/default/28.prim_present_test.2618161268 |
| /workspace/coverage/default/29.prim_present_test.789001962 |
| /workspace/coverage/default/3.prim_present_test.2381475462 |
| /workspace/coverage/default/30.prim_present_test.567159848 |
| /workspace/coverage/default/31.prim_present_test.1316267863 |
| /workspace/coverage/default/32.prim_present_test.1001855601 |
| /workspace/coverage/default/33.prim_present_test.3680604574 |
| /workspace/coverage/default/34.prim_present_test.209153344 |
| /workspace/coverage/default/35.prim_present_test.2238039888 |
| /workspace/coverage/default/36.prim_present_test.3431499577 |
| /workspace/coverage/default/37.prim_present_test.2190147449 |
| /workspace/coverage/default/38.prim_present_test.4026331971 |
| /workspace/coverage/default/39.prim_present_test.1793109788 |
| /workspace/coverage/default/4.prim_present_test.1641579067 |
| /workspace/coverage/default/40.prim_present_test.2655393365 |
| /workspace/coverage/default/41.prim_present_test.263485551 |
| /workspace/coverage/default/42.prim_present_test.1597485525 |
| /workspace/coverage/default/43.prim_present_test.1481058505 |
| /workspace/coverage/default/44.prim_present_test.2043771229 |
| /workspace/coverage/default/45.prim_present_test.1174464579 |
| /workspace/coverage/default/46.prim_present_test.3079455805 |
| /workspace/coverage/default/47.prim_present_test.3631633063 |
| /workspace/coverage/default/48.prim_present_test.3981784378 |
| /workspace/coverage/default/49.prim_present_test.1650839194 |
| /workspace/coverage/default/5.prim_present_test.2941891594 |
| /workspace/coverage/default/6.prim_present_test.891521380 |
| /workspace/coverage/default/7.prim_present_test.1718783862 |
| /workspace/coverage/default/8.prim_present_test.5788190 |
| /workspace/coverage/default/9.prim_present_test.1312863237 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/27.prim_present_test.3298951422 | Jun 11 12:22:43 PM PDT 24 | Jun 11 12:23:32 PM PDT 24 | 7725200000 ps | ||
| T2 | /workspace/coverage/default/10.prim_present_test.3180525661 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:17:46 PM PDT 24 | 4392700000 ps | ||
| T3 | /workspace/coverage/default/46.prim_present_test.3079455805 | Jun 11 12:22:44 PM PDT 24 | Jun 11 12:23:48 PM PDT 24 | 10738400000 ps | ||
| T4 | /workspace/coverage/default/21.prim_present_test.4158652001 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:18:50 PM PDT 24 | 14708260000 ps | ||
| T5 | /workspace/coverage/default/9.prim_present_test.1312863237 | Jun 11 12:22:24 PM PDT 24 | Jun 11 12:23:41 PM PDT 24 | 11188520000 ps | ||
| T6 | /workspace/coverage/default/14.prim_present_test.3318647771 | Jun 11 12:17:09 PM PDT 24 | Jun 11 12:17:49 PM PDT 24 | 5087100000 ps | ||
| T7 | /workspace/coverage/default/7.prim_present_test.1718783862 | Jun 11 12:17:14 PM PDT 24 | Jun 11 12:18:32 PM PDT 24 | 11232540000 ps | ||
| T8 | /workspace/coverage/default/40.prim_present_test.2655393365 | Jun 11 12:17:15 PM PDT 24 | Jun 11 12:18:17 PM PDT 24 | 7865320000 ps | ||
| T9 | /workspace/coverage/default/8.prim_present_test.5788190 | Jun 11 12:17:55 PM PDT 24 | Jun 11 12:19:22 PM PDT 24 | 12998920000 ps | ||
| T10 | /workspace/coverage/default/11.prim_present_test.1578475891 | Jun 11 12:20:41 PM PDT 24 | Jun 11 12:22:01 PM PDT 24 | 14234580000 ps | ||
| T11 | /workspace/coverage/default/16.prim_present_test.2412222096 | Jun 11 12:17:14 PM PDT 24 | Jun 11 12:17:39 PM PDT 24 | 3572440000 ps | ||
| T12 | /workspace/coverage/default/47.prim_present_test.3631633063 | Jun 11 12:17:14 PM PDT 24 | Jun 11 12:18:11 PM PDT 24 | 8085420000 ps | ||
| T13 | /workspace/coverage/default/30.prim_present_test.567159848 | Jun 11 12:17:14 PM PDT 24 | Jun 11 12:18:24 PM PDT 24 | 10216360000 ps | ||
| T14 | /workspace/coverage/default/23.prim_present_test.4178460163 | Jun 11 12:20:42 PM PDT 24 | Jun 11 12:21:22 PM PDT 24 | 7207500000 ps | ||
| T15 | /workspace/coverage/default/41.prim_present_test.263485551 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:18:10 PM PDT 24 | 7984980000 ps | ||
| T16 | /workspace/coverage/default/35.prim_present_test.2238039888 | Jun 11 12:22:24 PM PDT 24 | Jun 11 12:23:44 PM PDT 24 | 11701260000 ps | ||
| T17 | /workspace/coverage/default/3.prim_present_test.2381475462 | Jun 11 12:17:15 PM PDT 24 | Jun 11 12:18:45 PM PDT 24 | 11922600000 ps | ||
| T18 | /workspace/coverage/default/45.prim_present_test.1174464579 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:18:07 PM PDT 24 | 7236020000 ps | ||
| T19 | /workspace/coverage/default/37.prim_present_test.2190147449 | Jun 11 12:22:26 PM PDT 24 | Jun 11 12:24:00 PM PDT 24 | 14394540000 ps | ||
| T20 | /workspace/coverage/default/13.prim_present_test.3117791044 | Jun 11 12:22:36 PM PDT 24 | Jun 11 12:23:14 PM PDT 24 | 5950760000 ps | ||
| T21 | /workspace/coverage/default/6.prim_present_test.891521380 | Jun 11 12:22:24 PM PDT 24 | Jun 11 12:23:38 PM PDT 24 | 10836360000 ps | ||
| T22 | /workspace/coverage/default/39.prim_present_test.1793109788 | Jun 11 12:18:22 PM PDT 24 | Jun 11 12:19:58 PM PDT 24 | 14697100000 ps | ||
| T23 | /workspace/coverage/default/25.prim_present_test.4018836436 | Jun 11 12:17:16 PM PDT 24 | Jun 11 12:18:27 PM PDT 24 | 9184060000 ps | ||
| T24 | /workspace/coverage/default/36.prim_present_test.3431499577 | Jun 11 12:17:16 PM PDT 24 | Jun 11 12:18:02 PM PDT 24 | 5797620000 ps | ||
| T25 | /workspace/coverage/default/34.prim_present_test.209153344 | Jun 11 12:17:08 PM PDT 24 | Jun 11 12:18:14 PM PDT 24 | 9360760000 ps | ||
| T26 | /workspace/coverage/default/20.prim_present_test.179370108 | Jun 11 12:22:35 PM PDT 24 | Jun 11 12:23:22 PM PDT 24 | 7487120000 ps | ||
| T27 | /workspace/coverage/default/43.prim_present_test.1481058505 | Jun 11 12:17:08 PM PDT 24 | Jun 11 12:18:43 PM PDT 24 | 13680300000 ps | ||
| T28 | /workspace/coverage/default/26.prim_present_test.3424002162 | Jun 11 12:22:25 PM PDT 24 | Jun 11 12:23:25 PM PDT 24 | 9076180000 ps | ||
| T29 | /workspace/coverage/default/24.prim_present_test.1603948094 | Jun 11 12:22:56 PM PDT 24 | Jun 11 12:24:12 PM PDT 24 | 11801700000 ps | ||
| T30 | /workspace/coverage/default/42.prim_present_test.1597485525 | Jun 11 12:17:14 PM PDT 24 | Jun 11 12:18:00 PM PDT 24 | 6524260000 ps | ||
| T31 | /workspace/coverage/default/0.prim_present_test.1267575850 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:18:48 PM PDT 24 | 13549480000 ps | ||
| T32 | /workspace/coverage/default/48.prim_present_test.3981784378 | Jun 11 12:22:43 PM PDT 24 | Jun 11 12:23:42 PM PDT 24 | 9730280000 ps | ||
| T33 | /workspace/coverage/default/15.prim_present_test.548041784 | Jun 11 12:17:09 PM PDT 24 | Jun 11 12:17:56 PM PDT 24 | 6594320000 ps | ||
| T34 | /workspace/coverage/default/49.prim_present_test.1650839194 | Jun 11 12:22:24 PM PDT 24 | Jun 11 12:22:57 PM PDT 24 | 4362320000 ps | ||
| T35 | /workspace/coverage/default/1.prim_present_test.1107035873 | Jun 11 12:17:57 PM PDT 24 | Jun 11 12:19:00 PM PDT 24 | 9545520000 ps | ||
| T36 | /workspace/coverage/default/17.prim_present_test.1290167740 | Jun 11 12:22:56 PM PDT 24 | Jun 11 12:24:24 PM PDT 24 | 13684020000 ps | ||
| T37 | /workspace/coverage/default/44.prim_present_test.2043771229 | Jun 11 12:22:24 PM PDT 24 | Jun 11 12:23:17 PM PDT 24 | 7385440000 ps | ||
| T38 | /workspace/coverage/default/4.prim_present_test.1641579067 | Jun 11 12:17:15 PM PDT 24 | Jun 11 12:18:33 PM PDT 24 | 11644840000 ps | ||
| T39 | /workspace/coverage/default/31.prim_present_test.1316267863 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:18:36 PM PDT 24 | 11267880000 ps | ||
| T40 | /workspace/coverage/default/29.prim_present_test.789001962 | Jun 11 12:22:24 PM PDT 24 | Jun 11 12:23:08 PM PDT 24 | 6171480000 ps | ||
| T41 | /workspace/coverage/default/33.prim_present_test.3680604574 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:17:48 PM PDT 24 | 4726260000 ps | ||
| T42 | /workspace/coverage/default/38.prim_present_test.4026331971 | Jun 11 12:17:15 PM PDT 24 | Jun 11 12:18:38 PM PDT 24 | 10995700000 ps | ||
| T43 | /workspace/coverage/default/32.prim_present_test.1001855601 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:18:59 PM PDT 24 | 15261300000 ps | ||
| T44 | /workspace/coverage/default/19.prim_present_test.232145024 | Jun 11 12:17:15 PM PDT 24 | Jun 11 12:17:58 PM PDT 24 | 5344400000 ps | ||
| T45 | /workspace/coverage/default/22.prim_present_test.2141970842 | Jun 11 12:17:13 PM PDT 24 | Jun 11 12:18:35 PM PDT 24 | 11204020000 ps | ||
| T46 | /workspace/coverage/default/12.prim_present_test.509248695 | Jun 11 12:22:44 PM PDT 24 | Jun 11 12:24:00 PM PDT 24 | 12934440000 ps | ||
| T47 | /workspace/coverage/default/5.prim_present_test.2941891594 | Jun 11 12:20:43 PM PDT 24 | Jun 11 12:21:45 PM PDT 24 | 11200920000 ps | ||
| T48 | /workspace/coverage/default/28.prim_present_test.2618161268 | Jun 11 12:20:41 PM PDT 24 | Jun 11 12:21:41 PM PDT 24 | 10623700000 ps | ||
| T49 | /workspace/coverage/default/2.prim_present_test.3813435624 | Jun 11 12:22:55 PM PDT 24 | Jun 11 12:24:28 PM PDT 24 | 14853960000 ps | ||
| T50 | /workspace/coverage/default/18.prim_present_test.3358414908 | Jun 11 12:17:16 PM PDT 24 | Jun 11 12:18:59 PM PDT 24 | 13927680000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3180525661 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4392700000 ps |
| CPU time | 16.8 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:17:46 PM PDT 24 |
| Peak memory | 142312 kb |
| Host | smart-575d6dc4-1eb8-4e0d-8ed9-6a696009a9a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180525661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3180525661 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1267575850 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13549480000 ps |
| CPU time | 48.4 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:18:48 PM PDT 24 |
| Peak memory | 144544 kb |
| Host | smart-a14b22b3-19dd-4513-b49e-c5211d12c14f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1267575850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1267575850 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1107035873 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9545520000 ps |
| CPU time | 32.98 seconds |
| Started | Jun 11 12:17:57 PM PDT 24 |
| Finished | Jun 11 12:19:00 PM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-be7917b7-09c4-4121-87bd-8381a92e376e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107035873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1107035873 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1578475891 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 14234580000 ps |
| CPU time | 44.26 seconds |
| Started | Jun 11 12:20:41 PM PDT 24 |
| Finished | Jun 11 12:22:01 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-a713a555-69de-4e0b-a583-06af9b01450d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578475891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1578475891 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.509248695 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12934440000 ps |
| CPU time | 39.98 seconds |
| Started | Jun 11 12:22:44 PM PDT 24 |
| Finished | Jun 11 12:24:00 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-0f41f000-5c8f-4835-a9b6-38801cd01322 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509248695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.509248695 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3117791044 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5950760000 ps |
| CPU time | 19.46 seconds |
| Started | Jun 11 12:22:36 PM PDT 24 |
| Finished | Jun 11 12:23:14 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-781dc947-bad4-4e77-bdef-40bc3035dd12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3117791044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3117791044 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3318647771 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5087100000 ps |
| CPU time | 20.48 seconds |
| Started | Jun 11 12:17:09 PM PDT 24 |
| Finished | Jun 11 12:17:49 PM PDT 24 |
| Peak memory | 143296 kb |
| Host | smart-a988de39-0483-470b-b2d5-8a8e3656bcf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3318647771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3318647771 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.548041784 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6594320000 ps |
| CPU time | 24.62 seconds |
| Started | Jun 11 12:17:09 PM PDT 24 |
| Finished | Jun 11 12:17:56 PM PDT 24 |
| Peak memory | 143476 kb |
| Host | smart-7cec15d4-2035-4ed5-b580-c4ad452a5928 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548041784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.548041784 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2412222096 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3572440000 ps |
| CPU time | 13.31 seconds |
| Started | Jun 11 12:17:14 PM PDT 24 |
| Finished | Jun 11 12:17:39 PM PDT 24 |
| Peak memory | 144304 kb |
| Host | smart-9faee80c-28ec-4e00-b629-cba6751dd652 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412222096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2412222096 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1290167740 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13684020000 ps |
| CPU time | 45.8 seconds |
| Started | Jun 11 12:22:56 PM PDT 24 |
| Finished | Jun 11 12:24:24 PM PDT 24 |
| Peak memory | 144080 kb |
| Host | smart-ccb95927-08a3-4678-96f8-18bf5dfff7b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290167740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1290167740 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3358414908 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13927680000 ps |
| CPU time | 53.85 seconds |
| Started | Jun 11 12:17:16 PM PDT 24 |
| Finished | Jun 11 12:18:59 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-b946649c-c99f-41ef-a844-806c31bc0435 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358414908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3358414908 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.232145024 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5344400000 ps |
| CPU time | 22.05 seconds |
| Started | Jun 11 12:17:15 PM PDT 24 |
| Finished | Jun 11 12:17:58 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-77ad3716-5f7a-4057-9cf6-549a883e2e62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=232145024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.232145024 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3813435624 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14853960000 ps |
| CPU time | 49.31 seconds |
| Started | Jun 11 12:22:55 PM PDT 24 |
| Finished | Jun 11 12:24:28 PM PDT 24 |
| Peak memory | 143824 kb |
| Host | smart-c1d9360d-ce52-459d-ade3-f2ed5428c77b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813435624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3813435624 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.179370108 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7487120000 ps |
| CPU time | 24.11 seconds |
| Started | Jun 11 12:22:35 PM PDT 24 |
| Finished | Jun 11 12:23:22 PM PDT 24 |
| Peak memory | 144700 kb |
| Host | smart-eec5d02d-170e-468f-8745-f07b5fb32959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179370108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.179370108 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4158652001 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14708260000 ps |
| CPU time | 51.4 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:18:50 PM PDT 24 |
| Peak memory | 144064 kb |
| Host | smart-e2767659-d4d5-4fc5-b639-ebd35c37c2ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158652001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4158652001 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2141970842 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11204020000 ps |
| CPU time | 41.38 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:18:35 PM PDT 24 |
| Peak memory | 144560 kb |
| Host | smart-e4d30c80-8212-4bc5-8522-ba64ed882267 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141970842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2141970842 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.4178460163 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7207500000 ps |
| CPU time | 21.5 seconds |
| Started | Jun 11 12:20:42 PM PDT 24 |
| Finished | Jun 11 12:21:22 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-bd7ea0e9-fca4-426d-8a0d-1efcb6326ae4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178460163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.4178460163 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1603948094 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11801700000 ps |
| CPU time | 39.17 seconds |
| Started | Jun 11 12:22:56 PM PDT 24 |
| Finished | Jun 11 12:24:12 PM PDT 24 |
| Peak memory | 144240 kb |
| Host | smart-8394ed1d-034a-4b39-929c-22fc88e6a43d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1603948094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1603948094 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4018836436 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9184060000 ps |
| CPU time | 36.36 seconds |
| Started | Jun 11 12:17:16 PM PDT 24 |
| Finished | Jun 11 12:18:27 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-1dbcd67d-b7fd-461d-a275-b3610cefdef6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018836436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4018836436 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3424002162 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9076180000 ps |
| CPU time | 31.37 seconds |
| Started | Jun 11 12:22:25 PM PDT 24 |
| Finished | Jun 11 12:23:25 PM PDT 24 |
| Peak memory | 144712 kb |
| Host | smart-adb151fb-dbe1-496c-87cf-81074760c171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424002162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3424002162 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3298951422 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7725200000 ps |
| CPU time | 25.1 seconds |
| Started | Jun 11 12:22:43 PM PDT 24 |
| Finished | Jun 11 12:23:32 PM PDT 24 |
| Peak memory | 144704 kb |
| Host | smart-3272d5d5-fbfb-4173-8e1a-77630bfe1395 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298951422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3298951422 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2618161268 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10623700000 ps |
| CPU time | 32.64 seconds |
| Started | Jun 11 12:20:41 PM PDT 24 |
| Finished | Jun 11 12:21:41 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-aa240e22-4d38-4cd1-aa96-4c10b06dd82b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618161268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2618161268 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.789001962 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6171480000 ps |
| CPU time | 22.59 seconds |
| Started | Jun 11 12:22:24 PM PDT 24 |
| Finished | Jun 11 12:23:08 PM PDT 24 |
| Peak memory | 142836 kb |
| Host | smart-aad97a73-2c6e-4248-a51b-361f53a68f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789001962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.789001962 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2381475462 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11922600000 ps |
| CPU time | 47.2 seconds |
| Started | Jun 11 12:17:15 PM PDT 24 |
| Finished | Jun 11 12:18:45 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-9d9a8bf5-8595-4945-ae68-43c5f648d8b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2381475462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2381475462 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.567159848 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10216360000 ps |
| CPU time | 36.57 seconds |
| Started | Jun 11 12:17:14 PM PDT 24 |
| Finished | Jun 11 12:18:24 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-db12a133-6969-4fc0-a618-dbfd2d8a8e3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567159848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.567159848 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1316267863 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11267880000 ps |
| CPU time | 42.09 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:18:36 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-ad417c8a-29bb-458f-9b9b-d1ebef74b212 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316267863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1316267863 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1001855601 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15261300000 ps |
| CPU time | 54.86 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:18:59 PM PDT 24 |
| Peak memory | 144560 kb |
| Host | smart-67480902-8cc1-4b78-aac0-5f89df844fac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001855601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1001855601 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3680604574 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4726260000 ps |
| CPU time | 17.99 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:17:48 PM PDT 24 |
| Peak memory | 142752 kb |
| Host | smart-596e38f7-3f23-47bf-b11e-6bc4e3988476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680604574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3680604574 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.209153344 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9360760000 ps |
| CPU time | 35.09 seconds |
| Started | Jun 11 12:17:08 PM PDT 24 |
| Finished | Jun 11 12:18:14 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-196631d2-1263-488e-9180-e0a9715d9c1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209153344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.209153344 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2238039888 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11701260000 ps |
| CPU time | 40.29 seconds |
| Started | Jun 11 12:22:24 PM PDT 24 |
| Finished | Jun 11 12:23:44 PM PDT 24 |
| Peak memory | 142780 kb |
| Host | smart-5b8cffcc-c0ff-450e-b241-cfb7cd9fadcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238039888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2238039888 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3431499577 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5797620000 ps |
| CPU time | 23.28 seconds |
| Started | Jun 11 12:17:16 PM PDT 24 |
| Finished | Jun 11 12:18:02 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-058f798f-3cef-46f9-920c-b5d7661c84a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431499577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3431499577 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2190147449 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14394540000 ps |
| CPU time | 47.79 seconds |
| Started | Jun 11 12:22:26 PM PDT 24 |
| Finished | Jun 11 12:24:00 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-99a9dc50-3e96-496a-9638-998b52fe911e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190147449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2190147449 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.4026331971 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10995700000 ps |
| CPU time | 43.46 seconds |
| Started | Jun 11 12:17:15 PM PDT 24 |
| Finished | Jun 11 12:18:38 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-6e2105fb-7286-411e-8d46-eef28ea04f2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026331971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.4026331971 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1793109788 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14697100000 ps |
| CPU time | 50.26 seconds |
| Started | Jun 11 12:18:22 PM PDT 24 |
| Finished | Jun 11 12:19:58 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-26612015-5c32-4ecd-9262-85473fd967b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793109788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1793109788 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1641579067 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11644840000 ps |
| CPU time | 41.61 seconds |
| Started | Jun 11 12:17:15 PM PDT 24 |
| Finished | Jun 11 12:18:33 PM PDT 24 |
| Peak memory | 144796 kb |
| Host | smart-5e6501e3-48cd-46c5-be27-e802fde1bb98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641579067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1641579067 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2655393365 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7865320000 ps |
| CPU time | 31.84 seconds |
| Started | Jun 11 12:17:15 PM PDT 24 |
| Finished | Jun 11 12:18:17 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-eee1914e-9999-4aea-bc0b-aef27992c71b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655393365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2655393365 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.263485551 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7984980000 ps |
| CPU time | 29.75 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:18:10 PM PDT 24 |
| Peak memory | 143944 kb |
| Host | smart-c42ace6c-666f-4518-8b0e-07c980115c7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=263485551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.263485551 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1597485525 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6524260000 ps |
| CPU time | 24.22 seconds |
| Started | Jun 11 12:17:14 PM PDT 24 |
| Finished | Jun 11 12:18:00 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-741da13f-9e6e-4c62-9939-ec0a7398558b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597485525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1597485525 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1481058505 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13680300000 ps |
| CPU time | 49.67 seconds |
| Started | Jun 11 12:17:08 PM PDT 24 |
| Finished | Jun 11 12:18:43 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-af661a8d-c490-4c06-a3ac-0325e248020a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481058505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1481058505 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2043771229 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 7385440000 ps |
| CPU time | 27.01 seconds |
| Started | Jun 11 12:22:24 PM PDT 24 |
| Finished | Jun 11 12:23:17 PM PDT 24 |
| Peak memory | 143140 kb |
| Host | smart-58ab9287-0390-43d5-90de-bb0e1ad0fe19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043771229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2043771229 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1174464579 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7236020000 ps |
| CPU time | 27.23 seconds |
| Started | Jun 11 12:17:13 PM PDT 24 |
| Finished | Jun 11 12:18:07 PM PDT 24 |
| Peak memory | 142832 kb |
| Host | smart-66727114-a3c6-4ecb-b0bd-8320a9e92eb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174464579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1174464579 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3079455805 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10738400000 ps |
| CPU time | 33.74 seconds |
| Started | Jun 11 12:22:44 PM PDT 24 |
| Finished | Jun 11 12:23:48 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-45fdbf4b-2165-46ba-b12c-16122eb0d4c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079455805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3079455805 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3631633063 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8085420000 ps |
| CPU time | 30.18 seconds |
| Started | Jun 11 12:17:14 PM PDT 24 |
| Finished | Jun 11 12:18:11 PM PDT 24 |
| Peak memory | 144484 kb |
| Host | smart-2c53bc4e-3c60-4000-b5fa-a28daa62b56d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631633063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3631633063 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3981784378 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9730280000 ps |
| CPU time | 30.5 seconds |
| Started | Jun 11 12:22:43 PM PDT 24 |
| Finished | Jun 11 12:23:42 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-1010a567-b585-4011-bd1d-55b62a36b823 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981784378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3981784378 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1650839194 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4362320000 ps |
| CPU time | 16.55 seconds |
| Started | Jun 11 12:22:24 PM PDT 24 |
| Finished | Jun 11 12:22:57 PM PDT 24 |
| Peak memory | 143024 kb |
| Host | smart-f5495900-a0ae-41b1-8f5f-9cc740d221c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650839194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1650839194 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2941891594 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11200920000 ps |
| CPU time | 33.32 seconds |
| Started | Jun 11 12:20:43 PM PDT 24 |
| Finished | Jun 11 12:21:45 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-e776df91-6158-4e57-bccb-04df8d9d8df5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941891594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2941891594 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.891521380 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10836360000 ps |
| CPU time | 36.62 seconds |
| Started | Jun 11 12:22:24 PM PDT 24 |
| Finished | Jun 11 12:23:38 PM PDT 24 |
| Peak memory | 143076 kb |
| Host | smart-cfc9b7f4-8c9a-4fe7-a33d-d7a573efc479 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891521380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.891521380 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1718783862 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11232540000 ps |
| CPU time | 41.71 seconds |
| Started | Jun 11 12:17:14 PM PDT 24 |
| Finished | Jun 11 12:18:32 PM PDT 24 |
| Peak memory | 144592 kb |
| Host | smart-2d20443f-109c-4cac-8fa6-2db4e284d2b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718783862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1718783862 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.5788190 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12998920000 ps |
| CPU time | 46.21 seconds |
| Started | Jun 11 12:17:55 PM PDT 24 |
| Finished | Jun 11 12:19:22 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-e11eca3a-fe0c-4b67-9b79-d1180c6d49e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5788190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.5788190 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1312863237 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11188520000 ps |
| CPU time | 39.04 seconds |
| Started | Jun 11 12:22:24 PM PDT 24 |
| Finished | Jun 11 12:23:41 PM PDT 24 |
| Peak memory | 142840 kb |
| Host | smart-22650072-df96-4a7a-8fac-c4246eedd47c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312863237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1312863237 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |