| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.3593843643 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1090771656 |
| /workspace/coverage/default/10.prim_present_test.542230357 |
| /workspace/coverage/default/11.prim_present_test.3633977396 |
| /workspace/coverage/default/12.prim_present_test.4174968750 |
| /workspace/coverage/default/13.prim_present_test.3712661690 |
| /workspace/coverage/default/14.prim_present_test.4082182271 |
| /workspace/coverage/default/15.prim_present_test.3296793032 |
| /workspace/coverage/default/16.prim_present_test.3708359504 |
| /workspace/coverage/default/17.prim_present_test.1574194881 |
| /workspace/coverage/default/18.prim_present_test.1847005009 |
| /workspace/coverage/default/19.prim_present_test.1098746206 |
| /workspace/coverage/default/2.prim_present_test.2702399306 |
| /workspace/coverage/default/20.prim_present_test.3722874370 |
| /workspace/coverage/default/21.prim_present_test.916192100 |
| /workspace/coverage/default/22.prim_present_test.3179197032 |
| /workspace/coverage/default/23.prim_present_test.3544704943 |
| /workspace/coverage/default/24.prim_present_test.2813953261 |
| /workspace/coverage/default/25.prim_present_test.1080776632 |
| /workspace/coverage/default/26.prim_present_test.2587702422 |
| /workspace/coverage/default/27.prim_present_test.3835430528 |
| /workspace/coverage/default/28.prim_present_test.71755201 |
| /workspace/coverage/default/29.prim_present_test.1957252353 |
| /workspace/coverage/default/3.prim_present_test.3537587499 |
| /workspace/coverage/default/30.prim_present_test.2239557624 |
| /workspace/coverage/default/31.prim_present_test.3126183836 |
| /workspace/coverage/default/32.prim_present_test.254118686 |
| /workspace/coverage/default/33.prim_present_test.448499788 |
| /workspace/coverage/default/34.prim_present_test.2703208171 |
| /workspace/coverage/default/35.prim_present_test.608116640 |
| /workspace/coverage/default/36.prim_present_test.4009202344 |
| /workspace/coverage/default/37.prim_present_test.2034861286 |
| /workspace/coverage/default/38.prim_present_test.2499396854 |
| /workspace/coverage/default/39.prim_present_test.1213668593 |
| /workspace/coverage/default/4.prim_present_test.1559967029 |
| /workspace/coverage/default/40.prim_present_test.1538340348 |
| /workspace/coverage/default/41.prim_present_test.132286060 |
| /workspace/coverage/default/42.prim_present_test.925361401 |
| /workspace/coverage/default/43.prim_present_test.3694043577 |
| /workspace/coverage/default/44.prim_present_test.2859924941 |
| /workspace/coverage/default/45.prim_present_test.1624508409 |
| /workspace/coverage/default/46.prim_present_test.469087755 |
| /workspace/coverage/default/47.prim_present_test.1858022306 |
| /workspace/coverage/default/48.prim_present_test.182149057 |
| /workspace/coverage/default/49.prim_present_test.1575748498 |
| /workspace/coverage/default/5.prim_present_test.4036226857 |
| /workspace/coverage/default/6.prim_present_test.469024769 |
| /workspace/coverage/default/7.prim_present_test.425647355 |
| /workspace/coverage/default/8.prim_present_test.1252189833 |
| /workspace/coverage/default/9.prim_present_test.397236714 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/4.prim_present_test.1559967029 | Jun 13 01:52:18 PM PDT 24 | Jun 13 01:53:18 PM PDT 24 | 10211400000 ps | ||
| T2 | /workspace/coverage/default/22.prim_present_test.3179197032 | Jun 13 01:52:22 PM PDT 24 | Jun 13 01:54:15 PM PDT 24 | 13784460000 ps | ||
| T3 | /workspace/coverage/default/6.prim_present_test.469024769 | Jun 13 01:52:21 PM PDT 24 | Jun 13 01:53:32 PM PDT 24 | 10263480000 ps | ||
| T4 | /workspace/coverage/default/1.prim_present_test.3593843643 | Jun 13 01:52:21 PM PDT 24 | Jun 13 01:53:11 PM PDT 24 | 6505040000 ps | ||
| T5 | /workspace/coverage/default/30.prim_present_test.2239557624 | Jun 13 01:52:21 PM PDT 24 | Jun 13 01:52:57 PM PDT 24 | 4808100000 ps | ||
| T6 | /workspace/coverage/default/28.prim_present_test.71755201 | Jun 13 01:52:21 PM PDT 24 | Jun 13 01:53:47 PM PDT 24 | 9231800000 ps | ||
| T7 | /workspace/coverage/default/27.prim_present_test.3835430528 | Jun 13 01:52:19 PM PDT 24 | Jun 13 01:53:14 PM PDT 24 | 9013560000 ps | ||
| T8 | /workspace/coverage/default/8.prim_present_test.1252189833 | Jun 13 01:52:20 PM PDT 24 | Jun 13 01:53:25 PM PDT 24 | 8655820000 ps | ||
| T9 | /workspace/coverage/default/10.prim_present_test.542230357 | Jun 13 01:52:18 PM PDT 24 | Jun 13 01:52:48 PM PDT 24 | 3794400000 ps | ||
| T10 | /workspace/coverage/default/46.prim_present_test.469087755 | Jun 13 01:52:26 PM PDT 24 | Jun 13 01:53:56 PM PDT 24 | 9736480000 ps | ||
| T11 | /workspace/coverage/default/37.prim_present_test.2034861286 | Jun 13 01:52:25 PM PDT 24 | Jun 13 01:54:04 PM PDT 24 | 11911440000 ps | ||
| T12 | /workspace/coverage/default/39.prim_present_test.1213668593 | Jun 13 01:52:26 PM PDT 24 | Jun 13 01:53:11 PM PDT 24 | 5456000000 ps | ||
| T13 | /workspace/coverage/default/0.prim_present_test.1090771656 | Jun 13 01:52:19 PM PDT 24 | Jun 13 01:53:10 PM PDT 24 | 6103900000 ps | ||
| T14 | /workspace/coverage/default/25.prim_present_test.1080776632 | Jun 13 01:52:17 PM PDT 24 | Jun 13 01:52:48 PM PDT 24 | 5056720000 ps | ||
| T15 | /workspace/coverage/default/2.prim_present_test.2702399306 | Jun 13 01:52:19 PM PDT 24 | Jun 13 01:53:25 PM PDT 24 | 7539820000 ps | ||
| T16 | /workspace/coverage/default/19.prim_present_test.1098746206 | Jun 13 01:52:18 PM PDT 24 | Jun 13 01:54:04 PM PDT 24 | 13731760000 ps | ||
| T17 | /workspace/coverage/default/41.prim_present_test.132286060 | Jun 13 01:52:26 PM PDT 24 | Jun 13 01:53:13 PM PDT 24 | 6843560000 ps | ||
| T18 | /workspace/coverage/default/29.prim_present_test.1957252353 | Jun 13 01:52:21 PM PDT 24 | Jun 13 01:54:04 PM PDT 24 | 11470620000 ps | ||
| T19 | /workspace/coverage/default/32.prim_present_test.254118686 | Jun 13 01:52:22 PM PDT 24 | Jun 13 01:53:20 PM PDT 24 | 7156660000 ps | ||
| T20 | /workspace/coverage/default/45.prim_present_test.1624508409 | Jun 13 01:52:24 PM PDT 24 | Jun 13 01:53:37 PM PDT 24 | 9600080000 ps | ||
| T21 | /workspace/coverage/default/15.prim_present_test.3296793032 | Jun 13 01:52:18 PM PDT 24 | Jun 13 01:53:26 PM PDT 24 | 9755700000 ps | ||
| T22 | /workspace/coverage/default/24.prim_present_test.2813953261 | Jun 13 01:52:21 PM PDT 24 | Jun 13 01:53:02 PM PDT 24 | 5620300000 ps | ||
| T23 | /workspace/coverage/default/49.prim_present_test.1575748498 | Jun 13 01:52:26 PM PDT 24 | Jun 13 01:53:14 PM PDT 24 | 5013320000 ps | ||
| T24 | /workspace/coverage/default/17.prim_present_test.1574194881 | Jun 13 01:52:20 PM PDT 24 | Jun 13 01:54:14 PM PDT 24 | 14865740000 ps | ||
| T25 | /workspace/coverage/default/11.prim_present_test.3633977396 | Jun 13 01:52:18 PM PDT 24 | Jun 13 01:53:27 PM PDT 24 | 8743860000 ps | ||
| T26 | /workspace/coverage/default/33.prim_present_test.448499788 | Jun 13 01:52:24 PM PDT 24 | Jun 13 01:54:01 PM PDT 24 | 11414200000 ps | ||
| T27 | /workspace/coverage/default/3.prim_present_test.3537587499 | Jun 13 01:52:22 PM PDT 24 | Jun 13 01:52:51 PM PDT 24 | 3688380000 ps | ||
| T28 | /workspace/coverage/default/14.prim_present_test.4082182271 | Jun 13 01:52:19 PM PDT 24 | Jun 13 01:53:37 PM PDT 24 | 12922660000 ps | ||
| T29 | /workspace/coverage/default/5.prim_present_test.4036226857 | Jun 13 01:52:21 PM PDT 24 | Jun 13 01:53:20 PM PDT 24 | 10251080000 ps | ||
| T30 | /workspace/coverage/default/44.prim_present_test.2859924941 | Jun 13 01:52:28 PM PDT 24 | Jun 13 01:54:24 PM PDT 24 | 14061600000 ps | ||
| T31 | /workspace/coverage/default/16.prim_present_test.3708359504 | Jun 13 01:52:18 PM PDT 24 | Jun 13 01:53:56 PM PDT 24 | 13686500000 ps | ||
| T32 | /workspace/coverage/default/23.prim_present_test.3544704943 | Jun 13 01:52:19 PM PDT 24 | Jun 13 01:53:02 PM PDT 24 | 6854100000 ps | ||
| T33 | /workspace/coverage/default/7.prim_present_test.425647355 | Jun 13 01:52:24 PM PDT 24 | Jun 13 01:53:31 PM PDT 24 | 8817020000 ps | ||
| T34 | /workspace/coverage/default/34.prim_present_test.2703208171 | Jun 13 01:52:23 PM PDT 24 | Jun 13 01:52:49 PM PDT 24 | 3906620000 ps | ||
| T35 | /workspace/coverage/default/35.prim_present_test.608116640 | Jun 13 01:52:26 PM PDT 24 | Jun 13 01:52:57 PM PDT 24 | 4088900000 ps | ||
| T36 | /workspace/coverage/default/47.prim_present_test.1858022306 | Jun 13 01:52:24 PM PDT 24 | Jun 13 01:54:13 PM PDT 24 | 14841560000 ps | ||
| T37 | /workspace/coverage/default/21.prim_present_test.916192100 | Jun 13 01:52:22 PM PDT 24 | Jun 13 01:53:40 PM PDT 24 | 13554440000 ps | ||
| T38 | /workspace/coverage/default/12.prim_present_test.4174968750 | Jun 13 01:52:21 PM PDT 24 | Jun 13 01:54:29 PM PDT 24 | 13851420000 ps | ||
| T39 | /workspace/coverage/default/18.prim_present_test.1847005009 | Jun 13 01:52:18 PM PDT 24 | Jun 13 01:52:41 PM PDT 24 | 3543920000 ps | ||
| T40 | /workspace/coverage/default/42.prim_present_test.925361401 | Jun 13 01:52:29 PM PDT 24 | Jun 13 01:53:25 PM PDT 24 | 7362500000 ps | ||
| T41 | /workspace/coverage/default/40.prim_present_test.1538340348 | Jun 13 01:52:25 PM PDT 24 | Jun 13 01:54:08 PM PDT 24 | 13455240000 ps | ||
| T42 | /workspace/coverage/default/26.prim_present_test.2587702422 | Jun 13 01:52:20 PM PDT 24 | Jun 13 01:53:35 PM PDT 24 | 7379860000 ps | ||
| T43 | /workspace/coverage/default/38.prim_present_test.2499396854 | Jun 13 01:52:26 PM PDT 24 | Jun 13 01:53:31 PM PDT 24 | 9988820000 ps | ||
| T44 | /workspace/coverage/default/13.prim_present_test.3712661690 | Jun 13 01:52:20 PM PDT 24 | Jun 13 01:53:16 PM PDT 24 | 8109600000 ps | ||
| T45 | /workspace/coverage/default/36.prim_present_test.4009202344 | Jun 13 01:52:24 PM PDT 24 | Jun 13 01:53:33 PM PDT 24 | 9056340000 ps | ||
| T46 | /workspace/coverage/default/31.prim_present_test.3126183836 | Jun 13 01:52:19 PM PDT 24 | Jun 13 01:53:55 PM PDT 24 | 13969840000 ps | ||
| T47 | /workspace/coverage/default/48.prim_present_test.182149057 | Jun 13 01:52:26 PM PDT 24 | Jun 13 01:53:38 PM PDT 24 | 9127020000 ps | ||
| T48 | /workspace/coverage/default/43.prim_present_test.3694043577 | Jun 13 01:52:24 PM PDT 24 | Jun 13 01:53:10 PM PDT 24 | 4588000000 ps | ||
| T49 | /workspace/coverage/default/20.prim_present_test.3722874370 | Jun 13 01:52:19 PM PDT 24 | Jun 13 01:53:34 PM PDT 24 | 9078040000 ps | ||
| T50 | /workspace/coverage/default/9.prim_present_test.397236714 | Jun 13 01:52:20 PM PDT 24 | Jun 13 01:54:16 PM PDT 24 | 14198000000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.3593843643 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6505040000 ps |
| CPU time | 24.92 seconds |
| Started | Jun 13 01:52:21 PM PDT 24 |
| Finished | Jun 13 01:53:11 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-c1bbd0d0-2917-471c-b1f5-8abfafb70422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3593843643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3593843643 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1090771656 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6103900000 ps |
| CPU time | 25.26 seconds |
| Started | Jun 13 01:52:19 PM PDT 24 |
| Finished | Jun 13 01:53:10 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-590b2eb5-80fe-4127-9e50-d7cb9fc2e7bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090771656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1090771656 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.542230357 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3794400000 ps |
| CPU time | 14.35 seconds |
| Started | Jun 13 01:52:18 PM PDT 24 |
| Finished | Jun 13 01:52:48 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-f46dc04b-8939-41a7-8eb5-802bf5fa5323 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542230357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.542230357 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3633977396 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8743860000 ps |
| CPU time | 34.49 seconds |
| Started | Jun 13 01:52:18 PM PDT 24 |
| Finished | Jun 13 01:53:27 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-846d2882-fb36-473d-af1e-507f6bda863d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633977396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3633977396 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4174968750 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13851420000 ps |
| CPU time | 61.26 seconds |
| Started | Jun 13 01:52:21 PM PDT 24 |
| Finished | Jun 13 01:54:29 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-a4d12b72-a8e6-40a1-bf3b-f95cc85cb16c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174968750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4174968750 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3712661690 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8109600000 ps |
| CPU time | 29.17 seconds |
| Started | Jun 13 01:52:20 PM PDT 24 |
| Finished | Jun 13 01:53:16 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-1a6e0610-ad11-4701-bf23-7e585e303c36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712661690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3712661690 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4082182271 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12922660000 ps |
| CPU time | 41.12 seconds |
| Started | Jun 13 01:52:19 PM PDT 24 |
| Finished | Jun 13 01:53:37 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-ffd572f0-a42a-4392-b353-7b93df908ef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082182271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4082182271 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3296793032 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9755700000 ps |
| CPU time | 35.31 seconds |
| Started | Jun 13 01:52:18 PM PDT 24 |
| Finished | Jun 13 01:53:26 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-68c982cd-7c09-473a-97d7-1037ca3561f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296793032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3296793032 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3708359504 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13686500000 ps |
| CPU time | 51.27 seconds |
| Started | Jun 13 01:52:18 PM PDT 24 |
| Finished | Jun 13 01:53:56 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-a0bb0cec-a5af-4e7b-a73e-3e45114dee67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708359504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3708359504 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1574194881 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 14865740000 ps |
| CPU time | 58.23 seconds |
| Started | Jun 13 01:52:20 PM PDT 24 |
| Finished | Jun 13 01:54:14 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-e3d31bfb-a2c7-4f45-9208-c1de159f56aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574194881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1574194881 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1847005009 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3543920000 ps |
| CPU time | 11.45 seconds |
| Started | Jun 13 01:52:18 PM PDT 24 |
| Finished | Jun 13 01:52:41 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-6da77172-1b60-4335-83d7-dbfe474e1895 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1847005009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1847005009 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1098746206 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13731760000 ps |
| CPU time | 54.57 seconds |
| Started | Jun 13 01:52:18 PM PDT 24 |
| Finished | Jun 13 01:54:04 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-7f7147b6-3c77-4d8a-882c-00e362c0acad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098746206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1098746206 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2702399306 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7539820000 ps |
| CPU time | 30.98 seconds |
| Started | Jun 13 01:52:19 PM PDT 24 |
| Finished | Jun 13 01:53:25 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-546d88b5-38a8-4860-bd3c-d2e4f81a81d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702399306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2702399306 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3722874370 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9078040000 ps |
| CPU time | 37.52 seconds |
| Started | Jun 13 01:52:19 PM PDT 24 |
| Finished | Jun 13 01:53:34 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-4253fd4a-ec77-449d-8cb5-8de73b51e06e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722874370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3722874370 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.916192100 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13554440000 ps |
| CPU time | 41.31 seconds |
| Started | Jun 13 01:52:22 PM PDT 24 |
| Finished | Jun 13 01:53:40 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-f4e7738f-46d3-4fec-84c6-a8dbb6e312e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916192100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.916192100 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3179197032 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13784460000 ps |
| CPU time | 57.51 seconds |
| Started | Jun 13 01:52:22 PM PDT 24 |
| Finished | Jun 13 01:54:15 PM PDT 24 |
| Peak memory | 144212 kb |
| Host | smart-984d2ec6-3152-4050-a648-410503bdb72a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3179197032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3179197032 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3544704943 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6854100000 ps |
| CPU time | 22.16 seconds |
| Started | Jun 13 01:52:19 PM PDT 24 |
| Finished | Jun 13 01:53:02 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-49555158-e064-406a-a4ab-7f7c75df7bef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544704943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3544704943 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2813953261 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5620300000 ps |
| CPU time | 20.09 seconds |
| Started | Jun 13 01:52:21 PM PDT 24 |
| Finished | Jun 13 01:53:02 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-cb748ce0-81cd-431d-8ac0-5f1d7fa76184 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813953261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2813953261 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1080776632 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5056720000 ps |
| CPU time | 15.92 seconds |
| Started | Jun 13 01:52:17 PM PDT 24 |
| Finished | Jun 13 01:52:48 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-200ddeda-6f99-4ca0-ae40-d7f5eccbba61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080776632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1080776632 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2587702422 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 7379860000 ps |
| CPU time | 34.97 seconds |
| Started | Jun 13 01:52:20 PM PDT 24 |
| Finished | Jun 13 01:53:35 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-e80a59d5-2d51-45db-92d7-fe85a4d535e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587702422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2587702422 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3835430528 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9013560000 ps |
| CPU time | 28.38 seconds |
| Started | Jun 13 01:52:19 PM PDT 24 |
| Finished | Jun 13 01:53:14 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-e27ec79d-509d-4ff0-85ae-d6c6f469cda3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3835430528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3835430528 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.71755201 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9231800000 ps |
| CPU time | 40.16 seconds |
| Started | Jun 13 01:52:21 PM PDT 24 |
| Finished | Jun 13 01:53:47 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-0d381c6b-17a2-4e86-b960-614150b41a97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71755201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.71755201 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1957252353 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11470620000 ps |
| CPU time | 48.7 seconds |
| Started | Jun 13 01:52:21 PM PDT 24 |
| Finished | Jun 13 01:54:04 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-6aa815ce-6d0b-4623-90b9-756e5ff041df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957252353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1957252353 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3537587499 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3688380000 ps |
| CPU time | 14.1 seconds |
| Started | Jun 13 01:52:22 PM PDT 24 |
| Finished | Jun 13 01:52:51 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-66fe844c-3c58-4429-85e9-64fc22fe5e62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537587499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3537587499 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2239557624 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4808100000 ps |
| CPU time | 17.5 seconds |
| Started | Jun 13 01:52:21 PM PDT 24 |
| Finished | Jun 13 01:52:57 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-b91774ff-0850-4b2f-a0dd-4e7299eb9a68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239557624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2239557624 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3126183836 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13969840000 ps |
| CPU time | 49.22 seconds |
| Started | Jun 13 01:52:19 PM PDT 24 |
| Finished | Jun 13 01:53:55 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-d07fa872-5d45-403f-b87f-03caf3f4cc6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126183836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3126183836 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.254118686 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7156660000 ps |
| CPU time | 29.56 seconds |
| Started | Jun 13 01:52:22 PM PDT 24 |
| Finished | Jun 13 01:53:20 PM PDT 24 |
| Peak memory | 144296 kb |
| Host | smart-29e97666-187f-4415-94b2-829b780eece0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=254118686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.254118686 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.448499788 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11414200000 ps |
| CPU time | 48.26 seconds |
| Started | Jun 13 01:52:24 PM PDT 24 |
| Finished | Jun 13 01:54:01 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-ec981c52-35e7-4b5e-a97a-2252041a232e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448499788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.448499788 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2703208171 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3906620000 ps |
| CPU time | 13.15 seconds |
| Started | Jun 13 01:52:23 PM PDT 24 |
| Finished | Jun 13 01:52:49 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-11fa58c6-b8b4-4126-a502-0cddb2baa38d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703208171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2703208171 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.608116640 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4088900000 ps |
| CPU time | 15.69 seconds |
| Started | Jun 13 01:52:26 PM PDT 24 |
| Finished | Jun 13 01:52:57 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-d1a1d7ed-7bfb-4e55-9a78-65fe901a680f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608116640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.608116640 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4009202344 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9056340000 ps |
| CPU time | 35.84 seconds |
| Started | Jun 13 01:52:24 PM PDT 24 |
| Finished | Jun 13 01:53:33 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-4907665e-ef50-492c-b72d-6ff73918699b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009202344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4009202344 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2034861286 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11911440000 ps |
| CPU time | 48.48 seconds |
| Started | Jun 13 01:52:25 PM PDT 24 |
| Finished | Jun 13 01:54:04 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-6d16c647-e453-4d42-a34e-9219505dfebe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034861286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2034861286 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2499396854 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 9988820000 ps |
| CPU time | 34.07 seconds |
| Started | Jun 13 01:52:26 PM PDT 24 |
| Finished | Jun 13 01:53:31 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-2b17941b-f5a1-422c-8f72-6b53c4ef0b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499396854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2499396854 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1213668593 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5456000000 ps |
| CPU time | 22.4 seconds |
| Started | Jun 13 01:52:26 PM PDT 24 |
| Finished | Jun 13 01:53:11 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-b97c6dea-7c81-46b2-a3dc-3db6072ba476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213668593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1213668593 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1559967029 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10211400000 ps |
| CPU time | 31.62 seconds |
| Started | Jun 13 01:52:18 PM PDT 24 |
| Finished | Jun 13 01:53:18 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-42d750ea-b80c-443b-86f5-1960f3b234a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1559967029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1559967029 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1538340348 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13455240000 ps |
| CPU time | 53.09 seconds |
| Started | Jun 13 01:52:25 PM PDT 24 |
| Finished | Jun 13 01:54:08 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-16dcffd4-85f4-46c7-b829-b9e7c0ff19df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538340348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1538340348 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.132286060 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6843560000 ps |
| CPU time | 24.69 seconds |
| Started | Jun 13 01:52:26 PM PDT 24 |
| Finished | Jun 13 01:53:13 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-f5b17ba3-c485-4bcd-be99-1fcb564a8851 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132286060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.132286060 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.925361401 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7362500000 ps |
| CPU time | 28.79 seconds |
| Started | Jun 13 01:52:29 PM PDT 24 |
| Finished | Jun 13 01:53:25 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-12fa2794-7c12-4dc5-8bb7-b1e0e6d0f739 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925361401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.925361401 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3694043577 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4588000000 ps |
| CPU time | 22.96 seconds |
| Started | Jun 13 01:52:24 PM PDT 24 |
| Finished | Jun 13 01:53:10 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-6ba19591-9196-411c-a51b-33d6b22ffcd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694043577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3694043577 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2859924941 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14061600000 ps |
| CPU time | 58.74 seconds |
| Started | Jun 13 01:52:28 PM PDT 24 |
| Finished | Jun 13 01:54:24 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-53f7515f-cf77-44f6-9591-6d5974254090 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859924941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2859924941 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1624508409 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9600080000 ps |
| CPU time | 37.88 seconds |
| Started | Jun 13 01:52:24 PM PDT 24 |
| Finished | Jun 13 01:53:37 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-b3d14ea2-0a63-4d8a-9291-9872868dd8c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624508409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1624508409 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.469087755 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9736480000 ps |
| CPU time | 42.08 seconds |
| Started | Jun 13 01:52:26 PM PDT 24 |
| Finished | Jun 13 01:53:56 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-7d200bf0-7840-4df2-abf7-2fdf55a3fd23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=469087755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.469087755 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1858022306 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14841560000 ps |
| CPU time | 57.08 seconds |
| Started | Jun 13 01:52:24 PM PDT 24 |
| Finished | Jun 13 01:54:13 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-b3c10018-a3dc-456c-8546-5799d8a9b854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858022306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1858022306 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.182149057 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9127020000 ps |
| CPU time | 34.74 seconds |
| Started | Jun 13 01:52:26 PM PDT 24 |
| Finished | Jun 13 01:53:38 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-eb77a024-a445-4be3-a09e-a8d347b76250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182149057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.182149057 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1575748498 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5013320000 ps |
| CPU time | 23.03 seconds |
| Started | Jun 13 01:52:26 PM PDT 24 |
| Finished | Jun 13 01:53:14 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-2b1effd4-cdab-44e5-be07-c8c9971363b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575748498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1575748498 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.4036226857 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10251080000 ps |
| CPU time | 30.52 seconds |
| Started | Jun 13 01:52:21 PM PDT 24 |
| Finished | Jun 13 01:53:20 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-bbcdbd34-c00b-43cf-8691-e7b3bb7a4745 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036226857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.4036226857 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.469024769 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10263480000 ps |
| CPU time | 36.82 seconds |
| Started | Jun 13 01:52:21 PM PDT 24 |
| Finished | Jun 13 01:53:32 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-bc2efdb3-ca66-4319-a063-5058ebfb6daa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=469024769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.469024769 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.425647355 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8817020000 ps |
| CPU time | 34.68 seconds |
| Started | Jun 13 01:52:24 PM PDT 24 |
| Finished | Jun 13 01:53:31 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-849facb5-ab1a-4ac6-99e9-ce8de7c02fb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425647355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.425647355 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1252189833 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8655820000 ps |
| CPU time | 33.34 seconds |
| Started | Jun 13 01:52:20 PM PDT 24 |
| Finished | Jun 13 01:53:25 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-cb23d342-140b-4aea-9fda-93ec4e9c2922 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252189833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1252189833 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.397236714 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14198000000 ps |
| CPU time | 59.09 seconds |
| Started | Jun 13 01:52:20 PM PDT 24 |
| Finished | Jun 13 01:54:16 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-e4aa5e6d-0533-426c-af22-468d35eb11a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397236714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.397236714 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |