| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.2804936569 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.229572321 |
| /workspace/coverage/default/1.prim_present_test.2935220563 |
| /workspace/coverage/default/10.prim_present_test.2373069835 |
| /workspace/coverage/default/12.prim_present_test.935379167 |
| /workspace/coverage/default/13.prim_present_test.3253980544 |
| /workspace/coverage/default/14.prim_present_test.2285924215 |
| /workspace/coverage/default/15.prim_present_test.3997925257 |
| /workspace/coverage/default/16.prim_present_test.23514294 |
| /workspace/coverage/default/17.prim_present_test.177437933 |
| /workspace/coverage/default/18.prim_present_test.2125518355 |
| /workspace/coverage/default/19.prim_present_test.4047164325 |
| /workspace/coverage/default/2.prim_present_test.920430689 |
| /workspace/coverage/default/20.prim_present_test.1636402250 |
| /workspace/coverage/default/21.prim_present_test.4281869665 |
| /workspace/coverage/default/22.prim_present_test.2482000239 |
| /workspace/coverage/default/23.prim_present_test.3541795554 |
| /workspace/coverage/default/24.prim_present_test.1001721295 |
| /workspace/coverage/default/25.prim_present_test.802200261 |
| /workspace/coverage/default/26.prim_present_test.2897147984 |
| /workspace/coverage/default/27.prim_present_test.1351912552 |
| /workspace/coverage/default/28.prim_present_test.2083298148 |
| /workspace/coverage/default/29.prim_present_test.4006345553 |
| /workspace/coverage/default/3.prim_present_test.3467856683 |
| /workspace/coverage/default/30.prim_present_test.720198000 |
| /workspace/coverage/default/31.prim_present_test.70403530 |
| /workspace/coverage/default/32.prim_present_test.1296146547 |
| /workspace/coverage/default/33.prim_present_test.3920635589 |
| /workspace/coverage/default/34.prim_present_test.539979119 |
| /workspace/coverage/default/35.prim_present_test.757812335 |
| /workspace/coverage/default/36.prim_present_test.1229856991 |
| /workspace/coverage/default/37.prim_present_test.1380732167 |
| /workspace/coverage/default/38.prim_present_test.1004634657 |
| /workspace/coverage/default/39.prim_present_test.2152160363 |
| /workspace/coverage/default/4.prim_present_test.2237492010 |
| /workspace/coverage/default/40.prim_present_test.3800473681 |
| /workspace/coverage/default/41.prim_present_test.1626214092 |
| /workspace/coverage/default/42.prim_present_test.844600152 |
| /workspace/coverage/default/43.prim_present_test.1488834182 |
| /workspace/coverage/default/44.prim_present_test.2318198818 |
| /workspace/coverage/default/45.prim_present_test.3815918459 |
| /workspace/coverage/default/46.prim_present_test.734881333 |
| /workspace/coverage/default/47.prim_present_test.2985462250 |
| /workspace/coverage/default/48.prim_present_test.4131606477 |
| /workspace/coverage/default/49.prim_present_test.2320764838 |
| /workspace/coverage/default/5.prim_present_test.1835713104 |
| /workspace/coverage/default/6.prim_present_test.496738611 |
| /workspace/coverage/default/7.prim_present_test.3166108434 |
| /workspace/coverage/default/8.prim_present_test.1213596702 |
| /workspace/coverage/default/9.prim_present_test.2436873368 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_present_test.496738611 | Jun 21 04:26:22 PM PDT 24 | Jun 21 04:27:41 PM PDT 24 | 13622640000 ps | ||
| T2 | /workspace/coverage/default/24.prim_present_test.1001721295 | Jun 21 04:21:55 PM PDT 24 | Jun 21 04:22:42 PM PDT 24 | 6430020000 ps | ||
| T3 | /workspace/coverage/default/43.prim_present_test.1488834182 | Jun 21 04:26:18 PM PDT 24 | Jun 21 04:27:21 PM PDT 24 | 11757680000 ps | ||
| T4 | /workspace/coverage/default/27.prim_present_test.1351912552 | Jun 21 04:22:25 PM PDT 24 | Jun 21 04:23:30 PM PDT 24 | 10443280000 ps | ||
| T5 | /workspace/coverage/default/29.prim_present_test.4006345553 | Jun 21 04:22:49 PM PDT 24 | Jun 21 04:23:46 PM PDT 24 | 8234840000 ps | ||
| T6 | /workspace/coverage/default/37.prim_present_test.1380732167 | Jun 21 04:27:39 PM PDT 24 | Jun 21 04:28:50 PM PDT 24 | 11042820000 ps | ||
| T7 | /workspace/coverage/default/9.prim_present_test.2436873368 | Jun 21 04:22:56 PM PDT 24 | Jun 21 04:24:08 PM PDT 24 | 11553080000 ps | ||
| T8 | /workspace/coverage/default/33.prim_present_test.3920635589 | Jun 21 04:27:39 PM PDT 24 | Jun 21 04:29:14 PM PDT 24 | 15114360000 ps | ||
| T9 | /workspace/coverage/default/35.prim_present_test.757812335 | Jun 21 04:22:25 PM PDT 24 | Jun 21 04:24:02 PM PDT 24 | 14157080000 ps | ||
| T10 | /workspace/coverage/default/11.prim_present_test.2804936569 | Jun 21 04:22:00 PM PDT 24 | Jun 21 04:23:10 PM PDT 24 | 10389960000 ps | ||
| T11 | /workspace/coverage/default/14.prim_present_test.2285924215 | Jun 21 04:21:03 PM PDT 24 | Jun 21 04:21:30 PM PDT 24 | 3842140000 ps | ||
| T12 | /workspace/coverage/default/0.prim_present_test.229572321 | Jun 21 04:21:43 PM PDT 24 | Jun 21 04:22:56 PM PDT 24 | 10974620000 ps | ||
| T13 | /workspace/coverage/default/30.prim_present_test.720198000 | Jun 21 04:25:04 PM PDT 24 | Jun 21 04:26:31 PM PDT 24 | 11579740000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.1626214092 | Jun 21 04:25:57 PM PDT 24 | Jun 21 04:26:42 PM PDT 24 | 6763580000 ps | ||
| T15 | /workspace/coverage/default/20.prim_present_test.1636402250 | Jun 21 04:21:46 PM PDT 24 | Jun 21 04:22:31 PM PDT 24 | 7909960000 ps | ||
| T16 | /workspace/coverage/default/38.prim_present_test.1004634657 | Jun 21 04:22:44 PM PDT 24 | Jun 21 04:24:15 PM PDT 24 | 13778880000 ps | ||
| T17 | /workspace/coverage/default/40.prim_present_test.3800473681 | Jun 21 04:25:04 PM PDT 24 | Jun 21 04:25:50 PM PDT 24 | 6418860000 ps | ||
| T18 | /workspace/coverage/default/28.prim_present_test.2083298148 | Jun 21 04:27:48 PM PDT 24 | Jun 21 04:28:38 PM PDT 24 | 9141900000 ps | ||
| T19 | /workspace/coverage/default/17.prim_present_test.177437933 | Jun 21 04:22:01 PM PDT 24 | Jun 21 04:23:33 PM PDT 24 | 13607140000 ps | ||
| T20 | /workspace/coverage/default/19.prim_present_test.4047164325 | Jun 21 04:22:01 PM PDT 24 | Jun 21 04:23:42 PM PDT 24 | 15457220000 ps | ||
| T21 | /workspace/coverage/default/39.prim_present_test.2152160363 | Jun 21 04:22:40 PM PDT 24 | Jun 21 04:23:54 PM PDT 24 | 12098680000 ps | ||
| T22 | /workspace/coverage/default/49.prim_present_test.2320764838 | Jun 21 04:22:10 PM PDT 24 | Jun 21 04:22:34 PM PDT 24 | 3201060000 ps | ||
| T23 | /workspace/coverage/default/18.prim_present_test.2125518355 | Jun 21 04:21:32 PM PDT 24 | Jun 21 04:22:51 PM PDT 24 | 11099860000 ps | ||
| T24 | /workspace/coverage/default/47.prim_present_test.2985462250 | Jun 21 04:22:49 PM PDT 24 | Jun 21 04:24:31 PM PDT 24 | 14221560000 ps | ||
| T25 | /workspace/coverage/default/21.prim_present_test.4281869665 | Jun 21 04:23:36 PM PDT 24 | Jun 21 04:24:08 PM PDT 24 | 5041220000 ps | ||
| T26 | /workspace/coverage/default/26.prim_present_test.2897147984 | Jun 21 04:21:50 PM PDT 24 | Jun 21 04:22:40 PM PDT 24 | 8529340000 ps | ||
| T27 | /workspace/coverage/default/22.prim_present_test.2482000239 | Jun 21 04:23:36 PM PDT 24 | Jun 21 04:24:40 PM PDT 24 | 9099120000 ps | ||
| T28 | /workspace/coverage/default/5.prim_present_test.1835713104 | Jun 21 04:21:47 PM PDT 24 | Jun 21 04:22:52 PM PDT 24 | 9124540000 ps | ||
| T29 | /workspace/coverage/default/23.prim_present_test.3541795554 | Jun 21 04:23:36 PM PDT 24 | Jun 21 04:25:01 PM PDT 24 | 13026820000 ps | ||
| T30 | /workspace/coverage/default/12.prim_present_test.935379167 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:22:11 PM PDT 24 | 11776280000 ps | ||
| T31 | /workspace/coverage/default/36.prim_present_test.1229856991 | Jun 21 04:27:55 PM PDT 24 | Jun 21 04:29:13 PM PDT 24 | 12302660000 ps | ||
| T32 | /workspace/coverage/default/48.prim_present_test.4131606477 | Jun 21 04:26:27 PM PDT 24 | Jun 21 04:27:26 PM PDT 24 | 8735800000 ps | ||
| T33 | /workspace/coverage/default/32.prim_present_test.1296146547 | Jun 21 04:21:25 PM PDT 24 | Jun 21 04:21:50 PM PDT 24 | 3537100000 ps | ||
| T34 | /workspace/coverage/default/15.prim_present_test.3997925257 | Jun 21 04:22:01 PM PDT 24 | Jun 21 04:22:36 PM PDT 24 | 5903020000 ps | ||
| T35 | /workspace/coverage/default/25.prim_present_test.802200261 | Jun 21 04:22:10 PM PDT 24 | Jun 21 04:22:34 PM PDT 24 | 3202920000 ps | ||
| T36 | /workspace/coverage/default/16.prim_present_test.23514294 | Jun 21 04:22:16 PM PDT 24 | Jun 21 04:23:16 PM PDT 24 | 8708520000 ps | ||
| T37 | /workspace/coverage/default/4.prim_present_test.2237492010 | Jun 21 04:23:05 PM PDT 24 | Jun 21 04:23:43 PM PDT 24 | 6001600000 ps | ||
| T38 | /workspace/coverage/default/2.prim_present_test.920430689 | Jun 21 04:21:52 PM PDT 24 | Jun 21 04:22:16 PM PDT 24 | 3526560000 ps | ||
| T39 | /workspace/coverage/default/1.prim_present_test.2935220563 | Jun 21 04:24:31 PM PDT 24 | Jun 21 04:25:58 PM PDT 24 | 12098680000 ps | ||
| T40 | /workspace/coverage/default/46.prim_present_test.734881333 | Jun 21 04:21:52 PM PDT 24 | Jun 21 04:22:33 PM PDT 24 | 6271300000 ps | ||
| T41 | /workspace/coverage/default/3.prim_present_test.3467856683 | Jun 21 04:26:37 PM PDT 24 | Jun 21 04:27:28 PM PDT 24 | 7852300000 ps | ||
| T42 | /workspace/coverage/default/44.prim_present_test.2318198818 | Jun 21 04:22:14 PM PDT 24 | Jun 21 04:23:53 PM PDT 24 | 14395780000 ps | ||
| T43 | /workspace/coverage/default/10.prim_present_test.2373069835 | Jun 21 04:22:16 PM PDT 24 | Jun 21 04:23:20 PM PDT 24 | 9267140000 ps | ||
| T44 | /workspace/coverage/default/34.prim_present_test.539979119 | Jun 21 04:26:28 PM PDT 24 | Jun 21 04:27:32 PM PDT 24 | 9940460000 ps | ||
| T45 | /workspace/coverage/default/31.prim_present_test.70403530 | Jun 21 04:24:26 PM PDT 24 | Jun 21 04:25:15 PM PDT 24 | 7136820000 ps | ||
| T46 | /workspace/coverage/default/7.prim_present_test.3166108434 | Jun 21 04:24:31 PM PDT 24 | Jun 21 04:26:14 PM PDT 24 | 14504900000 ps | ||
| T47 | /workspace/coverage/default/42.prim_present_test.844600152 | Jun 21 04:21:43 PM PDT 24 | Jun 21 04:23:21 PM PDT 24 | 15033140000 ps | ||
| T48 | /workspace/coverage/default/8.prim_present_test.1213596702 | Jun 21 04:25:44 PM PDT 24 | Jun 21 04:26:49 PM PDT 24 | 8764940000 ps | ||
| T49 | /workspace/coverage/default/13.prim_present_test.3253980544 | Jun 21 04:21:52 PM PDT 24 | Jun 21 04:22:43 PM PDT 24 | 8051320000 ps | ||
| T50 | /workspace/coverage/default/45.prim_present_test.3815918459 | Jun 21 04:21:38 PM PDT 24 | Jun 21 04:22:02 PM PDT 24 | 3848340000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.2804936569 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10389960000 ps |
| CPU time | 37.09 seconds |
| Started | Jun 21 04:22:00 PM PDT 24 |
| Finished | Jun 21 04:23:10 PM PDT 24 |
| Peak memory | 143852 kb |
| Host | smart-2d713e5f-1ef9-49f2-9ba8-2c0113fd451c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804936569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2804936569 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.229572321 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10974620000 ps |
| CPU time | 39.25 seconds |
| Started | Jun 21 04:21:43 PM PDT 24 |
| Finished | Jun 21 04:22:56 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c29930c8-eba4-4152-9c1c-ca2f0d986c0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229572321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.229572321 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2935220563 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12098680000 ps |
| CPU time | 45.94 seconds |
| Started | Jun 21 04:24:31 PM PDT 24 |
| Finished | Jun 21 04:25:58 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-1ba6cfac-e051-4002-b240-eeec48769fae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935220563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2935220563 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2373069835 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 9267140000 ps |
| CPU time | 33.53 seconds |
| Started | Jun 21 04:22:16 PM PDT 24 |
| Finished | Jun 21 04:23:20 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-1a374034-51d0-4aae-9156-5e1191e81189 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373069835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2373069835 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.935379167 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11776280000 ps |
| CPU time | 41.38 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:22:11 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-fcb1d450-1707-4e20-b5b7-d19e02fdf679 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935379167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.935379167 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3253980544 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8051320000 ps |
| CPU time | 27.37 seconds |
| Started | Jun 21 04:21:52 PM PDT 24 |
| Finished | Jun 21 04:22:43 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-5a473217-e7ca-4b0a-be61-fd56e71a561e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253980544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3253980544 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2285924215 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3842140000 ps |
| CPU time | 14 seconds |
| Started | Jun 21 04:21:03 PM PDT 24 |
| Finished | Jun 21 04:21:30 PM PDT 24 |
| Peak memory | 144760 kb |
| Host | smart-b3c74fc6-9364-4500-8290-53095f954738 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285924215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2285924215 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3997925257 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5903020000 ps |
| CPU time | 18.69 seconds |
| Started | Jun 21 04:22:01 PM PDT 24 |
| Finished | Jun 21 04:22:36 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-fdf5db64-edc6-4e58-923b-728b7d1f3a9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997925257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3997925257 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.23514294 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8708520000 ps |
| CPU time | 31.27 seconds |
| Started | Jun 21 04:22:16 PM PDT 24 |
| Finished | Jun 21 04:23:16 PM PDT 24 |
| Peak memory | 144692 kb |
| Host | smart-4f29165b-034a-4eaa-8507-6d68ab34bf57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23514294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.23514294 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.177437933 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13607140000 ps |
| CPU time | 48.78 seconds |
| Started | Jun 21 04:22:01 PM PDT 24 |
| Finished | Jun 21 04:23:33 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-a646a747-4e63-40e2-a2c8-4577c86f0a09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177437933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.177437933 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2125518355 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11099860000 ps |
| CPU time | 41.56 seconds |
| Started | Jun 21 04:21:32 PM PDT 24 |
| Finished | Jun 21 04:22:51 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-d15b7b47-1dbb-4fc8-9f68-2ac38ec57863 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125518355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2125518355 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.4047164325 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 15457220000 ps |
| CPU time | 54.74 seconds |
| Started | Jun 21 04:22:01 PM PDT 24 |
| Finished | Jun 21 04:23:42 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-d22e8478-ac7f-4f71-8243-8e617c50a4b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047164325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.4047164325 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.920430689 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3526560000 ps |
| CPU time | 12.85 seconds |
| Started | Jun 21 04:21:52 PM PDT 24 |
| Finished | Jun 21 04:22:16 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-7db389e0-8764-46ef-8149-8048ae3aa2ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920430689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.920430689 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1636402250 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7909960000 ps |
| CPU time | 24.89 seconds |
| Started | Jun 21 04:21:46 PM PDT 24 |
| Finished | Jun 21 04:22:31 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-af6a55fc-4a13-42d9-86ff-b219620261d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636402250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1636402250 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4281869665 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5041220000 ps |
| CPU time | 17.05 seconds |
| Started | Jun 21 04:23:36 PM PDT 24 |
| Finished | Jun 21 04:24:08 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-d315f215-e81a-47db-a585-e842c90a2543 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281869665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4281869665 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2482000239 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9099120000 ps |
| CPU time | 33.68 seconds |
| Started | Jun 21 04:23:36 PM PDT 24 |
| Finished | Jun 21 04:24:40 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-8d384622-8a42-40d3-b505-8fb48848da74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482000239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2482000239 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3541795554 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13026820000 ps |
| CPU time | 45.54 seconds |
| Started | Jun 21 04:23:36 PM PDT 24 |
| Finished | Jun 21 04:25:01 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-d5057868-82dd-481c-b76b-487e9f497245 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541795554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3541795554 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1001721295 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6430020000 ps |
| CPU time | 24.55 seconds |
| Started | Jun 21 04:21:55 PM PDT 24 |
| Finished | Jun 21 04:22:42 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-0ca8a3c0-3e73-4739-bef2-c835c5d07d19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001721295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1001721295 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.802200261 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3202920000 ps |
| CPU time | 12.67 seconds |
| Started | Jun 21 04:22:10 PM PDT 24 |
| Finished | Jun 21 04:22:34 PM PDT 24 |
| Peak memory | 144716 kb |
| Host | smart-5043efa5-8dc5-4cfb-b993-2714d505c156 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802200261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.802200261 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2897147984 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8529340000 ps |
| CPU time | 26.99 seconds |
| Started | Jun 21 04:21:50 PM PDT 24 |
| Finished | Jun 21 04:22:40 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-bf2b6e8d-344f-43f2-9d0c-e02b34d85eaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897147984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2897147984 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1351912552 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10443280000 ps |
| CPU time | 35.77 seconds |
| Started | Jun 21 04:22:25 PM PDT 24 |
| Finished | Jun 21 04:23:30 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-2fbca948-cd64-4830-af6b-7f42a1a229b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1351912552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1351912552 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2083298148 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9141900000 ps |
| CPU time | 26.38 seconds |
| Started | Jun 21 04:27:48 PM PDT 24 |
| Finished | Jun 21 04:28:38 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-360b29d5-629c-4dce-9fc8-ed1a9f82af40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083298148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2083298148 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4006345553 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8234840000 ps |
| CPU time | 30.02 seconds |
| Started | Jun 21 04:22:49 PM PDT 24 |
| Finished | Jun 21 04:23:46 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-462a3289-9e97-4459-a492-7f55e615e417 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006345553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4006345553 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3467856683 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 7852300000 ps |
| CPU time | 27.48 seconds |
| Started | Jun 21 04:26:37 PM PDT 24 |
| Finished | Jun 21 04:27:28 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-cebc9f5c-75a3-41e8-a88c-9ef1d643b1f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467856683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3467856683 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.720198000 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11579740000 ps |
| CPU time | 45.21 seconds |
| Started | Jun 21 04:25:04 PM PDT 24 |
| Finished | Jun 21 04:26:31 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-b09d9162-f625-4fa5-8246-7953b71b8df0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720198000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.720198000 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.70403530 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7136820000 ps |
| CPU time | 25.8 seconds |
| Started | Jun 21 04:24:26 PM PDT 24 |
| Finished | Jun 21 04:25:15 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-1557f18a-b0a8-458e-b3c3-ad3fea3a20fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70403530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.70403530 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1296146547 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3537100000 ps |
| CPU time | 13.27 seconds |
| Started | Jun 21 04:21:25 PM PDT 24 |
| Finished | Jun 21 04:21:50 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-835755c6-0e2b-48d5-9546-159f739b5600 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296146547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1296146547 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3920635589 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 15114360000 ps |
| CPU time | 50.96 seconds |
| Started | Jun 21 04:27:39 PM PDT 24 |
| Finished | Jun 21 04:29:14 PM PDT 24 |
| Peak memory | 143560 kb |
| Host | smart-8af87697-58d6-4e39-a740-299d9576907e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920635589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3920635589 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.539979119 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 9940460000 ps |
| CPU time | 33.91 seconds |
| Started | Jun 21 04:26:28 PM PDT 24 |
| Finished | Jun 21 04:27:32 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-4ac3ab65-171a-4231-a6bd-e219e2385693 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539979119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.539979119 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.757812335 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 14157080000 ps |
| CPU time | 50.82 seconds |
| Started | Jun 21 04:22:25 PM PDT 24 |
| Finished | Jun 21 04:24:02 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-2bd6cf98-648f-4e99-a5e3-63253470c6ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=757812335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.757812335 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1229856991 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12302660000 ps |
| CPU time | 41.16 seconds |
| Started | Jun 21 04:27:55 PM PDT 24 |
| Finished | Jun 21 04:29:13 PM PDT 24 |
| Peak memory | 144656 kb |
| Host | smart-ea34b5b7-85a4-4c26-a04d-cfffd73e98a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229856991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1229856991 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1380732167 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11042820000 ps |
| CPU time | 37.72 seconds |
| Started | Jun 21 04:27:39 PM PDT 24 |
| Finished | Jun 21 04:28:50 PM PDT 24 |
| Peak memory | 143896 kb |
| Host | smart-3a7db06d-4c71-44d4-93a9-bfd8f16f7b1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380732167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1380732167 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1004634657 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13778880000 ps |
| CPU time | 47.91 seconds |
| Started | Jun 21 04:22:44 PM PDT 24 |
| Finished | Jun 21 04:24:15 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-fa2c8489-97ef-44bd-8b85-147ffa618fa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004634657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1004634657 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2152160363 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12098680000 ps |
| CPU time | 40.53 seconds |
| Started | Jun 21 04:22:40 PM PDT 24 |
| Finished | Jun 21 04:23:54 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-0a492167-1916-4493-8ab1-a7ffdac798c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2152160363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2152160363 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2237492010 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6001600000 ps |
| CPU time | 20.59 seconds |
| Started | Jun 21 04:23:05 PM PDT 24 |
| Finished | Jun 21 04:23:43 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-3129f88b-7d7a-4c13-9954-42b34c2680b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237492010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2237492010 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3800473681 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6418860000 ps |
| CPU time | 23.84 seconds |
| Started | Jun 21 04:25:04 PM PDT 24 |
| Finished | Jun 21 04:25:50 PM PDT 24 |
| Peak memory | 143964 kb |
| Host | smart-9e2c1932-ce2b-4484-ac66-b47470e9cbe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800473681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3800473681 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1626214092 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6763580000 ps |
| CPU time | 23.93 seconds |
| Started | Jun 21 04:25:57 PM PDT 24 |
| Finished | Jun 21 04:26:42 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-ff1c1d52-3582-4a07-a26a-b0115f524165 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626214092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1626214092 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.844600152 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15033140000 ps |
| CPU time | 52.46 seconds |
| Started | Jun 21 04:21:43 PM PDT 24 |
| Finished | Jun 21 04:23:21 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-b70bfd50-9e53-4ddc-88d7-267abb178177 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844600152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.844600152 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1488834182 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11757680000 ps |
| CPU time | 33.68 seconds |
| Started | Jun 21 04:26:18 PM PDT 24 |
| Finished | Jun 21 04:27:21 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-a7e85a7b-d7c5-4b76-806a-a789f6267afc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488834182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1488834182 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2318198818 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14395780000 ps |
| CPU time | 52.28 seconds |
| Started | Jun 21 04:22:14 PM PDT 24 |
| Finished | Jun 21 04:23:53 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-3b094a08-31cf-4425-9981-44f3c664007a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318198818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2318198818 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3815918459 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3848340000 ps |
| CPU time | 12.88 seconds |
| Started | Jun 21 04:21:38 PM PDT 24 |
| Finished | Jun 21 04:22:02 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-9819c33f-77c7-4b53-af70-f57837544b0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815918459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3815918459 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.734881333 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6271300000 ps |
| CPU time | 22.19 seconds |
| Started | Jun 21 04:21:52 PM PDT 24 |
| Finished | Jun 21 04:22:33 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-cb8cfd2c-4f7e-4b29-b3b8-c70d69c4c243 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=734881333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.734881333 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2985462250 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 14221560000 ps |
| CPU time | 53.63 seconds |
| Started | Jun 21 04:22:49 PM PDT 24 |
| Finished | Jun 21 04:24:31 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-31853feb-63bf-4791-9482-129577948d89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985462250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2985462250 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4131606477 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8735800000 ps |
| CPU time | 30.44 seconds |
| Started | Jun 21 04:26:27 PM PDT 24 |
| Finished | Jun 21 04:27:26 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-b7c782f8-e794-4fac-8008-24c56723f042 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131606477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4131606477 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2320764838 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3201060000 ps |
| CPU time | 12.74 seconds |
| Started | Jun 21 04:22:10 PM PDT 24 |
| Finished | Jun 21 04:22:34 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-e2a68a2a-b945-481e-bced-aa588effb540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320764838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2320764838 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1835713104 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9124540000 ps |
| CPU time | 34.43 seconds |
| Started | Jun 21 04:21:47 PM PDT 24 |
| Finished | Jun 21 04:22:52 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-a9a86b07-99b7-48e8-a798-73e10553c696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835713104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1835713104 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.496738611 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13622640000 ps |
| CPU time | 43.05 seconds |
| Started | Jun 21 04:26:22 PM PDT 24 |
| Finished | Jun 21 04:27:41 PM PDT 24 |
| Peak memory | 144020 kb |
| Host | smart-afffba2d-f10f-4639-8be2-bea4c4505fa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496738611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.496738611 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3166108434 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14504900000 ps |
| CPU time | 54.46 seconds |
| Started | Jun 21 04:24:31 PM PDT 24 |
| Finished | Jun 21 04:26:14 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-91a1189e-d610-4765-baba-4647d0f53b43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166108434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3166108434 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1213596702 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8764940000 ps |
| CPU time | 34.24 seconds |
| Started | Jun 21 04:25:44 PM PDT 24 |
| Finished | Jun 21 04:26:49 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-2ac7db77-b06e-404e-84b5-cc5d2df8b083 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213596702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1213596702 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2436873368 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11553080000 ps |
| CPU time | 39.01 seconds |
| Started | Jun 21 04:22:56 PM PDT 24 |
| Finished | Jun 21 04:24:08 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-ba1debf1-3a5f-4ebe-ae47-babaf2df523c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436873368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2436873368 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |