| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.1771951256 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.649570024 |
| /workspace/coverage/default/1.prim_present_test.277588945 |
| /workspace/coverage/default/10.prim_present_test.2234086206 |
| /workspace/coverage/default/12.prim_present_test.2415666414 |
| /workspace/coverage/default/13.prim_present_test.2939570518 |
| /workspace/coverage/default/14.prim_present_test.4058470612 |
| /workspace/coverage/default/15.prim_present_test.4019541541 |
| /workspace/coverage/default/16.prim_present_test.3552240586 |
| /workspace/coverage/default/17.prim_present_test.2154188952 |
| /workspace/coverage/default/18.prim_present_test.1842543637 |
| /workspace/coverage/default/19.prim_present_test.3818838331 |
| /workspace/coverage/default/2.prim_present_test.1110514206 |
| /workspace/coverage/default/20.prim_present_test.2658212200 |
| /workspace/coverage/default/21.prim_present_test.406071441 |
| /workspace/coverage/default/22.prim_present_test.534955975 |
| /workspace/coverage/default/23.prim_present_test.1824267034 |
| /workspace/coverage/default/24.prim_present_test.2001671591 |
| /workspace/coverage/default/25.prim_present_test.1722692710 |
| /workspace/coverage/default/26.prim_present_test.1989136698 |
| /workspace/coverage/default/27.prim_present_test.1823549280 |
| /workspace/coverage/default/28.prim_present_test.3883289523 |
| /workspace/coverage/default/29.prim_present_test.1152483703 |
| /workspace/coverage/default/3.prim_present_test.3252057617 |
| /workspace/coverage/default/30.prim_present_test.4114328487 |
| /workspace/coverage/default/31.prim_present_test.1789795240 |
| /workspace/coverage/default/32.prim_present_test.1825902603 |
| /workspace/coverage/default/33.prim_present_test.1072642092 |
| /workspace/coverage/default/34.prim_present_test.2174684959 |
| /workspace/coverage/default/35.prim_present_test.3686332759 |
| /workspace/coverage/default/36.prim_present_test.3517114257 |
| /workspace/coverage/default/37.prim_present_test.2411159894 |
| /workspace/coverage/default/38.prim_present_test.416811307 |
| /workspace/coverage/default/39.prim_present_test.3706483272 |
| /workspace/coverage/default/4.prim_present_test.2252171094 |
| /workspace/coverage/default/40.prim_present_test.139118435 |
| /workspace/coverage/default/41.prim_present_test.82746583 |
| /workspace/coverage/default/42.prim_present_test.1998289768 |
| /workspace/coverage/default/43.prim_present_test.2686087809 |
| /workspace/coverage/default/44.prim_present_test.1517339382 |
| /workspace/coverage/default/45.prim_present_test.3356105983 |
| /workspace/coverage/default/46.prim_present_test.3727702264 |
| /workspace/coverage/default/47.prim_present_test.2221626630 |
| /workspace/coverage/default/48.prim_present_test.3150603891 |
| /workspace/coverage/default/49.prim_present_test.3241554124 |
| /workspace/coverage/default/5.prim_present_test.2804061815 |
| /workspace/coverage/default/6.prim_present_test.108885609 |
| /workspace/coverage/default/7.prim_present_test.3321422844 |
| /workspace/coverage/default/8.prim_present_test.3057938202 |
| /workspace/coverage/default/9.prim_present_test.523960550 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_present_test.3321422844 | Jun 22 04:40:01 PM PDT 24 | Jun 22 04:40:31 PM PDT 24 | 3489360000 ps | ||
| T2 | /workspace/coverage/default/21.prim_present_test.406071441 | Jun 22 04:40:02 PM PDT 24 | Jun 22 04:40:54 PM PDT 24 | 6698480000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.2939570518 | Jun 22 04:40:02 PM PDT 24 | Jun 22 04:41:02 PM PDT 24 | 9578380000 ps | ||
| T4 | /workspace/coverage/default/2.prim_present_test.1110514206 | Jun 22 04:40:02 PM PDT 24 | Jun 22 04:41:01 PM PDT 24 | 6827440000 ps | ||
| T5 | /workspace/coverage/default/17.prim_present_test.2154188952 | Jun 22 04:40:12 PM PDT 24 | Jun 22 04:41:02 PM PDT 24 | 7503240000 ps | ||
| T6 | /workspace/coverage/default/30.prim_present_test.4114328487 | Jun 22 04:40:16 PM PDT 24 | Jun 22 04:40:54 PM PDT 24 | 4843440000 ps | ||
| T7 | /workspace/coverage/default/16.prim_present_test.3552240586 | Jun 22 04:40:17 PM PDT 24 | Jun 22 04:40:47 PM PDT 24 | 3955600000 ps | ||
| T8 | /workspace/coverage/default/24.prim_present_test.2001671591 | Jun 22 04:40:14 PM PDT 24 | Jun 22 04:41:20 PM PDT 24 | 10283320000 ps | ||
| T9 | /workspace/coverage/default/11.prim_present_test.1771951256 | Jun 22 04:40:15 PM PDT 24 | Jun 22 04:40:41 PM PDT 24 | 4234600000 ps | ||
| T10 | /workspace/coverage/default/42.prim_present_test.1998289768 | Jun 22 04:40:17 PM PDT 24 | Jun 22 04:40:57 PM PDT 24 | 7272600000 ps | ||
| T11 | /workspace/coverage/default/46.prim_present_test.3727702264 | Jun 22 04:39:58 PM PDT 24 | Jun 22 04:40:57 PM PDT 24 | 9153680000 ps | ||
| T12 | /workspace/coverage/default/10.prim_present_test.2234086206 | Jun 22 04:39:53 PM PDT 24 | Jun 22 04:41:05 PM PDT 24 | 8451840000 ps | ||
| T13 | /workspace/coverage/default/31.prim_present_test.1789795240 | Jun 22 04:40:57 PM PDT 24 | Jun 22 04:41:38 PM PDT 24 | 5652540000 ps | ||
| T14 | /workspace/coverage/default/4.prim_present_test.2252171094 | Jun 22 04:39:59 PM PDT 24 | Jun 22 04:41:21 PM PDT 24 | 13258080000 ps | ||
| T15 | /workspace/coverage/default/49.prim_present_test.3241554124 | Jun 22 04:40:02 PM PDT 24 | Jun 22 04:40:58 PM PDT 24 | 7000420000 ps | ||
| T16 | /workspace/coverage/default/28.prim_present_test.3883289523 | Jun 22 04:40:04 PM PDT 24 | Jun 22 04:40:41 PM PDT 24 | 4980460000 ps | ||
| T17 | /workspace/coverage/default/8.prim_present_test.3057938202 | Jun 22 04:40:06 PM PDT 24 | Jun 22 04:41:38 PM PDT 24 | 15385920000 ps | ||
| T18 | /workspace/coverage/default/34.prim_present_test.2174684959 | Jun 22 04:39:59 PM PDT 24 | Jun 22 04:41:36 PM PDT 24 | 13065260000 ps | ||
| T19 | /workspace/coverage/default/37.prim_present_test.2411159894 | Jun 22 04:40:01 PM PDT 24 | Jun 22 04:41:17 PM PDT 24 | 11925080000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.2415666414 | Jun 22 04:39:51 PM PDT 24 | Jun 22 04:40:22 PM PDT 24 | 4033100000 ps | ||
| T21 | /workspace/coverage/default/47.prim_present_test.2221626630 | Jun 22 04:40:22 PM PDT 24 | Jun 22 04:41:02 PM PDT 24 | 4188720000 ps | ||
| T22 | /workspace/coverage/default/32.prim_present_test.1825902603 | Jun 22 04:40:18 PM PDT 24 | Jun 22 04:41:47 PM PDT 24 | 14669200000 ps | ||
| T23 | /workspace/coverage/default/45.prim_present_test.3356105983 | Jun 22 04:40:11 PM PDT 24 | Jun 22 04:41:49 PM PDT 24 | 12653580000 ps | ||
| T24 | /workspace/coverage/default/29.prim_present_test.1152483703 | Jun 22 04:40:02 PM PDT 24 | Jun 22 04:41:14 PM PDT 24 | 10617500000 ps | ||
| T25 | /workspace/coverage/default/5.prim_present_test.2804061815 | Jun 22 04:40:01 PM PDT 24 | Jun 22 04:41:19 PM PDT 24 | 9729660000 ps | ||
| T26 | /workspace/coverage/default/25.prim_present_test.1722692710 | Jun 22 04:40:05 PM PDT 24 | Jun 22 04:41:10 PM PDT 24 | 9982620000 ps | ||
| T27 | /workspace/coverage/default/27.prim_present_test.1823549280 | Jun 22 04:40:04 PM PDT 24 | Jun 22 04:40:33 PM PDT 24 | 4020700000 ps | ||
| T28 | /workspace/coverage/default/9.prim_present_test.523960550 | Jun 22 04:39:57 PM PDT 24 | Jun 22 04:41:25 PM PDT 24 | 12212140000 ps | ||
| T29 | /workspace/coverage/default/39.prim_present_test.3706483272 | Jun 22 04:40:03 PM PDT 24 | Jun 22 04:41:26 PM PDT 24 | 11491080000 ps | ||
| T30 | /workspace/coverage/default/33.prim_present_test.1072642092 | Jun 22 04:40:07 PM PDT 24 | Jun 22 04:41:11 PM PDT 24 | 9875360000 ps | ||
| T31 | /workspace/coverage/default/41.prim_present_test.82746583 | Jun 22 04:40:05 PM PDT 24 | Jun 22 04:41:03 PM PDT 24 | 8928000000 ps | ||
| T32 | /workspace/coverage/default/26.prim_present_test.1989136698 | Jun 22 04:40:01 PM PDT 24 | Jun 22 04:41:34 PM PDT 24 | 12869340000 ps | ||
| T33 | /workspace/coverage/default/19.prim_present_test.3818838331 | Jun 22 04:39:57 PM PDT 24 | Jun 22 04:41:14 PM PDT 24 | 15346240000 ps | ||
| T34 | /workspace/coverage/default/48.prim_present_test.3150603891 | Jun 22 04:40:03 PM PDT 24 | Jun 22 04:41:23 PM PDT 24 | 10794820000 ps | ||
| T35 | /workspace/coverage/default/36.prim_present_test.3517114257 | Jun 22 04:40:01 PM PDT 24 | Jun 22 04:40:25 PM PDT 24 | 3623280000 ps | ||
| T36 | /workspace/coverage/default/40.prim_present_test.139118435 | Jun 22 04:40:12 PM PDT 24 | Jun 22 04:40:54 PM PDT 24 | 6005320000 ps | ||
| T37 | /workspace/coverage/default/1.prim_present_test.277588945 | Jun 22 04:40:00 PM PDT 24 | Jun 22 04:41:07 PM PDT 24 | 8502680000 ps | ||
| T38 | /workspace/coverage/default/44.prim_present_test.1517339382 | Jun 22 04:40:03 PM PDT 24 | Jun 22 04:41:08 PM PDT 24 | 9582720000 ps | ||
| T39 | /workspace/coverage/default/38.prim_present_test.416811307 | Jun 22 04:40:03 PM PDT 24 | Jun 22 04:41:51 PM PDT 24 | 15501860000 ps | ||
| T40 | /workspace/coverage/default/23.prim_present_test.1824267034 | Jun 22 04:40:00 PM PDT 24 | Jun 22 04:40:51 PM PDT 24 | 7671880000 ps | ||
| T41 | /workspace/coverage/default/14.prim_present_test.4058470612 | Jun 22 04:40:05 PM PDT 24 | Jun 22 04:41:50 PM PDT 24 | 14408800000 ps | ||
| T42 | /workspace/coverage/default/3.prim_present_test.3252057617 | Jun 22 04:40:04 PM PDT 24 | Jun 22 04:41:05 PM PDT 24 | 9643480000 ps | ||
| T43 | /workspace/coverage/default/15.prim_present_test.4019541541 | Jun 22 04:40:13 PM PDT 24 | Jun 22 04:41:57 PM PDT 24 | 15196820000 ps | ||
| T44 | /workspace/coverage/default/6.prim_present_test.108885609 | Jun 22 04:40:02 PM PDT 24 | Jun 22 04:40:56 PM PDT 24 | 6231000000 ps | ||
| T45 | /workspace/coverage/default/20.prim_present_test.2658212200 | Jun 22 04:40:08 PM PDT 24 | Jun 22 04:41:40 PM PDT 24 | 13707580000 ps | ||
| T46 | /workspace/coverage/default/22.prim_present_test.534955975 | Jun 22 04:40:07 PM PDT 24 | Jun 22 04:40:42 PM PDT 24 | 4702700000 ps | ||
| T47 | /workspace/coverage/default/0.prim_present_test.649570024 | Jun 22 04:40:02 PM PDT 24 | Jun 22 04:41:23 PM PDT 24 | 13172520000 ps | ||
| T48 | /workspace/coverage/default/35.prim_present_test.3686332759 | Jun 22 04:39:54 PM PDT 24 | Jun 22 04:41:18 PM PDT 24 | 11895320000 ps | ||
| T49 | /workspace/coverage/default/18.prim_present_test.1842543637 | Jun 22 04:39:50 PM PDT 24 | Jun 22 04:41:29 PM PDT 24 | 14634480000 ps | ||
| T50 | /workspace/coverage/default/43.prim_present_test.2686087809 | Jun 22 04:40:00 PM PDT 24 | Jun 22 04:41:30 PM PDT 24 | 14953160000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.1771951256 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4234600000 ps |
| CPU time | 13.41 seconds |
| Started | Jun 22 04:40:15 PM PDT 24 |
| Finished | Jun 22 04:40:41 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-bcc6cfcf-a5c9-4f5f-82b2-20ee1f546efa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771951256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1771951256 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.649570024 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13172520000 ps |
| CPU time | 42.42 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 04:41:23 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-c26a3417-ceb3-4f4d-a176-53e9d1461bc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649570024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.649570024 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.277588945 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8502680000 ps |
| CPU time | 33.43 seconds |
| Started | Jun 22 04:40:00 PM PDT 24 |
| Finished | Jun 22 04:41:07 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-b0ef0b87-7ea7-4d7a-895b-bf609ad69e97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=277588945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.277588945 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2234086206 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8451840000 ps |
| CPU time | 33.71 seconds |
| Started | Jun 22 04:39:53 PM PDT 24 |
| Finished | Jun 22 04:41:05 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-34e46b85-d8bf-40e6-88d1-060b398c468a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234086206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2234086206 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2415666414 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4033100000 ps |
| CPU time | 15.46 seconds |
| Started | Jun 22 04:39:51 PM PDT 24 |
| Finished | Jun 22 04:40:22 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-b7c74765-bf18-4e31-b22b-434ce7ed5630 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415666414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2415666414 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2939570518 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9578380000 ps |
| CPU time | 31.76 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 04:41:02 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-e65302c2-9948-405b-948c-1a32f3ba997c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939570518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2939570518 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4058470612 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14408800000 ps |
| CPU time | 53.74 seconds |
| Started | Jun 22 04:40:05 PM PDT 24 |
| Finished | Jun 22 04:41:50 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-2ad7c605-f856-4819-be3d-7d8a5895d4fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058470612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4058470612 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.4019541541 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15196820000 ps |
| CPU time | 54.71 seconds |
| Started | Jun 22 04:40:13 PM PDT 24 |
| Finished | Jun 22 04:41:57 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-81e76ce2-6ccc-4af4-a07a-86b5c90227b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019541541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4019541541 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3552240586 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3955600000 ps |
| CPU time | 15.45 seconds |
| Started | Jun 22 04:40:17 PM PDT 24 |
| Finished | Jun 22 04:40:47 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-7956d76a-efcf-431c-bd0a-b7f5ef4add80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552240586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3552240586 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2154188952 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7503240000 ps |
| CPU time | 26.34 seconds |
| Started | Jun 22 04:40:12 PM PDT 24 |
| Finished | Jun 22 04:41:02 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-dc27b847-cde9-4d9a-9f2e-5d05363e3694 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154188952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2154188952 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1842543637 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14634480000 ps |
| CPU time | 51.58 seconds |
| Started | Jun 22 04:39:50 PM PDT 24 |
| Finished | Jun 22 04:41:29 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-39d6cdbe-4c5a-4348-bcb3-04675e82c409 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842543637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1842543637 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3818838331 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 15346240000 ps |
| CPU time | 40.75 seconds |
| Started | Jun 22 04:39:57 PM PDT 24 |
| Finished | Jun 22 04:41:14 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-bbde5dd8-67ab-4f82-98f7-a70a14a522ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3818838331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3818838331 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1110514206 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6827440000 ps |
| CPU time | 29.17 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 04:41:01 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-b3190250-9551-45ca-bac4-4254254dda88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110514206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1110514206 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2658212200 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13707580000 ps |
| CPU time | 48.57 seconds |
| Started | Jun 22 04:40:08 PM PDT 24 |
| Finished | Jun 22 04:41:40 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-59e5562e-d376-4566-83bb-0ad2f3f3efc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658212200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2658212200 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.406071441 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6698480000 ps |
| CPU time | 26.39 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 04:40:54 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-a115821b-966f-431b-bd7e-2f62c74fab6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406071441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.406071441 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.534955975 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4702700000 ps |
| CPU time | 17.96 seconds |
| Started | Jun 22 04:40:07 PM PDT 24 |
| Finished | Jun 22 04:40:42 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-a80a8e08-0879-439e-b1d1-d9a4e63e15fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534955975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.534955975 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1824267034 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7671880000 ps |
| CPU time | 26.27 seconds |
| Started | Jun 22 04:40:00 PM PDT 24 |
| Finished | Jun 22 04:40:51 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-f1e16bd6-3b24-4e00-8c42-c74abe20d4b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824267034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1824267034 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2001671591 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10283320000 ps |
| CPU time | 35 seconds |
| Started | Jun 22 04:40:14 PM PDT 24 |
| Finished | Jun 22 04:41:20 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-63d2d29f-5ae8-4393-93e2-7681a34d4c04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001671591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2001671591 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1722692710 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9982620000 ps |
| CPU time | 34.1 seconds |
| Started | Jun 22 04:40:05 PM PDT 24 |
| Finished | Jun 22 04:41:10 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a0304b36-ae60-4b8f-9881-25850058f692 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722692710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1722692710 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1989136698 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12869340000 ps |
| CPU time | 47.82 seconds |
| Started | Jun 22 04:40:01 PM PDT 24 |
| Finished | Jun 22 04:41:34 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-b8952d8e-8629-487a-8a08-05c0f0560a9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989136698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1989136698 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1823549280 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4020700000 ps |
| CPU time | 14.59 seconds |
| Started | Jun 22 04:40:04 PM PDT 24 |
| Finished | Jun 22 04:40:33 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-75926588-506f-4595-b38f-e333d9e17702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823549280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1823549280 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3883289523 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4980460000 ps |
| CPU time | 18.77 seconds |
| Started | Jun 22 04:40:04 PM PDT 24 |
| Finished | Jun 22 04:40:41 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-a5564951-0760-4825-ade3-62095ab91cd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883289523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3883289523 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1152483703 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10617500000 ps |
| CPU time | 37.44 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 04:41:14 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-41112c15-8832-4625-b988-807b7d1147cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152483703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1152483703 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3252057617 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 9643480000 ps |
| CPU time | 31.4 seconds |
| Started | Jun 22 04:40:04 PM PDT 24 |
| Finished | Jun 22 04:41:05 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-7ce04ff6-5a4a-4078-8385-949d4ae16eb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252057617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3252057617 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4114328487 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4843440000 ps |
| CPU time | 19.4 seconds |
| Started | Jun 22 04:40:16 PM PDT 24 |
| Finished | Jun 22 04:40:54 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-f8e116fd-cab8-4bbb-8f60-6bf7848541cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114328487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4114328487 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1789795240 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5652540000 ps |
| CPU time | 21.32 seconds |
| Started | Jun 22 04:40:57 PM PDT 24 |
| Finished | Jun 22 04:41:38 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-c9b46fc2-d056-4a68-aca6-27f355dadffc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789795240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1789795240 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1825902603 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14669200000 ps |
| CPU time | 47.51 seconds |
| Started | Jun 22 04:40:18 PM PDT 24 |
| Finished | Jun 22 04:41:47 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-6e4b243d-004b-41b7-b7bd-056c30aea532 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825902603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1825902603 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1072642092 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9875360000 ps |
| CPU time | 33.73 seconds |
| Started | Jun 22 04:40:07 PM PDT 24 |
| Finished | Jun 22 04:41:11 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-50984bd3-d0e0-48a5-8838-f39903653f06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072642092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1072642092 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2174684959 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13065260000 ps |
| CPU time | 50.19 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 04:41:36 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-1b1daa70-d6f1-4847-9b4d-3d038726ef33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174684959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2174684959 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3686332759 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11895320000 ps |
| CPU time | 43.44 seconds |
| Started | Jun 22 04:39:54 PM PDT 24 |
| Finished | Jun 22 04:41:18 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-b4580638-f375-4507-a300-783a30da77d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686332759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3686332759 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3517114257 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3623280000 ps |
| CPU time | 11.9 seconds |
| Started | Jun 22 04:40:01 PM PDT 24 |
| Finished | Jun 22 04:40:25 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-2ea7162c-9cf6-49fb-9d16-607f64179a22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517114257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3517114257 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2411159894 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11925080000 ps |
| CPU time | 38.88 seconds |
| Started | Jun 22 04:40:01 PM PDT 24 |
| Finished | Jun 22 04:41:17 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-7a30ff2a-1a2f-4cc0-9dde-1585bfc9c638 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411159894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2411159894 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.416811307 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 15501860000 ps |
| CPU time | 55.15 seconds |
| Started | Jun 22 04:40:03 PM PDT 24 |
| Finished | Jun 22 04:41:51 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-50229336-6962-4d1d-87da-52fb91a1f1f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416811307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.416811307 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3706483272 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11491080000 ps |
| CPU time | 42.41 seconds |
| Started | Jun 22 04:40:03 PM PDT 24 |
| Finished | Jun 22 04:41:26 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-64286879-ffca-4a29-be26-a86c95e6ab05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3706483272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3706483272 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2252171094 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13258080000 ps |
| CPU time | 42.88 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 04:41:21 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-e49f7107-b02d-40dd-a5a0-a75dd7b42fb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2252171094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2252171094 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.139118435 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6005320000 ps |
| CPU time | 21.88 seconds |
| Started | Jun 22 04:40:12 PM PDT 24 |
| Finished | Jun 22 04:40:54 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-bcb21310-5ba8-4882-a23b-999be1eaa8a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139118435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.139118435 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.82746583 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8928000000 ps |
| CPU time | 30.36 seconds |
| Started | Jun 22 04:40:05 PM PDT 24 |
| Finished | Jun 22 04:41:03 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-bfaf911a-d445-412b-838f-160932eae66a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82746583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.82746583 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1998289768 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7272600000 ps |
| CPU time | 21.49 seconds |
| Started | Jun 22 04:40:17 PM PDT 24 |
| Finished | Jun 22 04:40:57 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-75320f3b-68d7-4082-a96b-eb0c9297298a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998289768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1998289768 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2686087809 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14953160000 ps |
| CPU time | 47.75 seconds |
| Started | Jun 22 04:40:00 PM PDT 24 |
| Finished | Jun 22 04:41:30 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-9b1b94ca-696b-404e-b53d-b11fee6e5c5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686087809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2686087809 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1517339382 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9582720000 ps |
| CPU time | 33.94 seconds |
| Started | Jun 22 04:40:03 PM PDT 24 |
| Finished | Jun 22 04:41:08 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-a9b4e29d-3459-438d-b6a3-9c79cc968cfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517339382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1517339382 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3356105983 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12653580000 ps |
| CPU time | 50.03 seconds |
| Started | Jun 22 04:40:11 PM PDT 24 |
| Finished | Jun 22 04:41:49 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-bf558b8a-c311-41ea-b839-efc3976d7382 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356105983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3356105983 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3727702264 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9153680000 ps |
| CPU time | 31.03 seconds |
| Started | Jun 22 04:39:58 PM PDT 24 |
| Finished | Jun 22 04:40:57 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-c3c8e487-eaf7-4189-a7c0-c5c59ea0c9a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727702264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3727702264 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2221626630 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4188720000 ps |
| CPU time | 15.78 seconds |
| Started | Jun 22 04:40:22 PM PDT 24 |
| Finished | Jun 22 04:41:02 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-b7a43cd8-1455-4b58-a0c7-201c10dfae6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221626630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2221626630 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3150603891 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10794820000 ps |
| CPU time | 41.02 seconds |
| Started | Jun 22 04:40:03 PM PDT 24 |
| Finished | Jun 22 04:41:23 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-7efc28b2-f305-49ac-9d27-e466c783882d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150603891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3150603891 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3241554124 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7000420000 ps |
| CPU time | 26.78 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 04:40:58 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-1e9123d2-2e18-4231-8beb-dd7919113a7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241554124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3241554124 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2804061815 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9729660000 ps |
| CPU time | 39.32 seconds |
| Started | Jun 22 04:40:01 PM PDT 24 |
| Finished | Jun 22 04:41:19 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-02027a05-1842-4d8e-89b5-b4f79def98a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804061815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2804061815 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.108885609 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6231000000 ps |
| CPU time | 27.05 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 04:40:56 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-9435596d-4efd-4c89-b4d5-b5a35209f77d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108885609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.108885609 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3321422844 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3489360000 ps |
| CPU time | 15.09 seconds |
| Started | Jun 22 04:40:01 PM PDT 24 |
| Finished | Jun 22 04:40:31 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-00eadac1-3267-488d-9962-d2abdb98ec3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321422844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3321422844 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3057938202 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 15385920000 ps |
| CPU time | 48.28 seconds |
| Started | Jun 22 04:40:06 PM PDT 24 |
| Finished | Jun 22 04:41:38 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-dff88550-3cc3-485d-8d43-90731000068b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057938202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3057938202 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.523960550 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12212140000 ps |
| CPU time | 45.24 seconds |
| Started | Jun 22 04:39:57 PM PDT 24 |
| Finished | Jun 22 04:41:25 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-0f0d4a3a-fc67-404f-af04-63870bdb8735 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523960550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.523960550 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |