| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.767663695 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3022241100 |
| /workspace/coverage/default/1.prim_present_test.4181207330 |
| /workspace/coverage/default/10.prim_present_test.94235753 |
| /workspace/coverage/default/12.prim_present_test.2139522161 |
| /workspace/coverage/default/13.prim_present_test.2884711591 |
| /workspace/coverage/default/14.prim_present_test.2356013752 |
| /workspace/coverage/default/15.prim_present_test.1363891109 |
| /workspace/coverage/default/16.prim_present_test.3200709068 |
| /workspace/coverage/default/17.prim_present_test.509253141 |
| /workspace/coverage/default/18.prim_present_test.1268334590 |
| /workspace/coverage/default/19.prim_present_test.2215695101 |
| /workspace/coverage/default/2.prim_present_test.3781185992 |
| /workspace/coverage/default/20.prim_present_test.1431646597 |
| /workspace/coverage/default/21.prim_present_test.2510064318 |
| /workspace/coverage/default/22.prim_present_test.1671434603 |
| /workspace/coverage/default/23.prim_present_test.1057928283 |
| /workspace/coverage/default/24.prim_present_test.3175879182 |
| /workspace/coverage/default/25.prim_present_test.2240902823 |
| /workspace/coverage/default/26.prim_present_test.2601711442 |
| /workspace/coverage/default/27.prim_present_test.3596949844 |
| /workspace/coverage/default/28.prim_present_test.2769920915 |
| /workspace/coverage/default/29.prim_present_test.3715869352 |
| /workspace/coverage/default/3.prim_present_test.2124394604 |
| /workspace/coverage/default/30.prim_present_test.1927912996 |
| /workspace/coverage/default/31.prim_present_test.2295257105 |
| /workspace/coverage/default/32.prim_present_test.2227614435 |
| /workspace/coverage/default/33.prim_present_test.3031106098 |
| /workspace/coverage/default/34.prim_present_test.1669348552 |
| /workspace/coverage/default/35.prim_present_test.2569402045 |
| /workspace/coverage/default/36.prim_present_test.680372624 |
| /workspace/coverage/default/37.prim_present_test.1005649197 |
| /workspace/coverage/default/38.prim_present_test.165159803 |
| /workspace/coverage/default/39.prim_present_test.4073831958 |
| /workspace/coverage/default/4.prim_present_test.3469681298 |
| /workspace/coverage/default/40.prim_present_test.1110450464 |
| /workspace/coverage/default/41.prim_present_test.3646093242 |
| /workspace/coverage/default/42.prim_present_test.2737010543 |
| /workspace/coverage/default/43.prim_present_test.3204485775 |
| /workspace/coverage/default/44.prim_present_test.2190482603 |
| /workspace/coverage/default/45.prim_present_test.4187470544 |
| /workspace/coverage/default/46.prim_present_test.2379731015 |
| /workspace/coverage/default/47.prim_present_test.2443310408 |
| /workspace/coverage/default/48.prim_present_test.4128052975 |
| /workspace/coverage/default/49.prim_present_test.2237434512 |
| /workspace/coverage/default/5.prim_present_test.2692304401 |
| /workspace/coverage/default/6.prim_present_test.2700875342 |
| /workspace/coverage/default/7.prim_present_test.2566903568 |
| /workspace/coverage/default/8.prim_present_test.608484486 |
| /workspace/coverage/default/9.prim_present_test.1827014687 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_present_test.509253141 | Jun 23 04:18:14 PM PDT 24 | Jun 23 04:18:38 PM PDT 24 | 3576780000 ps | ||
| T2 | /workspace/coverage/default/6.prim_present_test.2700875342 | Jun 23 04:18:09 PM PDT 24 | Jun 23 04:18:45 PM PDT 24 | 4955040000 ps | ||
| T3 | /workspace/coverage/default/3.prim_present_test.2124394604 | Jun 23 04:18:16 PM PDT 24 | Jun 23 04:19:38 PM PDT 24 | 10996320000 ps | ||
| T4 | /workspace/coverage/default/21.prim_present_test.2510064318 | Jun 23 04:18:17 PM PDT 24 | Jun 23 04:18:57 PM PDT 24 | 5901160000 ps | ||
| T5 | /workspace/coverage/default/39.prim_present_test.4073831958 | Jun 23 04:19:16 PM PDT 24 | Jun 23 04:20:51 PM PDT 24 | 14098800000 ps | ||
| T6 | /workspace/coverage/default/11.prim_present_test.767663695 | Jun 23 04:19:29 PM PDT 24 | Jun 23 04:19:59 PM PDT 24 | 3963040000 ps | ||
| T7 | /workspace/coverage/default/7.prim_present_test.2566903568 | Jun 23 04:19:15 PM PDT 24 | Jun 23 04:20:47 PM PDT 24 | 12941880000 ps | ||
| T8 | /workspace/coverage/default/20.prim_present_test.1431646597 | Jun 23 04:18:15 PM PDT 24 | Jun 23 04:18:55 PM PDT 24 | 5890620000 ps | ||
| T9 | /workspace/coverage/default/35.prim_present_test.2569402045 | Jun 23 04:18:10 PM PDT 24 | Jun 23 04:18:47 PM PDT 24 | 5368580000 ps | ||
| T10 | /workspace/coverage/default/37.prim_present_test.1005649197 | Jun 23 04:18:29 PM PDT 24 | Jun 23 04:19:51 PM PDT 24 | 12722400000 ps | ||
| T11 | /workspace/coverage/default/23.prim_present_test.1057928283 | Jun 23 04:19:15 PM PDT 24 | Jun 23 04:20:27 PM PDT 24 | 9649060000 ps | ||
| T12 | /workspace/coverage/default/29.prim_present_test.3715869352 | Jun 23 04:19:15 PM PDT 24 | Jun 23 04:20:22 PM PDT 24 | 9086100000 ps | ||
| T13 | /workspace/coverage/default/48.prim_present_test.4128052975 | Jun 23 04:23:27 PM PDT 24 | Jun 23 04:24:09 PM PDT 24 | 6823100000 ps | ||
| T14 | /workspace/coverage/default/40.prim_present_test.1110450464 | Jun 23 04:23:31 PM PDT 24 | Jun 23 04:24:31 PM PDT 24 | 10313700000 ps | ||
| T15 | /workspace/coverage/default/42.prim_present_test.2737010543 | Jun 23 04:23:22 PM PDT 24 | Jun 23 04:24:36 PM PDT 24 | 11931280000 ps | ||
| T16 | /workspace/coverage/default/41.prim_present_test.3646093242 | Jun 23 04:19:52 PM PDT 24 | Jun 23 04:21:13 PM PDT 24 | 11931900000 ps | ||
| T17 | /workspace/coverage/default/28.prim_present_test.2769920915 | Jun 23 04:19:15 PM PDT 24 | Jun 23 04:21:01 PM PDT 24 | 15155280000 ps | ||
| T18 | /workspace/coverage/default/36.prim_present_test.680372624 | Jun 23 04:18:29 PM PDT 24 | Jun 23 04:19:43 PM PDT 24 | 11407380000 ps | ||
| T19 | /workspace/coverage/default/38.prim_present_test.165159803 | Jun 23 04:18:04 PM PDT 24 | Jun 23 04:18:32 PM PDT 24 | 4175080000 ps | ||
| T20 | /workspace/coverage/default/49.prim_present_test.2237434512 | Jun 23 04:19:53 PM PDT 24 | Jun 23 04:20:35 PM PDT 24 | 6859680000 ps | ||
| T21 | /workspace/coverage/default/46.prim_present_test.2379731015 | Jun 23 04:23:22 PM PDT 24 | Jun 23 04:23:59 PM PDT 24 | 5647580000 ps | ||
| T22 | /workspace/coverage/default/8.prim_present_test.608484486 | Jun 23 04:18:17 PM PDT 24 | Jun 23 04:18:42 PM PDT 24 | 3434180000 ps | ||
| T23 | /workspace/coverage/default/13.prim_present_test.2884711591 | Jun 23 04:18:12 PM PDT 24 | Jun 23 04:18:47 PM PDT 24 | 4918460000 ps | ||
| T24 | /workspace/coverage/default/9.prim_present_test.1827014687 | Jun 23 04:18:16 PM PDT 24 | Jun 23 04:19:04 PM PDT 24 | 7134340000 ps | ||
| T25 | /workspace/coverage/default/18.prim_present_test.1268334590 | Jun 23 04:18:14 PM PDT 24 | Jun 23 04:19:04 PM PDT 24 | 7278800000 ps | ||
| T26 | /workspace/coverage/default/31.prim_present_test.2295257105 | Jun 23 04:19:15 PM PDT 24 | Jun 23 04:19:42 PM PDT 24 | 3639400000 ps | ||
| T27 | /workspace/coverage/default/22.prim_present_test.1671434603 | Jun 23 04:19:14 PM PDT 24 | Jun 23 04:20:47 PM PDT 24 | 13579240000 ps | ||
| T28 | /workspace/coverage/default/24.prim_present_test.3175879182 | Jun 23 04:18:13 PM PDT 24 | Jun 23 04:18:57 PM PDT 24 | 5596120000 ps | ||
| T29 | /workspace/coverage/default/34.prim_present_test.1669348552 | Jun 23 04:18:06 PM PDT 24 | Jun 23 04:18:41 PM PDT 24 | 5612860000 ps | ||
| T30 | /workspace/coverage/default/30.prim_present_test.1927912996 | Jun 23 04:19:15 PM PDT 24 | Jun 23 04:20:59 PM PDT 24 | 14627040000 ps | ||
| T31 | /workspace/coverage/default/16.prim_present_test.3200709068 | Jun 23 04:18:16 PM PDT 24 | Jun 23 04:19:52 PM PDT 24 | 13463300000 ps | ||
| T32 | /workspace/coverage/default/26.prim_present_test.2601711442 | Jun 23 04:18:13 PM PDT 24 | Jun 23 04:18:52 PM PDT 24 | 4955660000 ps | ||
| T33 | /workspace/coverage/default/1.prim_present_test.4181207330 | Jun 23 04:19:30 PM PDT 24 | Jun 23 04:20:27 PM PDT 24 | 7877720000 ps | ||
| T34 | /workspace/coverage/default/45.prim_present_test.4187470544 | Jun 23 04:20:09 PM PDT 24 | Jun 23 04:21:27 PM PDT 24 | 10695000000 ps | ||
| T35 | /workspace/coverage/default/5.prim_present_test.2692304401 | Jun 23 04:18:09 PM PDT 24 | Jun 23 04:18:48 PM PDT 24 | 5403920000 ps | ||
| T36 | /workspace/coverage/default/32.prim_present_test.2227614435 | Jun 23 04:19:14 PM PDT 24 | Jun 23 04:19:36 PM PDT 24 | 3150220000 ps | ||
| T37 | /workspace/coverage/default/15.prim_present_test.1363891109 | Jun 23 04:18:17 PM PDT 24 | Jun 23 04:19:32 PM PDT 24 | 10284560000 ps | ||
| T38 | /workspace/coverage/default/2.prim_present_test.3781185992 | Jun 23 04:18:14 PM PDT 24 | Jun 23 04:19:28 PM PDT 24 | 10937420000 ps | ||
| T39 | /workspace/coverage/default/27.prim_present_test.3596949844 | Jun 23 04:18:17 PM PDT 24 | Jun 23 04:18:51 PM PDT 24 | 5101360000 ps | ||
| T40 | /workspace/coverage/default/4.prim_present_test.3469681298 | Jun 23 04:18:08 PM PDT 24 | Jun 23 04:19:34 PM PDT 24 | 12194160000 ps | ||
| T41 | /workspace/coverage/default/12.prim_present_test.2139522161 | Jun 23 04:18:17 PM PDT 24 | Jun 23 04:19:48 PM PDT 24 | 13302100000 ps | ||
| T42 | /workspace/coverage/default/0.prim_present_test.3022241100 | Jun 23 04:19:29 PM PDT 24 | Jun 23 04:20:01 PM PDT 24 | 4062860000 ps | ||
| T43 | /workspace/coverage/default/19.prim_present_test.2215695101 | Jun 23 04:18:16 PM PDT 24 | Jun 23 04:19:46 PM PDT 24 | 14585500000 ps | ||
| T44 | /workspace/coverage/default/14.prim_present_test.2356013752 | Jun 23 04:18:12 PM PDT 24 | Jun 23 04:19:51 PM PDT 24 | 12954280000 ps | ||
| T45 | /workspace/coverage/default/33.prim_present_test.3031106098 | Jun 23 04:19:14 PM PDT 24 | Jun 23 04:20:59 PM PDT 24 | 15247660000 ps | ||
| T46 | /workspace/coverage/default/43.prim_present_test.3204485775 | Jun 23 04:23:26 PM PDT 24 | Jun 23 04:24:31 PM PDT 24 | 11202780000 ps | ||
| T47 | /workspace/coverage/default/44.prim_present_test.2190482603 | Jun 23 04:19:11 PM PDT 24 | Jun 23 04:20:12 PM PDT 24 | 8608700000 ps | ||
| T48 | /workspace/coverage/default/47.prim_present_test.2443310408 | Jun 23 04:19:51 PM PDT 24 | Jun 23 04:20:35 PM PDT 24 | 6333920000 ps | ||
| T49 | /workspace/coverage/default/10.prim_present_test.94235753 | Jun 23 04:18:13 PM PDT 24 | Jun 23 04:19:07 PM PDT 24 | 8486560000 ps | ||
| T50 | /workspace/coverage/default/25.prim_present_test.2240902823 | Jun 23 04:18:16 PM PDT 24 | Jun 23 04:18:53 PM PDT 24 | 5349360000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.767663695 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3963040000 ps |
| CPU time | 15.44 seconds |
| Started | Jun 23 04:19:29 PM PDT 24 |
| Finished | Jun 23 04:19:59 PM PDT 24 |
| Peak memory | 144764 kb |
| Host | smart-bed9f5e1-cd13-458f-bfe5-366f1392f25e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=767663695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.767663695 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3022241100 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4062860000 ps |
| CPU time | 16.4 seconds |
| Started | Jun 23 04:19:29 PM PDT 24 |
| Finished | Jun 23 04:20:01 PM PDT 24 |
| Peak memory | 144760 kb |
| Host | smart-7a720128-cb0e-4353-b65c-40468afa0e53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022241100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3022241100 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4181207330 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7877720000 ps |
| CPU time | 30.17 seconds |
| Started | Jun 23 04:19:30 PM PDT 24 |
| Finished | Jun 23 04:20:27 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-df403fea-135d-48c7-9271-32693936e880 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181207330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4181207330 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.94235753 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8486560000 ps |
| CPU time | 29 seconds |
| Started | Jun 23 04:18:13 PM PDT 24 |
| Finished | Jun 23 04:19:07 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-714820d5-c4f6-445c-9484-a993c92a7379 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94235753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.94235753 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2139522161 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13302100000 ps |
| CPU time | 48.74 seconds |
| Started | Jun 23 04:18:17 PM PDT 24 |
| Finished | Jun 23 04:19:48 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-1dd97e31-6dc8-49bd-9bcc-c53e66806ff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139522161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2139522161 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2884711591 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4918460000 ps |
| CPU time | 18.13 seconds |
| Started | Jun 23 04:18:12 PM PDT 24 |
| Finished | Jun 23 04:18:47 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-bb8c141a-6e33-4cb6-bc7a-d25d928f7801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2884711591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2884711591 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2356013752 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12954280000 ps |
| CPU time | 51.65 seconds |
| Started | Jun 23 04:18:12 PM PDT 24 |
| Finished | Jun 23 04:19:51 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-ffb7c0e6-9123-4a27-9870-90ce5bf0e084 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356013752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2356013752 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1363891109 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10284560000 ps |
| CPU time | 39.41 seconds |
| Started | Jun 23 04:18:17 PM PDT 24 |
| Finished | Jun 23 04:19:32 PM PDT 24 |
| Peak memory | 144648 kb |
| Host | smart-21495a93-0554-4920-909f-d6f755e7d042 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363891109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1363891109 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3200709068 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13463300000 ps |
| CPU time | 50.56 seconds |
| Started | Jun 23 04:18:16 PM PDT 24 |
| Finished | Jun 23 04:19:52 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-972974b2-54a6-4143-a232-3722186f437e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200709068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3200709068 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.509253141 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3576780000 ps |
| CPU time | 12.48 seconds |
| Started | Jun 23 04:18:14 PM PDT 24 |
| Finished | Jun 23 04:18:38 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-f721dc18-5432-4b4a-a673-3acb9028d00d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509253141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.509253141 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1268334590 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7278800000 ps |
| CPU time | 26.5 seconds |
| Started | Jun 23 04:18:14 PM PDT 24 |
| Finished | Jun 23 04:19:04 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-80206e93-3eaa-4c75-897f-22efde4b8385 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268334590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1268334590 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2215695101 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14585500000 ps |
| CPU time | 49.04 seconds |
| Started | Jun 23 04:18:16 PM PDT 24 |
| Finished | Jun 23 04:19:46 PM PDT 24 |
| Peak memory | 143932 kb |
| Host | smart-83e625bf-b395-4b58-a288-b7cf75df607b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215695101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2215695101 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3781185992 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10937420000 ps |
| CPU time | 39.02 seconds |
| Started | Jun 23 04:18:14 PM PDT 24 |
| Finished | Jun 23 04:19:28 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-f90135ff-03ce-48e5-95cb-3498eaaa7ac6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781185992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3781185992 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1431646597 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5890620000 ps |
| CPU time | 21.62 seconds |
| Started | Jun 23 04:18:15 PM PDT 24 |
| Finished | Jun 23 04:18:55 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-9726dd3b-035b-41f2-9292-2b2ca7b1714a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431646597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1431646597 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2510064318 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5901160000 ps |
| CPU time | 21.27 seconds |
| Started | Jun 23 04:18:17 PM PDT 24 |
| Finished | Jun 23 04:18:57 PM PDT 24 |
| Peak memory | 144656 kb |
| Host | smart-154cec5d-17f3-4ac1-8283-f94612c572ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510064318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2510064318 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1671434603 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13579240000 ps |
| CPU time | 49.18 seconds |
| Started | Jun 23 04:19:14 PM PDT 24 |
| Finished | Jun 23 04:20:47 PM PDT 24 |
| Peak memory | 143204 kb |
| Host | smart-a42affd2-04d3-425e-b950-4fd178a75a7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671434603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1671434603 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1057928283 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9649060000 ps |
| CPU time | 37.34 seconds |
| Started | Jun 23 04:19:15 PM PDT 24 |
| Finished | Jun 23 04:20:27 PM PDT 24 |
| Peak memory | 142564 kb |
| Host | smart-a65f2b8c-233b-4a3b-adda-0529d4d34b72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057928283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1057928283 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3175879182 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5596120000 ps |
| CPU time | 22.62 seconds |
| Started | Jun 23 04:18:13 PM PDT 24 |
| Finished | Jun 23 04:18:57 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-7dd26112-b878-4d29-8b49-65911de2df92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3175879182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3175879182 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2240902823 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5349360000 ps |
| CPU time | 19.67 seconds |
| Started | Jun 23 04:18:16 PM PDT 24 |
| Finished | Jun 23 04:18:53 PM PDT 24 |
| Peak memory | 144544 kb |
| Host | smart-d880ef85-bd2d-4601-be5d-4bbada811a08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240902823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2240902823 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2601711442 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4955660000 ps |
| CPU time | 19.98 seconds |
| Started | Jun 23 04:18:13 PM PDT 24 |
| Finished | Jun 23 04:18:52 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-cf80b615-6e6b-42b1-ac93-2ff00c98f047 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601711442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2601711442 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3596949844 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5101360000 ps |
| CPU time | 18.41 seconds |
| Started | Jun 23 04:18:17 PM PDT 24 |
| Finished | Jun 23 04:18:51 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-f5c04278-5620-4216-a14f-a6a409f1aee9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596949844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3596949844 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2769920915 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 15155280000 ps |
| CPU time | 56.09 seconds |
| Started | Jun 23 04:19:15 PM PDT 24 |
| Finished | Jun 23 04:21:01 PM PDT 24 |
| Peak memory | 142784 kb |
| Host | smart-f470e3e7-69d4-45d1-beca-451565052ddf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769920915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2769920915 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3715869352 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9086100000 ps |
| CPU time | 34.66 seconds |
| Started | Jun 23 04:19:15 PM PDT 24 |
| Finished | Jun 23 04:20:22 PM PDT 24 |
| Peak memory | 144444 kb |
| Host | smart-ff4177da-0dd3-4127-adb7-def64bc018f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715869352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3715869352 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2124394604 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10996320000 ps |
| CPU time | 43.32 seconds |
| Started | Jun 23 04:18:16 PM PDT 24 |
| Finished | Jun 23 04:19:38 PM PDT 24 |
| Peak memory | 144016 kb |
| Host | smart-2dbf3609-4b38-4c42-a832-da9776d74f6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124394604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2124394604 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1927912996 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14627040000 ps |
| CPU time | 54.08 seconds |
| Started | Jun 23 04:19:15 PM PDT 24 |
| Finished | Jun 23 04:20:59 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-becd65e2-68ea-4a1d-a0c8-a20394ae260c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927912996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1927912996 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2295257105 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3639400000 ps |
| CPU time | 13.68 seconds |
| Started | Jun 23 04:19:15 PM PDT 24 |
| Finished | Jun 23 04:19:42 PM PDT 24 |
| Peak memory | 143480 kb |
| Host | smart-50b7b736-8367-4b2e-a09a-c4f1c2ef7daa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295257105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2295257105 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2227614435 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3150220000 ps |
| CPU time | 11.22 seconds |
| Started | Jun 23 04:19:14 PM PDT 24 |
| Finished | Jun 23 04:19:36 PM PDT 24 |
| Peak memory | 143004 kb |
| Host | smart-bda351af-24d0-4a68-b881-6aea42bbb6c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2227614435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2227614435 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3031106098 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 15247660000 ps |
| CPU time | 54.98 seconds |
| Started | Jun 23 04:19:14 PM PDT 24 |
| Finished | Jun 23 04:20:59 PM PDT 24 |
| Peak memory | 143736 kb |
| Host | smart-b34d86e1-d01f-409a-be7c-de8e9795e99b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031106098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3031106098 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1669348552 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5612860000 ps |
| CPU time | 19.16 seconds |
| Started | Jun 23 04:18:06 PM PDT 24 |
| Finished | Jun 23 04:18:41 PM PDT 24 |
| Peak memory | 144600 kb |
| Host | smart-edc0aab1-fe14-432f-add1-6b7518501f80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669348552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1669348552 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2569402045 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5368580000 ps |
| CPU time | 19.09 seconds |
| Started | Jun 23 04:18:10 PM PDT 24 |
| Finished | Jun 23 04:18:47 PM PDT 24 |
| Peak memory | 144016 kb |
| Host | smart-87778748-0009-46e9-b83f-1acd96fb8e1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569402045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2569402045 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.680372624 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11407380000 ps |
| CPU time | 40.06 seconds |
| Started | Jun 23 04:18:29 PM PDT 24 |
| Finished | Jun 23 04:19:43 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-e4d66606-1515-4d73-91c4-de42975aae33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680372624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.680372624 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1005649197 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12722400000 ps |
| CPU time | 44.47 seconds |
| Started | Jun 23 04:18:29 PM PDT 24 |
| Finished | Jun 23 04:19:51 PM PDT 24 |
| Peak memory | 144600 kb |
| Host | smart-ddefb5e3-930a-415d-a31f-4e397ffd8870 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005649197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1005649197 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.165159803 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4175080000 ps |
| CPU time | 14.78 seconds |
| Started | Jun 23 04:18:04 PM PDT 24 |
| Finished | Jun 23 04:18:32 PM PDT 24 |
| Peak memory | 144332 kb |
| Host | smart-cec38350-0e7d-4de1-b1db-9261ac6a4873 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165159803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.165159803 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.4073831958 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14098800000 ps |
| CPU time | 51.08 seconds |
| Started | Jun 23 04:19:16 PM PDT 24 |
| Finished | Jun 23 04:20:51 PM PDT 24 |
| Peak memory | 144796 kb |
| Host | smart-d41acbc6-df36-45f0-9bd2-0a34449e9bd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073831958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4073831958 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3469681298 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12194160000 ps |
| CPU time | 45.26 seconds |
| Started | Jun 23 04:18:08 PM PDT 24 |
| Finished | Jun 23 04:19:34 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-36eb595f-0063-4ed5-bda3-83ba3fb22246 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469681298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3469681298 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1110450464 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10313700000 ps |
| CPU time | 31.74 seconds |
| Started | Jun 23 04:23:31 PM PDT 24 |
| Finished | Jun 23 04:24:31 PM PDT 24 |
| Peak memory | 143992 kb |
| Host | smart-3f204f60-064c-4f38-8f74-97a0894424f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110450464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1110450464 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3646093242 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11931900000 ps |
| CPU time | 43.25 seconds |
| Started | Jun 23 04:19:52 PM PDT 24 |
| Finished | Jun 23 04:21:13 PM PDT 24 |
| Peak memory | 144852 kb |
| Host | smart-daa3af5d-796f-48cb-bffa-7ca9db2938ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646093242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3646093242 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2737010543 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11931280000 ps |
| CPU time | 38.54 seconds |
| Started | Jun 23 04:23:22 PM PDT 24 |
| Finished | Jun 23 04:24:36 PM PDT 24 |
| Peak memory | 143712 kb |
| Host | smart-d5d06c02-c6e1-4b1a-abe2-44a572c81372 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737010543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2737010543 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3204485775 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11202780000 ps |
| CPU time | 35.09 seconds |
| Started | Jun 23 04:23:26 PM PDT 24 |
| Finished | Jun 23 04:24:31 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-5da94773-5776-4270-b076-bd2501782ac9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204485775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3204485775 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2190482603 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8608700000 ps |
| CPU time | 32.65 seconds |
| Started | Jun 23 04:19:11 PM PDT 24 |
| Finished | Jun 23 04:20:12 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-40baab23-9194-4828-8ad5-8b9886d31193 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190482603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2190482603 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4187470544 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10695000000 ps |
| CPU time | 40.75 seconds |
| Started | Jun 23 04:20:09 PM PDT 24 |
| Finished | Jun 23 04:21:27 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-44c6a9a9-e549-469b-a1ab-869b1fc53002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187470544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4187470544 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2379731015 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5647580000 ps |
| CPU time | 19.3 seconds |
| Started | Jun 23 04:23:22 PM PDT 24 |
| Finished | Jun 23 04:23:59 PM PDT 24 |
| Peak memory | 143496 kb |
| Host | smart-12f1c1de-1cd8-4a02-838f-57ab991fd180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2379731015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2379731015 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2443310408 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6333920000 ps |
| CPU time | 23.2 seconds |
| Started | Jun 23 04:19:51 PM PDT 24 |
| Finished | Jun 23 04:20:35 PM PDT 24 |
| Peak memory | 144852 kb |
| Host | smart-34245e0a-ea0d-4121-b987-b5069e1479af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443310408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2443310408 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4128052975 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6823100000 ps |
| CPU time | 22.78 seconds |
| Started | Jun 23 04:23:27 PM PDT 24 |
| Finished | Jun 23 04:24:09 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-30c1fb03-249e-4350-b002-68d98cb5d971 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128052975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4128052975 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2237434512 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6859680000 ps |
| CPU time | 23.19 seconds |
| Started | Jun 23 04:19:53 PM PDT 24 |
| Finished | Jun 23 04:20:35 PM PDT 24 |
| Peak memory | 144852 kb |
| Host | smart-ec397557-e007-41d4-8fc2-8b143d06f2c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237434512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2237434512 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2692304401 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5403920000 ps |
| CPU time | 20.65 seconds |
| Started | Jun 23 04:18:09 PM PDT 24 |
| Finished | Jun 23 04:18:48 PM PDT 24 |
| Peak memory | 144516 kb |
| Host | smart-619ec067-df95-4049-a845-66a75c2ede92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692304401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2692304401 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2700875342 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4955040000 ps |
| CPU time | 19.2 seconds |
| Started | Jun 23 04:18:09 PM PDT 24 |
| Finished | Jun 23 04:18:45 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-07cd43f2-09cb-4e13-a67a-bf8e09b28b22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700875342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2700875342 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2566903568 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12941880000 ps |
| CPU time | 48.21 seconds |
| Started | Jun 23 04:19:15 PM PDT 24 |
| Finished | Jun 23 04:20:47 PM PDT 24 |
| Peak memory | 144500 kb |
| Host | smart-74e626d7-8bb9-4cb7-9e8a-2d776233a045 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2566903568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2566903568 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.608484486 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3434180000 ps |
| CPU time | 13.36 seconds |
| Started | Jun 23 04:18:17 PM PDT 24 |
| Finished | Jun 23 04:18:42 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-b02fd919-fc7b-4ebf-b686-66129d82c373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608484486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.608484486 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1827014687 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7134340000 ps |
| CPU time | 25.74 seconds |
| Started | Jun 23 04:18:16 PM PDT 24 |
| Finished | Jun 23 04:19:04 PM PDT 24 |
| Peak memory | 144040 kb |
| Host | smart-0e8d5a78-d554-4694-8104-e049f7f28f1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827014687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1827014687 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |