| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.2693311484 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.996364583 |
| /workspace/coverage/default/10.prim_present_test.2298836796 |
| /workspace/coverage/default/11.prim_present_test.646563367 |
| /workspace/coverage/default/12.prim_present_test.3633340132 |
| /workspace/coverage/default/13.prim_present_test.931728788 |
| /workspace/coverage/default/14.prim_present_test.3848663880 |
| /workspace/coverage/default/15.prim_present_test.355911234 |
| /workspace/coverage/default/16.prim_present_test.797343378 |
| /workspace/coverage/default/17.prim_present_test.4061790796 |
| /workspace/coverage/default/18.prim_present_test.393228821 |
| /workspace/coverage/default/19.prim_present_test.1284868427 |
| /workspace/coverage/default/2.prim_present_test.2125803151 |
| /workspace/coverage/default/20.prim_present_test.2445183236 |
| /workspace/coverage/default/21.prim_present_test.959178588 |
| /workspace/coverage/default/22.prim_present_test.3750485399 |
| /workspace/coverage/default/23.prim_present_test.2188759767 |
| /workspace/coverage/default/24.prim_present_test.4039236196 |
| /workspace/coverage/default/25.prim_present_test.3770974659 |
| /workspace/coverage/default/26.prim_present_test.1541303099 |
| /workspace/coverage/default/27.prim_present_test.313258655 |
| /workspace/coverage/default/28.prim_present_test.1226548952 |
| /workspace/coverage/default/29.prim_present_test.1570543879 |
| /workspace/coverage/default/3.prim_present_test.736639265 |
| /workspace/coverage/default/30.prim_present_test.2783151300 |
| /workspace/coverage/default/31.prim_present_test.1081772666 |
| /workspace/coverage/default/32.prim_present_test.1055146945 |
| /workspace/coverage/default/33.prim_present_test.1625012726 |
| /workspace/coverage/default/34.prim_present_test.3511954477 |
| /workspace/coverage/default/35.prim_present_test.2622938558 |
| /workspace/coverage/default/36.prim_present_test.3376892322 |
| /workspace/coverage/default/37.prim_present_test.2041688091 |
| /workspace/coverage/default/38.prim_present_test.1602061360 |
| /workspace/coverage/default/39.prim_present_test.1882193289 |
| /workspace/coverage/default/4.prim_present_test.2961671566 |
| /workspace/coverage/default/40.prim_present_test.1362426097 |
| /workspace/coverage/default/41.prim_present_test.18698058 |
| /workspace/coverage/default/42.prim_present_test.410965639 |
| /workspace/coverage/default/43.prim_present_test.1945309987 |
| /workspace/coverage/default/44.prim_present_test.2352267304 |
| /workspace/coverage/default/45.prim_present_test.750999382 |
| /workspace/coverage/default/46.prim_present_test.640301166 |
| /workspace/coverage/default/47.prim_present_test.1173084077 |
| /workspace/coverage/default/48.prim_present_test.1875668879 |
| /workspace/coverage/default/49.prim_present_test.4147112689 |
| /workspace/coverage/default/5.prim_present_test.3887509201 |
| /workspace/coverage/default/6.prim_present_test.2181533380 |
| /workspace/coverage/default/7.prim_present_test.4075291625 |
| /workspace/coverage/default/8.prim_present_test.1618677832 |
| /workspace/coverage/default/9.prim_present_test.2423515258 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/45.prim_present_test.750999382 | Jun 24 04:17:22 PM PDT 24 | Jun 24 04:18:04 PM PDT 24 | 5201180000 ps | ||
| T2 | /workspace/coverage/default/20.prim_present_test.2445183236 | Jun 24 04:17:36 PM PDT 24 | Jun 24 04:19:22 PM PDT 24 | 15333220000 ps | ||
| T3 | /workspace/coverage/default/1.prim_present_test.2693311484 | Jun 24 04:16:21 PM PDT 24 | Jun 24 04:16:56 PM PDT 24 | 4822980000 ps | ||
| T4 | /workspace/coverage/default/33.prim_present_test.1625012726 | Jun 24 04:17:22 PM PDT 24 | Jun 24 04:18:59 PM PDT 24 | 12783780000 ps | ||
| T5 | /workspace/coverage/default/34.prim_present_test.3511954477 | Jun 24 04:22:16 PM PDT 24 | Jun 24 04:23:27 PM PDT 24 | 11697540000 ps | ||
| T6 | /workspace/coverage/default/35.prim_present_test.2622938558 | Jun 24 04:21:58 PM PDT 24 | Jun 24 04:22:33 PM PDT 24 | 6304780000 ps | ||
| T7 | /workspace/coverage/default/44.prim_present_test.2352267304 | Jun 24 04:19:20 PM PDT 24 | Jun 24 04:21:08 PM PDT 24 | 14796300000 ps | ||
| T8 | /workspace/coverage/default/27.prim_present_test.313258655 | Jun 24 04:19:14 PM PDT 24 | Jun 24 04:19:45 PM PDT 24 | 4210420000 ps | ||
| T9 | /workspace/coverage/default/28.prim_present_test.1226548952 | Jun 24 04:22:04 PM PDT 24 | Jun 24 04:22:55 PM PDT 24 | 7506340000 ps | ||
| T10 | /workspace/coverage/default/39.prim_present_test.1882193289 | Jun 24 04:21:56 PM PDT 24 | Jun 24 04:22:21 PM PDT 24 | 4165160000 ps | ||
| T11 | /workspace/coverage/default/42.prim_present_test.410965639 | Jun 24 04:21:48 PM PDT 24 | Jun 24 04:22:18 PM PDT 24 | 5047420000 ps | ||
| T12 | /workspace/coverage/default/36.prim_present_test.3376892322 | Jun 24 04:17:55 PM PDT 24 | Jun 24 04:18:58 PM PDT 24 | 9787320000 ps | ||
| T13 | /workspace/coverage/default/19.prim_present_test.1284868427 | Jun 24 04:17:12 PM PDT 24 | Jun 24 04:18:05 PM PDT 24 | 7164720000 ps | ||
| T14 | /workspace/coverage/default/47.prim_present_test.1173084077 | Jun 24 04:20:16 PM PDT 24 | Jun 24 04:21:03 PM PDT 24 | 6049960000 ps | ||
| T15 | /workspace/coverage/default/7.prim_present_test.4075291625 | Jun 24 04:16:44 PM PDT 24 | Jun 24 04:18:01 PM PDT 24 | 12075120000 ps | ||
| T16 | /workspace/coverage/default/22.prim_present_test.3750485399 | Jun 24 04:17:14 PM PDT 24 | Jun 24 04:18:06 PM PDT 24 | 7105200000 ps | ||
| T17 | /workspace/coverage/default/17.prim_present_test.4061790796 | Jun 24 04:18:03 PM PDT 24 | Jun 24 04:19:38 PM PDT 24 | 12360940000 ps | ||
| T18 | /workspace/coverage/default/37.prim_present_test.2041688091 | Jun 24 04:22:18 PM PDT 24 | Jun 24 04:23:53 PM PDT 24 | 14010140000 ps | ||
| T19 | /workspace/coverage/default/12.prim_present_test.3633340132 | Jun 24 04:17:22 PM PDT 24 | Jun 24 04:18:05 PM PDT 24 | 5265660000 ps | ||
| T20 | /workspace/coverage/default/46.prim_present_test.640301166 | Jun 24 04:22:21 PM PDT 24 | Jun 24 04:23:05 PM PDT 24 | 6445520000 ps | ||
| T21 | /workspace/coverage/default/25.prim_present_test.3770974659 | Jun 24 04:22:10 PM PDT 24 | Jun 24 04:23:16 PM PDT 24 | 10310600000 ps | ||
| T22 | /workspace/coverage/default/6.prim_present_test.2181533380 | Jun 24 04:22:01 PM PDT 24 | Jun 24 04:22:48 PM PDT 24 | 7918640000 ps | ||
| T23 | /workspace/coverage/default/14.prim_present_test.3848663880 | Jun 24 04:16:26 PM PDT 24 | Jun 24 04:18:03 PM PDT 24 | 14991600000 ps | ||
| T24 | /workspace/coverage/default/24.prim_present_test.4039236196 | Jun 24 04:22:04 PM PDT 24 | Jun 24 04:22:31 PM PDT 24 | 3948780000 ps | ||
| T25 | /workspace/coverage/default/30.prim_present_test.2783151300 | Jun 24 04:17:51 PM PDT 24 | Jun 24 04:19:06 PM PDT 24 | 9921860000 ps | ||
| T26 | /workspace/coverage/default/31.prim_present_test.1081772666 | Jun 24 04:18:18 PM PDT 24 | Jun 24 04:19:29 PM PDT 24 | 11040340000 ps | ||
| T27 | /workspace/coverage/default/32.prim_present_test.1055146945 | Jun 24 04:17:10 PM PDT 24 | Jun 24 04:17:53 PM PDT 24 | 6666860000 ps | ||
| T28 | /workspace/coverage/default/21.prim_present_test.959178588 | Jun 24 04:18:06 PM PDT 24 | Jun 24 04:18:59 PM PDT 24 | 7040720000 ps | ||
| T29 | /workspace/coverage/default/13.prim_present_test.931728788 | Jun 24 04:16:19 PM PDT 24 | Jun 24 04:17:29 PM PDT 24 | 10102900000 ps | ||
| T30 | /workspace/coverage/default/26.prim_present_test.1541303099 | Jun 24 04:21:37 PM PDT 24 | Jun 24 04:23:02 PM PDT 24 | 14275500000 ps | ||
| T31 | /workspace/coverage/default/2.prim_present_test.2125803151 | Jun 24 04:16:31 PM PDT 24 | Jun 24 04:17:29 PM PDT 24 | 8374960000 ps | ||
| T32 | /workspace/coverage/default/38.prim_present_test.1602061360 | Jun 24 04:22:04 PM PDT 24 | Jun 24 04:22:53 PM PDT 24 | 6421340000 ps | ||
| T33 | /workspace/coverage/default/5.prim_present_test.3887509201 | Jun 24 04:16:19 PM PDT 24 | Jun 24 04:17:56 PM PDT 24 | 13148340000 ps | ||
| T34 | /workspace/coverage/default/9.prim_present_test.2423515258 | Jun 24 04:16:31 PM PDT 24 | Jun 24 04:17:09 PM PDT 24 | 5454140000 ps | ||
| T35 | /workspace/coverage/default/4.prim_present_test.2961671566 | Jun 24 04:16:26 PM PDT 24 | Jun 24 04:17:18 PM PDT 24 | 8225540000 ps | ||
| T36 | /workspace/coverage/default/16.prim_present_test.797343378 | Jun 24 04:17:17 PM PDT 24 | Jun 24 04:18:07 PM PDT 24 | 7441240000 ps | ||
| T37 | /workspace/coverage/default/41.prim_present_test.18698058 | Jun 24 04:18:30 PM PDT 24 | Jun 24 04:18:53 PM PDT 24 | 3271120000 ps | ||
| T38 | /workspace/coverage/default/15.prim_present_test.355911234 | Jun 24 04:16:26 PM PDT 24 | Jun 24 04:17:44 PM PDT 24 | 12165640000 ps | ||
| T39 | /workspace/coverage/default/0.prim_present_test.996364583 | Jun 24 04:20:01 PM PDT 24 | Jun 24 04:20:48 PM PDT 24 | 6524880000 ps | ||
| T40 | /workspace/coverage/default/23.prim_present_test.2188759767 | Jun 24 04:21:37 PM PDT 24 | Jun 24 04:22:44 PM PDT 24 | 11256720000 ps | ||
| T41 | /workspace/coverage/default/43.prim_present_test.1945309987 | Jun 24 04:22:21 PM PDT 24 | Jun 24 04:23:24 PM PDT 24 | 9503980000 ps | ||
| T42 | /workspace/coverage/default/8.prim_present_test.1618677832 | Jun 24 04:16:43 PM PDT 24 | Jun 24 04:18:00 PM PDT 24 | 10927500000 ps | ||
| T43 | /workspace/coverage/default/18.prim_present_test.393228821 | Jun 24 04:22:11 PM PDT 24 | Jun 24 04:23:03 PM PDT 24 | 7887020000 ps | ||
| T44 | /workspace/coverage/default/49.prim_present_test.4147112689 | Jun 24 04:22:20 PM PDT 24 | Jun 24 04:23:57 PM PDT 24 | 14748560000 ps | ||
| T45 | /workspace/coverage/default/3.prim_present_test.736639265 | Jun 24 04:16:21 PM PDT 24 | Jun 24 04:17:17 PM PDT 24 | 8259640000 ps | ||
| T46 | /workspace/coverage/default/10.prim_present_test.2298836796 | Jun 24 04:16:22 PM PDT 24 | Jun 24 04:16:43 PM PDT 24 | 3554460000 ps | ||
| T47 | /workspace/coverage/default/40.prim_present_test.1362426097 | Jun 24 04:22:03 PM PDT 24 | Jun 24 04:23:47 PM PDT 24 | 15038100000 ps | ||
| T48 | /workspace/coverage/default/48.prim_present_test.1875668879 | Jun 24 04:22:04 PM PDT 24 | Jun 24 04:22:42 PM PDT 24 | 5632080000 ps | ||
| T49 | /workspace/coverage/default/29.prim_present_test.1570543879 | Jun 24 04:22:11 PM PDT 24 | Jun 24 04:22:34 PM PDT 24 | 3210360000 ps | ||
| T50 | /workspace/coverage/default/11.prim_present_test.646563367 | Jun 24 04:16:45 PM PDT 24 | Jun 24 04:17:53 PM PDT 24 | 8907540000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.2693311484 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4822980000 ps |
| CPU time | 18.73 seconds |
| Started | Jun 24 04:16:21 PM PDT 24 |
| Finished | Jun 24 04:16:56 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-930276ef-0531-4c70-b7a7-4fe236f0cbf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693311484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2693311484 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.996364583 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6524880000 ps |
| CPU time | 24.61 seconds |
| Started | Jun 24 04:20:01 PM PDT 24 |
| Finished | Jun 24 04:20:48 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-02eca7f0-f66c-4488-a1f0-8845716322fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996364583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.996364583 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2298836796 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3554460000 ps |
| CPU time | 11.47 seconds |
| Started | Jun 24 04:16:22 PM PDT 24 |
| Finished | Jun 24 04:16:43 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-50a93512-2f72-45e6-8d01-d805343c862f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298836796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2298836796 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.646563367 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8907540000 ps |
| CPU time | 35.89 seconds |
| Started | Jun 24 04:16:45 PM PDT 24 |
| Finished | Jun 24 04:17:53 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-9577b9a3-3699-439f-b5f3-cbf1c61449bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646563367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.646563367 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3633340132 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5265660000 ps |
| CPU time | 21.83 seconds |
| Started | Jun 24 04:17:22 PM PDT 24 |
| Finished | Jun 24 04:18:05 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-7bdfb844-e854-4a9c-bc47-2831efee61b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633340132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3633340132 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.931728788 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10102900000 ps |
| CPU time | 37.04 seconds |
| Started | Jun 24 04:16:19 PM PDT 24 |
| Finished | Jun 24 04:17:29 PM PDT 24 |
| Peak memory | 144608 kb |
| Host | smart-c6ae94b3-559f-42e9-978e-f3f07241a229 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931728788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.931728788 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3848663880 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14991600000 ps |
| CPU time | 52.12 seconds |
| Started | Jun 24 04:16:26 PM PDT 24 |
| Finished | Jun 24 04:18:03 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-6365dcc8-9182-42a3-a58d-328ace0f1494 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848663880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3848663880 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.355911234 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12165640000 ps |
| CPU time | 41.89 seconds |
| Started | Jun 24 04:16:26 PM PDT 24 |
| Finished | Jun 24 04:17:44 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-4cdfc3d0-6e88-4894-ad22-1ab79a3b7ea3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355911234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.355911234 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.797343378 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7441240000 ps |
| CPU time | 26.61 seconds |
| Started | Jun 24 04:17:17 PM PDT 24 |
| Finished | Jun 24 04:18:07 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-b5667512-eb1e-487d-ad61-6a9b7093b90a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797343378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.797343378 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4061790796 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12360940000 ps |
| CPU time | 49.57 seconds |
| Started | Jun 24 04:18:03 PM PDT 24 |
| Finished | Jun 24 04:19:38 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-da8647e1-1c17-4991-aa2d-1a4f5930b499 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061790796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4061790796 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.393228821 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7887020000 ps |
| CPU time | 27.3 seconds |
| Started | Jun 24 04:22:11 PM PDT 24 |
| Finished | Jun 24 04:23:03 PM PDT 24 |
| Peak memory | 143884 kb |
| Host | smart-43dee606-27b6-4952-8ed4-df31e5e481c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393228821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.393228821 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1284868427 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7164720000 ps |
| CPU time | 27.91 seconds |
| Started | Jun 24 04:17:12 PM PDT 24 |
| Finished | Jun 24 04:18:05 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-8fece0d7-4d23-4eb7-b244-724e2e2d4e14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284868427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1284868427 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2125803151 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8374960000 ps |
| CPU time | 31.15 seconds |
| Started | Jun 24 04:16:31 PM PDT 24 |
| Finished | Jun 24 04:17:29 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-46ec0a56-d46b-4870-b254-38c8ea4aa4b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125803151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2125803151 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2445183236 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15333220000 ps |
| CPU time | 55.62 seconds |
| Started | Jun 24 04:17:36 PM PDT 24 |
| Finished | Jun 24 04:19:22 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-10a95652-7530-4f92-a600-e5024ca278f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445183236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2445183236 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.959178588 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7040720000 ps |
| CPU time | 27.8 seconds |
| Started | Jun 24 04:18:06 PM PDT 24 |
| Finished | Jun 24 04:18:59 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-aaca9f6b-72ba-4189-96bb-b522f687983f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959178588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.959178588 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3750485399 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7105200000 ps |
| CPU time | 27.23 seconds |
| Started | Jun 24 04:17:14 PM PDT 24 |
| Finished | Jun 24 04:18:06 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-c699ee27-aed2-4b6c-9ba6-6d494378dd9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750485399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3750485399 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2188759767 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11256720000 ps |
| CPU time | 36.57 seconds |
| Started | Jun 24 04:21:37 PM PDT 24 |
| Finished | Jun 24 04:22:44 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-fdce118a-583a-4ba3-8f9d-9fb2c4de7361 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188759767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2188759767 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4039236196 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3948780000 ps |
| CPU time | 14.35 seconds |
| Started | Jun 24 04:22:04 PM PDT 24 |
| Finished | Jun 24 04:22:31 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-d2caf40e-d645-4bd6-8596-7ba340de41f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039236196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4039236196 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3770974659 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10310600000 ps |
| CPU time | 34.64 seconds |
| Started | Jun 24 04:22:10 PM PDT 24 |
| Finished | Jun 24 04:23:16 PM PDT 24 |
| Peak memory | 143172 kb |
| Host | smart-6eef503b-9bc8-4be1-9c7a-15d601dc9835 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770974659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3770974659 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1541303099 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14275500000 ps |
| CPU time | 46.31 seconds |
| Started | Jun 24 04:21:37 PM PDT 24 |
| Finished | Jun 24 04:23:02 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-5b4b4a16-f56f-40aa-85dc-d9dbf162ae76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1541303099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1541303099 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.313258655 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4210420000 ps |
| CPU time | 16.03 seconds |
| Started | Jun 24 04:19:14 PM PDT 24 |
| Finished | Jun 24 04:19:45 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-b19eaee0-16d4-4baf-a8f4-b3944dc4b4db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313258655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.313258655 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1226548952 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7506340000 ps |
| CPU time | 27.29 seconds |
| Started | Jun 24 04:22:04 PM PDT 24 |
| Finished | Jun 24 04:22:55 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-d2e26b94-7994-4976-bef6-6f330f2233dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226548952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1226548952 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1570543879 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3210360000 ps |
| CPU time | 11.9 seconds |
| Started | Jun 24 04:22:11 PM PDT 24 |
| Finished | Jun 24 04:22:34 PM PDT 24 |
| Peak memory | 144456 kb |
| Host | smart-7ce73d95-93ee-4f95-9018-ba128c3c66da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570543879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1570543879 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.736639265 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8259640000 ps |
| CPU time | 29.54 seconds |
| Started | Jun 24 04:16:21 PM PDT 24 |
| Finished | Jun 24 04:17:17 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-2c4e1345-b054-43f6-8328-24061f062717 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736639265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.736639265 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2783151300 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9921860000 ps |
| CPU time | 39.26 seconds |
| Started | Jun 24 04:17:51 PM PDT 24 |
| Finished | Jun 24 04:19:06 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-c1ecea1e-e95c-4301-8d3e-5a965a081f09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783151300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2783151300 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1081772666 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11040340000 ps |
| CPU time | 37.5 seconds |
| Started | Jun 24 04:18:18 PM PDT 24 |
| Finished | Jun 24 04:19:29 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-b1c78d18-3ec7-4037-88d3-1db92ad9ce6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081772666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1081772666 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1055146945 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6666860000 ps |
| CPU time | 22.47 seconds |
| Started | Jun 24 04:17:10 PM PDT 24 |
| Finished | Jun 24 04:17:53 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-ef914f21-3970-4787-88a1-d015e32bdf8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1055146945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1055146945 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1625012726 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12783780000 ps |
| CPU time | 50.61 seconds |
| Started | Jun 24 04:17:22 PM PDT 24 |
| Finished | Jun 24 04:18:59 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-8f441dda-7294-4d3c-8b9b-b0809859fa70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625012726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1625012726 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3511954477 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11697540000 ps |
| CPU time | 38.01 seconds |
| Started | Jun 24 04:22:16 PM PDT 24 |
| Finished | Jun 24 04:23:27 PM PDT 24 |
| Peak memory | 143980 kb |
| Host | smart-8605dd04-e99d-46e5-a56d-04c94d8f138a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3511954477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3511954477 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2622938558 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6304780000 ps |
| CPU time | 18.73 seconds |
| Started | Jun 24 04:21:58 PM PDT 24 |
| Finished | Jun 24 04:22:33 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-3e0077cb-7ce0-4f91-9eaf-894e37c6e5e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622938558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2622938558 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3376892322 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9787320000 ps |
| CPU time | 33.34 seconds |
| Started | Jun 24 04:17:55 PM PDT 24 |
| Finished | Jun 24 04:18:58 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-8a0b2344-4a06-4032-8c13-ffd5e054b7fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376892322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3376892322 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2041688091 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14010140000 ps |
| CPU time | 50.01 seconds |
| Started | Jun 24 04:22:18 PM PDT 24 |
| Finished | Jun 24 04:23:53 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-dbe7b8ef-1b63-4498-a867-d2ed6f7a0678 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041688091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2041688091 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1602061360 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6421340000 ps |
| CPU time | 25.35 seconds |
| Started | Jun 24 04:22:04 PM PDT 24 |
| Finished | Jun 24 04:22:53 PM PDT 24 |
| Peak memory | 144656 kb |
| Host | smart-ffad6aa4-e199-48e5-a32d-b5aed9386dd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1602061360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1602061360 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1882193289 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4165160000 ps |
| CPU time | 13.34 seconds |
| Started | Jun 24 04:21:56 PM PDT 24 |
| Finished | Jun 24 04:22:21 PM PDT 24 |
| Peak memory | 144344 kb |
| Host | smart-55cdef43-b2dd-4b62-bc21-38df0d244b07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882193289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1882193289 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2961671566 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8225540000 ps |
| CPU time | 28.09 seconds |
| Started | Jun 24 04:16:26 PM PDT 24 |
| Finished | Jun 24 04:17:18 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-719fd1b3-231d-42b1-a995-92bfd115dc69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961671566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2961671566 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1362426097 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15038100000 ps |
| CPU time | 54.49 seconds |
| Started | Jun 24 04:22:03 PM PDT 24 |
| Finished | Jun 24 04:23:47 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-0e5e2df6-7ebc-4ffd-b043-4ea467a24dee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362426097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1362426097 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.18698058 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3271120000 ps |
| CPU time | 11.8 seconds |
| Started | Jun 24 04:18:30 PM PDT 24 |
| Finished | Jun 24 04:18:53 PM PDT 24 |
| Peak memory | 144808 kb |
| Host | smart-c68c8808-d79f-47bc-baef-7a8a36442e66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18698058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.18698058 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.410965639 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5047420000 ps |
| CPU time | 15.88 seconds |
| Started | Jun 24 04:21:48 PM PDT 24 |
| Finished | Jun 24 04:22:18 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-28333d93-391a-47ce-8c7f-554f807c05d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410965639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.410965639 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1945309987 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9503980000 ps |
| CPU time | 32.63 seconds |
| Started | Jun 24 04:22:21 PM PDT 24 |
| Finished | Jun 24 04:23:24 PM PDT 24 |
| Peak memory | 143836 kb |
| Host | smart-da6ab0d9-e877-4689-a59b-967fc4115ea5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945309987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1945309987 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2352267304 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14796300000 ps |
| CPU time | 56.56 seconds |
| Started | Jun 24 04:19:20 PM PDT 24 |
| Finished | Jun 24 04:21:08 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-d2ae1ee8-bd81-47b2-a18f-52d626923fe1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352267304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2352267304 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.750999382 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5201180000 ps |
| CPU time | 21.46 seconds |
| Started | Jun 24 04:17:22 PM PDT 24 |
| Finished | Jun 24 04:18:04 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-7d21a027-c701-41f3-9092-bd52b9654fe1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750999382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.750999382 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.640301166 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6445520000 ps |
| CPU time | 22.57 seconds |
| Started | Jun 24 04:22:21 PM PDT 24 |
| Finished | Jun 24 04:23:05 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-f277f90e-abed-4850-aafa-4c967d890e4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640301166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.640301166 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1173084077 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6049960000 ps |
| CPU time | 24.77 seconds |
| Started | Jun 24 04:20:16 PM PDT 24 |
| Finished | Jun 24 04:21:03 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-c877d569-6c81-486b-b178-6971176d3d77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1173084077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1173084077 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1875668879 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5632080000 ps |
| CPU time | 20.38 seconds |
| Started | Jun 24 04:22:04 PM PDT 24 |
| Finished | Jun 24 04:22:42 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-0c5d0291-ab6d-4d3c-b709-f107bf4ecc7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875668879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1875668879 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.4147112689 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14748560000 ps |
| CPU time | 51.54 seconds |
| Started | Jun 24 04:22:20 PM PDT 24 |
| Finished | Jun 24 04:23:57 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-57fd28cc-a5d6-40fa-8dd6-cb9c30f314e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147112689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4147112689 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3887509201 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13148340000 ps |
| CPU time | 51.05 seconds |
| Started | Jun 24 04:16:19 PM PDT 24 |
| Finished | Jun 24 04:17:56 PM PDT 24 |
| Peak memory | 144004 kb |
| Host | smart-1dc2b9c1-994d-4bdb-bdaa-6e881a9d2aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3887509201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3887509201 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2181533380 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7918640000 ps |
| CPU time | 24.96 seconds |
| Started | Jun 24 04:22:01 PM PDT 24 |
| Finished | Jun 24 04:22:48 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-84076595-1519-4c13-9639-4cd1b05f7aca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181533380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2181533380 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.4075291625 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12075120000 ps |
| CPU time | 41.56 seconds |
| Started | Jun 24 04:16:44 PM PDT 24 |
| Finished | Jun 24 04:18:01 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-1159ec49-392b-477b-ad09-c7887eaf8819 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075291625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.4075291625 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1618677832 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10927500000 ps |
| CPU time | 40.76 seconds |
| Started | Jun 24 04:16:43 PM PDT 24 |
| Finished | Jun 24 04:18:00 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-57cea920-7bbd-47d8-88c3-248dced4f06b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618677832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1618677832 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2423515258 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5454140000 ps |
| CPU time | 20.28 seconds |
| Started | Jun 24 04:16:31 PM PDT 24 |
| Finished | Jun 24 04:17:09 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-0f108cea-56b3-4fca-8c2a-b67a70710dad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423515258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2423515258 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |