| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/13.prim_present_test.911007957 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2429148123 |
| /workspace/coverage/default/1.prim_present_test.3047338173 |
| /workspace/coverage/default/10.prim_present_test.1706333601 |
| /workspace/coverage/default/11.prim_present_test.1604910452 |
| /workspace/coverage/default/12.prim_present_test.550946403 |
| /workspace/coverage/default/14.prim_present_test.4256729225 |
| /workspace/coverage/default/15.prim_present_test.1041230718 |
| /workspace/coverage/default/16.prim_present_test.1847252657 |
| /workspace/coverage/default/17.prim_present_test.2675744205 |
| /workspace/coverage/default/18.prim_present_test.2716787328 |
| /workspace/coverage/default/19.prim_present_test.2481245925 |
| /workspace/coverage/default/2.prim_present_test.1465240478 |
| /workspace/coverage/default/20.prim_present_test.2019842618 |
| /workspace/coverage/default/21.prim_present_test.820331318 |
| /workspace/coverage/default/22.prim_present_test.36793133 |
| /workspace/coverage/default/23.prim_present_test.2782614332 |
| /workspace/coverage/default/24.prim_present_test.3577771552 |
| /workspace/coverage/default/25.prim_present_test.2043776864 |
| /workspace/coverage/default/26.prim_present_test.1833821734 |
| /workspace/coverage/default/27.prim_present_test.976560041 |
| /workspace/coverage/default/28.prim_present_test.3314769984 |
| /workspace/coverage/default/29.prim_present_test.979778051 |
| /workspace/coverage/default/3.prim_present_test.3513025267 |
| /workspace/coverage/default/30.prim_present_test.2773135046 |
| /workspace/coverage/default/31.prim_present_test.860743745 |
| /workspace/coverage/default/32.prim_present_test.3244662362 |
| /workspace/coverage/default/33.prim_present_test.1371317363 |
| /workspace/coverage/default/34.prim_present_test.1510591561 |
| /workspace/coverage/default/35.prim_present_test.140371671 |
| /workspace/coverage/default/36.prim_present_test.4097591650 |
| /workspace/coverage/default/37.prim_present_test.2009679408 |
| /workspace/coverage/default/38.prim_present_test.2697959855 |
| /workspace/coverage/default/39.prim_present_test.505611747 |
| /workspace/coverage/default/4.prim_present_test.3741718743 |
| /workspace/coverage/default/40.prim_present_test.165543541 |
| /workspace/coverage/default/41.prim_present_test.1619516001 |
| /workspace/coverage/default/42.prim_present_test.1311731735 |
| /workspace/coverage/default/43.prim_present_test.2025998849 |
| /workspace/coverage/default/44.prim_present_test.2411506046 |
| /workspace/coverage/default/45.prim_present_test.3389745310 |
| /workspace/coverage/default/46.prim_present_test.4012575235 |
| /workspace/coverage/default/47.prim_present_test.3728639257 |
| /workspace/coverage/default/48.prim_present_test.3364572687 |
| /workspace/coverage/default/49.prim_present_test.739235951 |
| /workspace/coverage/default/5.prim_present_test.3954186573 |
| /workspace/coverage/default/6.prim_present_test.4283014461 |
| /workspace/coverage/default/7.prim_present_test.2491355608 |
| /workspace/coverage/default/8.prim_present_test.3542303748 |
| /workspace/coverage/default/9.prim_present_test.173842828 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/30.prim_present_test.2773135046 | Jun 25 04:41:36 PM PDT 24 | Jun 25 04:42:30 PM PDT 24 | 6384760000 ps | ||
| T2 | /workspace/coverage/default/19.prim_present_test.2481245925 | Jun 25 04:41:37 PM PDT 24 | Jun 25 04:41:58 PM PDT 24 | 3644360000 ps | ||
| T3 | /workspace/coverage/default/29.prim_present_test.979778051 | Jun 25 04:41:39 PM PDT 24 | Jun 25 04:42:23 PM PDT 24 | 6040040000 ps | ||
| T4 | /workspace/coverage/default/47.prim_present_test.3728639257 | Jun 25 04:41:42 PM PDT 24 | Jun 25 04:43:05 PM PDT 24 | 11016780000 ps | ||
| T5 | /workspace/coverage/default/45.prim_present_test.3389745310 | Jun 25 04:41:41 PM PDT 24 | Jun 25 04:42:49 PM PDT 24 | 9694940000 ps | ||
| T6 | /workspace/coverage/default/43.prim_present_test.2025998849 | Jun 25 04:41:44 PM PDT 24 | Jun 25 04:43:10 PM PDT 24 | 11797360000 ps | ||
| T7 | /workspace/coverage/default/9.prim_present_test.173842828 | Jun 25 04:41:38 PM PDT 24 | Jun 25 04:43:09 PM PDT 24 | 12338000000 ps | ||
| T8 | /workspace/coverage/default/32.prim_present_test.3244662362 | Jun 25 04:41:42 PM PDT 24 | Jun 25 04:42:20 PM PDT 24 | 5668660000 ps | ||
| T9 | /workspace/coverage/default/13.prim_present_test.911007957 | Jun 25 04:41:30 PM PDT 24 | Jun 25 04:42:54 PM PDT 24 | 11508440000 ps | ||
| T10 | /workspace/coverage/default/44.prim_present_test.2411506046 | Jun 25 04:41:45 PM PDT 24 | Jun 25 04:42:42 PM PDT 24 | 6640820000 ps | ||
| T11 | /workspace/coverage/default/27.prim_present_test.976560041 | Jun 25 04:41:44 PM PDT 24 | Jun 25 04:43:11 PM PDT 24 | 10594560000 ps | ||
| T12 | /workspace/coverage/default/11.prim_present_test.1604910452 | Jun 25 04:41:28 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 7426980000 ps | ||
| T13 | /workspace/coverage/default/0.prim_present_test.2429148123 | Jun 25 04:41:25 PM PDT 24 | Jun 25 04:42:23 PM PDT 24 | 7674360000 ps | ||
| T14 | /workspace/coverage/default/10.prim_present_test.1706333601 | Jun 25 04:41:26 PM PDT 24 | Jun 25 04:43:08 PM PDT 24 | 13295280000 ps | ||
| T15 | /workspace/coverage/default/8.prim_present_test.3542303748 | Jun 25 04:41:28 PM PDT 24 | Jun 25 04:42:48 PM PDT 24 | 10657800000 ps | ||
| T16 | /workspace/coverage/default/20.prim_present_test.2019842618 | Jun 25 04:41:43 PM PDT 24 | Jun 25 04:42:27 PM PDT 24 | 5910460000 ps | ||
| T17 | /workspace/coverage/default/14.prim_present_test.4256729225 | Jun 25 04:41:29 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 7294300000 ps | ||
| T18 | /workspace/coverage/default/23.prim_present_test.2782614332 | Jun 25 04:41:37 PM PDT 24 | Jun 25 04:42:30 PM PDT 24 | 8015360000 ps | ||
| T19 | /workspace/coverage/default/39.prim_present_test.505611747 | Jun 25 04:41:40 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 5080900000 ps | ||
| T20 | /workspace/coverage/default/7.prim_present_test.2491355608 | Jun 25 04:41:36 PM PDT 24 | Jun 25 04:42:33 PM PDT 24 | 7428220000 ps | ||
| T21 | /workspace/coverage/default/33.prim_present_test.1371317363 | Jun 25 04:41:37 PM PDT 24 | Jun 25 04:43:04 PM PDT 24 | 12586620000 ps | ||
| T22 | /workspace/coverage/default/16.prim_present_test.1847252657 | Jun 25 04:41:38 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 4992240000 ps | ||
| T23 | /workspace/coverage/default/17.prim_present_test.2675744205 | Jun 25 04:41:28 PM PDT 24 | Jun 25 04:42:43 PM PDT 24 | 12218340000 ps | ||
| T24 | /workspace/coverage/default/22.prim_present_test.36793133 | Jun 25 04:41:40 PM PDT 24 | Jun 25 04:42:46 PM PDT 24 | 9902020000 ps | ||
| T25 | /workspace/coverage/default/28.prim_present_test.3314769984 | Jun 25 04:41:40 PM PDT 24 | Jun 25 04:43:27 PM PDT 24 | 13776400000 ps | ||
| T26 | /workspace/coverage/default/41.prim_present_test.1619516001 | Jun 25 04:42:30 PM PDT 24 | Jun 25 04:43:48 PM PDT 24 | 12440920000 ps | ||
| T27 | /workspace/coverage/default/35.prim_present_test.140371671 | Jun 25 04:41:44 PM PDT 24 | Jun 25 04:42:29 PM PDT 24 | 7098380000 ps | ||
| T28 | /workspace/coverage/default/12.prim_present_test.550946403 | Jun 25 04:41:38 PM PDT 24 | Jun 25 04:43:17 PM PDT 24 | 13815460000 ps | ||
| T29 | /workspace/coverage/default/4.prim_present_test.3741718743 | Jun 25 04:41:35 PM PDT 24 | Jun 25 04:42:54 PM PDT 24 | 11199680000 ps | ||
| T30 | /workspace/coverage/default/40.prim_present_test.165543541 | Jun 25 04:41:41 PM PDT 24 | Jun 25 04:42:14 PM PDT 24 | 4591100000 ps | ||
| T31 | /workspace/coverage/default/5.prim_present_test.3954186573 | Jun 25 04:41:28 PM PDT 24 | Jun 25 04:42:45 PM PDT 24 | 12483080000 ps | ||
| T32 | /workspace/coverage/default/26.prim_present_test.1833821734 | Jun 25 04:41:45 PM PDT 24 | Jun 25 04:43:08 PM PDT 24 | 10146920000 ps | ||
| T33 | /workspace/coverage/default/6.prim_present_test.4283014461 | Jun 25 04:41:31 PM PDT 24 | Jun 25 04:42:57 PM PDT 24 | 13801200000 ps | ||
| T34 | /workspace/coverage/default/15.prim_present_test.1041230718 | Jun 25 04:41:33 PM PDT 24 | Jun 25 04:42:38 PM PDT 24 | 9431440000 ps | ||
| T35 | /workspace/coverage/default/21.prim_present_test.820331318 | Jun 25 04:42:20 PM PDT 24 | Jun 25 04:42:46 PM PDT 24 | 4429280000 ps | ||
| T36 | /workspace/coverage/default/25.prim_present_test.2043776864 | Jun 25 04:41:34 PM PDT 24 | Jun 25 04:42:54 PM PDT 24 | 10246740000 ps | ||
| T37 | /workspace/coverage/default/34.prim_present_test.1510591561 | Jun 25 04:42:20 PM PDT 24 | Jun 25 04:44:04 PM PDT 24 | 14173200000 ps | ||
| T38 | /workspace/coverage/default/24.prim_present_test.3577771552 | Jun 25 04:41:37 PM PDT 24 | Jun 25 04:41:56 PM PDT 24 | 3163240000 ps | ||
| T39 | /workspace/coverage/default/38.prim_present_test.2697959855 | Jun 25 04:41:44 PM PDT 24 | Jun 25 04:42:31 PM PDT 24 | 5636420000 ps | ||
| T40 | /workspace/coverage/default/46.prim_present_test.4012575235 | Jun 25 04:41:40 PM PDT 24 | Jun 25 04:42:44 PM PDT 24 | 8708520000 ps | ||
| T41 | /workspace/coverage/default/3.prim_present_test.3513025267 | Jun 25 04:41:25 PM PDT 24 | Jun 25 04:42:52 PM PDT 24 | 11632440000 ps | ||
| T42 | /workspace/coverage/default/18.prim_present_test.2716787328 | Jun 25 04:41:30 PM PDT 24 | Jun 25 04:43:17 PM PDT 24 | 15095140000 ps | ||
| T43 | /workspace/coverage/default/36.prim_present_test.4097591650 | Jun 25 04:41:45 PM PDT 24 | Jun 25 04:43:03 PM PDT 24 | 11605160000 ps | ||
| T44 | /workspace/coverage/default/31.prim_present_test.860743745 | Jun 25 04:41:37 PM PDT 24 | Jun 25 04:42:44 PM PDT 24 | 8947220000 ps | ||
| T45 | /workspace/coverage/default/48.prim_present_test.3364572687 | Jun 25 04:41:45 PM PDT 24 | Jun 25 04:42:18 PM PDT 24 | 3695200000 ps | ||
| T46 | /workspace/coverage/default/49.prim_present_test.739235951 | Jun 25 04:41:39 PM PDT 24 | Jun 25 04:42:53 PM PDT 24 | 9592640000 ps | ||
| T47 | /workspace/coverage/default/1.prim_present_test.3047338173 | Jun 25 04:41:25 PM PDT 24 | Jun 25 04:41:45 PM PDT 24 | 3439140000 ps | ||
| T48 | /workspace/coverage/default/42.prim_present_test.1311731735 | Jun 25 04:41:40 PM PDT 24 | Jun 25 04:42:11 PM PDT 24 | 4000860000 ps | ||
| T49 | /workspace/coverage/default/2.prim_present_test.1465240478 | Jun 25 04:41:28 PM PDT 24 | Jun 25 04:42:09 PM PDT 24 | 5660600000 ps | ||
| T50 | /workspace/coverage/default/37.prim_present_test.2009679408 | Jun 25 04:41:37 PM PDT 24 | Jun 25 04:43:16 PM PDT 24 | 15160240000 ps |
| Test location | /workspace/coverage/default/13.prim_present_test.911007957 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11508440000 ps |
| CPU time | 43.11 seconds |
| Started | Jun 25 04:41:30 PM PDT 24 |
| Finished | Jun 25 04:42:54 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-7b44c6db-0a03-4bcb-8750-5c8cb49a26f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=911007957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.911007957 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2429148123 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7674360000 ps |
| CPU time | 30.17 seconds |
| Started | Jun 25 04:41:25 PM PDT 24 |
| Finished | Jun 25 04:42:23 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-ea4427ae-a483-4d3a-a22e-e7857f298402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429148123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2429148123 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3047338173 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3439140000 ps |
| CPU time | 10.48 seconds |
| Started | Jun 25 04:41:25 PM PDT 24 |
| Finished | Jun 25 04:41:45 PM PDT 24 |
| Peak memory | 144368 kb |
| Host | smart-4ec31aec-53cd-4431-a16c-5d997ec97702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047338173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3047338173 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1706333601 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13295280000 ps |
| CPU time | 52.63 seconds |
| Started | Jun 25 04:41:26 PM PDT 24 |
| Finished | Jun 25 04:43:08 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-5abeeeb2-0e57-4a2c-9d09-c5c744e15149 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706333601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1706333601 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1604910452 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7426980000 ps |
| CPU time | 26.88 seconds |
| Started | Jun 25 04:41:28 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 143984 kb |
| Host | smart-dabd6795-20cd-4feb-80d3-9c3abb4e7f07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604910452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1604910452 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.550946403 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13815460000 ps |
| CPU time | 51.29 seconds |
| Started | Jun 25 04:41:38 PM PDT 24 |
| Finished | Jun 25 04:43:17 PM PDT 24 |
| Peak memory | 143668 kb |
| Host | smart-606bee41-006c-487a-86c0-d9d73cd447c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550946403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.550946403 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4256729225 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7294300000 ps |
| CPU time | 26.16 seconds |
| Started | Jun 25 04:41:29 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-e7d85d6e-b449-4b9d-a606-f4e0af0456ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4256729225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4256729225 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1041230718 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9431440000 ps |
| CPU time | 33.93 seconds |
| Started | Jun 25 04:41:33 PM PDT 24 |
| Finished | Jun 25 04:42:38 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-7fff92fe-5067-4312-aef3-dc41930bd31b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1041230718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1041230718 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1847252657 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4992240000 ps |
| CPU time | 21.07 seconds |
| Started | Jun 25 04:41:38 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 144612 kb |
| Host | smart-53449da8-7ebe-4495-8c05-c9cac6586ddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1847252657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1847252657 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2675744205 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12218340000 ps |
| CPU time | 40.1 seconds |
| Started | Jun 25 04:41:28 PM PDT 24 |
| Finished | Jun 25 04:42:43 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-e7e2007e-a3c8-40af-b59c-8fd5f1a1d8bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2675744205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2675744205 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2716787328 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15095140000 ps |
| CPU time | 55.45 seconds |
| Started | Jun 25 04:41:30 PM PDT 24 |
| Finished | Jun 25 04:43:17 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-92fcacd9-4a29-4a6e-ba17-e5951e3f0323 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716787328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2716787328 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2481245925 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3644360000 ps |
| CPU time | 10.87 seconds |
| Started | Jun 25 04:41:37 PM PDT 24 |
| Finished | Jun 25 04:41:58 PM PDT 24 |
| Peak memory | 143876 kb |
| Host | smart-aa769d8c-b34a-4c70-9112-b8eee225a0c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481245925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2481245925 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1465240478 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5660600000 ps |
| CPU time | 21.24 seconds |
| Started | Jun 25 04:41:28 PM PDT 24 |
| Finished | Jun 25 04:42:09 PM PDT 24 |
| Peak memory | 144516 kb |
| Host | smart-4605607d-526b-425b-b034-e78aa1555473 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465240478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1465240478 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2019842618 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5910460000 ps |
| CPU time | 22.56 seconds |
| Started | Jun 25 04:41:43 PM PDT 24 |
| Finished | Jun 25 04:42:27 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-e71cb1c7-e4c0-4ecc-8f4c-b5ba87235943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019842618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2019842618 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.820331318 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4429280000 ps |
| CPU time | 12.71 seconds |
| Started | Jun 25 04:42:20 PM PDT 24 |
| Finished | Jun 25 04:42:46 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-b3c15100-4002-478f-aecf-8c2d07a4df98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820331318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.820331318 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.36793133 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9902020000 ps |
| CPU time | 34.32 seconds |
| Started | Jun 25 04:41:40 PM PDT 24 |
| Finished | Jun 25 04:42:46 PM PDT 24 |
| Peak memory | 144604 kb |
| Host | smart-4f0c5c17-bfa0-4b38-8116-808eafce8c65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36793133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.36793133 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2782614332 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8015360000 ps |
| CPU time | 27.87 seconds |
| Started | Jun 25 04:41:37 PM PDT 24 |
| Finished | Jun 25 04:42:30 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-fc925cb1-1a59-43d5-b765-b7ce3abcf623 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782614332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2782614332 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3577771552 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3163240000 ps |
| CPU time | 9.58 seconds |
| Started | Jun 25 04:41:37 PM PDT 24 |
| Finished | Jun 25 04:41:56 PM PDT 24 |
| Peak memory | 144344 kb |
| Host | smart-72d8b226-0185-41e2-8f40-dc27dfe1c9ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577771552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3577771552 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2043776864 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10246740000 ps |
| CPU time | 41.34 seconds |
| Started | Jun 25 04:41:34 PM PDT 24 |
| Finished | Jun 25 04:42:54 PM PDT 24 |
| Peak memory | 143980 kb |
| Host | smart-fc56c3c6-cc89-463b-9785-6c84aee5ba96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043776864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2043776864 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1833821734 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10146920000 ps |
| CPU time | 42.05 seconds |
| Started | Jun 25 04:41:45 PM PDT 24 |
| Finished | Jun 25 04:43:08 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-45de9445-bb67-4ce4-a022-1a040bd816e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833821734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1833821734 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.976560041 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10594560000 ps |
| CPU time | 44.5 seconds |
| Started | Jun 25 04:41:44 PM PDT 24 |
| Finished | Jun 25 04:43:11 PM PDT 24 |
| Peak memory | 143876 kb |
| Host | smart-fb1e2e4d-a2ed-454b-afac-1912c09095a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976560041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.976560041 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3314769984 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13776400000 ps |
| CPU time | 55.14 seconds |
| Started | Jun 25 04:41:40 PM PDT 24 |
| Finished | Jun 25 04:43:27 PM PDT 24 |
| Peak memory | 144516 kb |
| Host | smart-f7fcf8f2-1e3c-40d5-9781-0ab6cdff0ace |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314769984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3314769984 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.979778051 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6040040000 ps |
| CPU time | 22.55 seconds |
| Started | Jun 25 04:41:39 PM PDT 24 |
| Finished | Jun 25 04:42:23 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-762013ae-e302-4f63-b987-0015bf5ac1af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979778051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.979778051 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3513025267 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11632440000 ps |
| CPU time | 45.3 seconds |
| Started | Jun 25 04:41:25 PM PDT 24 |
| Finished | Jun 25 04:42:52 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-02b7e7a4-fa2b-4627-93ca-63e335f27a70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513025267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3513025267 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2773135046 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6384760000 ps |
| CPU time | 27.42 seconds |
| Started | Jun 25 04:41:36 PM PDT 24 |
| Finished | Jun 25 04:42:30 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-e3800313-4135-4322-b4f7-12cf36bcf198 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773135046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2773135046 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.860743745 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8947220000 ps |
| CPU time | 35.22 seconds |
| Started | Jun 25 04:41:37 PM PDT 24 |
| Finished | Jun 25 04:42:44 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-a4a0bc65-f96f-4b85-8f9e-20b2b22136a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860743745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.860743745 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3244662362 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5668660000 ps |
| CPU time | 19.99 seconds |
| Started | Jun 25 04:41:42 PM PDT 24 |
| Finished | Jun 25 04:42:20 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-132ddedf-ecde-4033-9ae8-508aae193225 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244662362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3244662362 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1371317363 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12586620000 ps |
| CPU time | 44.91 seconds |
| Started | Jun 25 04:41:37 PM PDT 24 |
| Finished | Jun 25 04:43:04 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-fa629904-6913-4504-9a6c-24a4144f3b34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371317363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1371317363 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1510591561 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 14173200000 ps |
| CPU time | 53.62 seconds |
| Started | Jun 25 04:42:20 PM PDT 24 |
| Finished | Jun 25 04:44:04 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-41ddbec2-e0db-4f17-8b8a-a4d811a6bd54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510591561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1510591561 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.140371671 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7098380000 ps |
| CPU time | 24.09 seconds |
| Started | Jun 25 04:41:44 PM PDT 24 |
| Finished | Jun 25 04:42:29 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-667d314d-4e0b-4aac-bf6d-942abf91ea2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140371671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.140371671 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4097591650 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11605160000 ps |
| CPU time | 40.44 seconds |
| Started | Jun 25 04:41:45 PM PDT 24 |
| Finished | Jun 25 04:43:03 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-50f011ee-d6b9-48de-8b29-c1b3113ad0c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097591650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4097591650 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2009679408 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15160240000 ps |
| CPU time | 51.99 seconds |
| Started | Jun 25 04:41:37 PM PDT 24 |
| Finished | Jun 25 04:43:16 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-771332c7-4d32-446f-9bf0-beaaec750733 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009679408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2009679408 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2697959855 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5636420000 ps |
| CPU time | 24.52 seconds |
| Started | Jun 25 04:41:44 PM PDT 24 |
| Finished | Jun 25 04:42:31 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-02f3b8a2-7d23-4b16-9021-11511cdaf1cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697959855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2697959855 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.505611747 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5080900000 ps |
| CPU time | 19.73 seconds |
| Started | Jun 25 04:41:40 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 144048 kb |
| Host | smart-b0cb02e2-0515-45f9-a95e-9ffa905d1fee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505611747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.505611747 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3741718743 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11199680000 ps |
| CPU time | 40.54 seconds |
| Started | Jun 25 04:41:35 PM PDT 24 |
| Finished | Jun 25 04:42:54 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-470e6452-d2fa-42b1-896c-b8be82c69b85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3741718743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3741718743 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.165543541 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4591100000 ps |
| CPU time | 16.8 seconds |
| Started | Jun 25 04:41:41 PM PDT 24 |
| Finished | Jun 25 04:42:14 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-532fb23f-fa84-4db9-8e79-dcee887e0a1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165543541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.165543541 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1619516001 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12440920000 ps |
| CPU time | 40.61 seconds |
| Started | Jun 25 04:42:30 PM PDT 24 |
| Finished | Jun 25 04:43:48 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-8da1f6c7-7ec6-4968-bad9-67a5ae8f5f18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619516001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1619516001 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1311731735 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4000860000 ps |
| CPU time | 16.43 seconds |
| Started | Jun 25 04:41:40 PM PDT 24 |
| Finished | Jun 25 04:42:11 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-5894ea1c-57d8-475e-b157-1e0d13d4fb5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311731735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1311731735 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2025998849 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11797360000 ps |
| CPU time | 45.1 seconds |
| Started | Jun 25 04:41:44 PM PDT 24 |
| Finished | Jun 25 04:43:10 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-386b4b60-495a-48ba-8ec7-e62ed17651cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025998849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2025998849 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2411506046 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6640820000 ps |
| CPU time | 28.94 seconds |
| Started | Jun 25 04:41:45 PM PDT 24 |
| Finished | Jun 25 04:42:42 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-8d507124-8e4d-41d4-bcff-66212975f0f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411506046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2411506046 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3389745310 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9694940000 ps |
| CPU time | 35.96 seconds |
| Started | Jun 25 04:41:41 PM PDT 24 |
| Finished | Jun 25 04:42:49 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-daf73292-33c7-42dd-8dbc-9f7153e9cbe2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389745310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3389745310 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4012575235 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8708520000 ps |
| CPU time | 32.78 seconds |
| Started | Jun 25 04:41:40 PM PDT 24 |
| Finished | Jun 25 04:42:44 PM PDT 24 |
| Peak memory | 144004 kb |
| Host | smart-35060ebf-685f-4c26-b740-9e030dcb3c8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012575235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4012575235 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3728639257 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11016780000 ps |
| CPU time | 43.06 seconds |
| Started | Jun 25 04:41:42 PM PDT 24 |
| Finished | Jun 25 04:43:05 PM PDT 24 |
| Peak memory | 143628 kb |
| Host | smart-88065f25-ef4e-48ce-8441-85a145830470 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728639257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3728639257 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3364572687 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3695200000 ps |
| CPU time | 16.55 seconds |
| Started | Jun 25 04:41:45 PM PDT 24 |
| Finished | Jun 25 04:42:18 PM PDT 24 |
| Peak memory | 144584 kb |
| Host | smart-03283001-886b-41f0-8468-f4b6d9ee02da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3364572687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3364572687 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.739235951 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9592640000 ps |
| CPU time | 38.21 seconds |
| Started | Jun 25 04:41:39 PM PDT 24 |
| Finished | Jun 25 04:42:53 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-997fc3ad-c566-41a8-8a49-448be1203509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739235951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.739235951 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3954186573 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12483080000 ps |
| CPU time | 40.94 seconds |
| Started | Jun 25 04:41:28 PM PDT 24 |
| Finished | Jun 25 04:42:45 PM PDT 24 |
| Peak memory | 144508 kb |
| Host | smart-3fca70a8-fdea-4dd7-8ed1-a4115ec4addf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954186573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3954186573 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4283014461 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13801200000 ps |
| CPU time | 45.88 seconds |
| Started | Jun 25 04:41:31 PM PDT 24 |
| Finished | Jun 25 04:42:57 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-77023fe9-2415-4766-b677-f0c19ba0d796 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283014461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4283014461 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2491355608 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7428220000 ps |
| CPU time | 29.47 seconds |
| Started | Jun 25 04:41:36 PM PDT 24 |
| Finished | Jun 25 04:42:33 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-60f2ad39-c89e-49ab-87ef-022fd521efae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491355608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2491355608 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3542303748 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10657800000 ps |
| CPU time | 40.98 seconds |
| Started | Jun 25 04:41:28 PM PDT 24 |
| Finished | Jun 25 04:42:48 PM PDT 24 |
| Peak memory | 144016 kb |
| Host | smart-54565440-eee7-4316-b6e7-de220e8a8268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542303748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3542303748 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.173842828 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12338000000 ps |
| CPU time | 47.18 seconds |
| Started | Jun 25 04:41:38 PM PDT 24 |
| Finished | Jun 25 04:43:09 PM PDT 24 |
| Peak memory | 143624 kb |
| Host | smart-9030c982-4b27-4ca8-b192-8bc50f337ba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173842828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.173842828 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |