| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/14.prim_present_test.1092860084 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.210304781 |
| /workspace/coverage/default/1.prim_present_test.766647820 |
| /workspace/coverage/default/10.prim_present_test.1489782729 |
| /workspace/coverage/default/11.prim_present_test.575120260 |
| /workspace/coverage/default/12.prim_present_test.2511449079 |
| /workspace/coverage/default/13.prim_present_test.302553638 |
| /workspace/coverage/default/15.prim_present_test.1645189209 |
| /workspace/coverage/default/16.prim_present_test.3565416276 |
| /workspace/coverage/default/17.prim_present_test.1292620962 |
| /workspace/coverage/default/18.prim_present_test.41168542 |
| /workspace/coverage/default/19.prim_present_test.3898393576 |
| /workspace/coverage/default/2.prim_present_test.1768462105 |
| /workspace/coverage/default/20.prim_present_test.2930870561 |
| /workspace/coverage/default/21.prim_present_test.2419221077 |
| /workspace/coverage/default/22.prim_present_test.2126628890 |
| /workspace/coverage/default/23.prim_present_test.3659566231 |
| /workspace/coverage/default/24.prim_present_test.3459454878 |
| /workspace/coverage/default/25.prim_present_test.4101207748 |
| /workspace/coverage/default/26.prim_present_test.476109617 |
| /workspace/coverage/default/27.prim_present_test.1022628385 |
| /workspace/coverage/default/28.prim_present_test.1159744666 |
| /workspace/coverage/default/29.prim_present_test.418731881 |
| /workspace/coverage/default/3.prim_present_test.3532240669 |
| /workspace/coverage/default/30.prim_present_test.2139893352 |
| /workspace/coverage/default/31.prim_present_test.2977427670 |
| /workspace/coverage/default/32.prim_present_test.1910849165 |
| /workspace/coverage/default/33.prim_present_test.2507662312 |
| /workspace/coverage/default/34.prim_present_test.780794737 |
| /workspace/coverage/default/35.prim_present_test.1150188021 |
| /workspace/coverage/default/36.prim_present_test.7586144 |
| /workspace/coverage/default/37.prim_present_test.4205323230 |
| /workspace/coverage/default/38.prim_present_test.1940287160 |
| /workspace/coverage/default/39.prim_present_test.2195815041 |
| /workspace/coverage/default/4.prim_present_test.3918148920 |
| /workspace/coverage/default/40.prim_present_test.841300757 |
| /workspace/coverage/default/41.prim_present_test.1682471773 |
| /workspace/coverage/default/42.prim_present_test.1070465902 |
| /workspace/coverage/default/43.prim_present_test.2545731084 |
| /workspace/coverage/default/44.prim_present_test.2682060928 |
| /workspace/coverage/default/45.prim_present_test.687804886 |
| /workspace/coverage/default/46.prim_present_test.4054637188 |
| /workspace/coverage/default/47.prim_present_test.2894876709 |
| /workspace/coverage/default/48.prim_present_test.1246761482 |
| /workspace/coverage/default/49.prim_present_test.451777501 |
| /workspace/coverage/default/5.prim_present_test.1799159306 |
| /workspace/coverage/default/6.prim_present_test.7126452 |
| /workspace/coverage/default/7.prim_present_test.4286414529 |
| /workspace/coverage/default/8.prim_present_test.1951911316 |
| /workspace/coverage/default/9.prim_present_test.1278954366 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/44.prim_present_test.2682060928 | Jun 26 04:18:47 PM PDT 24 | Jun 26 04:19:15 PM PDT 24 | 4031240000 ps | ||
| T2 | /workspace/coverage/default/6.prim_present_test.7126452 | Jun 26 04:18:58 PM PDT 24 | Jun 26 04:20:16 PM PDT 24 | 13137800000 ps | ||
| T3 | /workspace/coverage/default/49.prim_present_test.451777501 | Jun 26 04:19:59 PM PDT 24 | Jun 26 04:21:24 PM PDT 24 | 12055900000 ps | ||
| T4 | /workspace/coverage/default/19.prim_present_test.3898393576 | Jun 26 04:23:01 PM PDT 24 | Jun 26 04:24:30 PM PDT 24 | 13681540000 ps | ||
| T5 | /workspace/coverage/default/27.prim_present_test.1022628385 | Jun 26 04:22:01 PM PDT 24 | Jun 26 04:22:51 PM PDT 24 | 7519360000 ps | ||
| T6 | /workspace/coverage/default/14.prim_present_test.1092860084 | Jun 26 04:20:42 PM PDT 24 | Jun 26 04:22:00 PM PDT 24 | 12223300000 ps | ||
| T7 | /workspace/coverage/default/34.prim_present_test.780794737 | Jun 26 04:21:01 PM PDT 24 | Jun 26 04:22:34 PM PDT 24 | 14672920000 ps | ||
| T8 | /workspace/coverage/default/7.prim_present_test.4286414529 | Jun 26 04:17:58 PM PDT 24 | Jun 26 04:19:10 PM PDT 24 | 10722280000 ps | ||
| T9 | /workspace/coverage/default/36.prim_present_test.7586144 | Jun 26 04:23:34 PM PDT 24 | Jun 26 04:24:47 PM PDT 24 | 11672120000 ps | ||
| T10 | /workspace/coverage/default/8.prim_present_test.1951911316 | Jun 26 04:19:55 PM PDT 24 | Jun 26 04:21:07 PM PDT 24 | 9389280000 ps | ||
| T11 | /workspace/coverage/default/13.prim_present_test.302553638 | Jun 26 04:22:57 PM PDT 24 | Jun 26 04:23:41 PM PDT 24 | 7825640000 ps | ||
| T12 | /workspace/coverage/default/4.prim_present_test.3918148920 | Jun 26 04:17:47 PM PDT 24 | Jun 26 04:19:28 PM PDT 24 | 14525980000 ps | ||
| T13 | /workspace/coverage/default/35.prim_present_test.1150188021 | Jun 26 04:23:20 PM PDT 24 | Jun 26 04:24:39 PM PDT 24 | 13992780000 ps | ||
| T14 | /workspace/coverage/default/16.prim_present_test.3565416276 | Jun 26 04:22:56 PM PDT 24 | Jun 26 04:23:21 PM PDT 24 | 4720060000 ps | ||
| T15 | /workspace/coverage/default/2.prim_present_test.1768462105 | Jun 26 04:18:58 PM PDT 24 | Jun 26 04:20:15 PM PDT 24 | 12957380000 ps | ||
| T16 | /workspace/coverage/default/28.prim_present_test.1159744666 | Jun 26 04:23:55 PM PDT 24 | Jun 26 04:24:58 PM PDT 24 | 10683840000 ps | ||
| T17 | /workspace/coverage/default/24.prim_present_test.3459454878 | Jun 26 04:19:23 PM PDT 24 | Jun 26 04:20:21 PM PDT 24 | 7739460000 ps | ||
| T18 | /workspace/coverage/default/25.prim_present_test.4101207748 | Jun 26 04:21:55 PM PDT 24 | Jun 26 04:23:29 PM PDT 24 | 12925140000 ps | ||
| T19 | /workspace/coverage/default/43.prim_present_test.2545731084 | Jun 26 04:23:54 PM PDT 24 | Jun 26 04:24:41 PM PDT 24 | 7314760000 ps | ||
| T20 | /workspace/coverage/default/3.prim_present_test.3532240669 | Jun 26 04:18:49 PM PDT 24 | Jun 26 04:19:35 PM PDT 24 | 6215500000 ps | ||
| T21 | /workspace/coverage/default/21.prim_present_test.2419221077 | Jun 26 04:22:59 PM PDT 24 | Jun 26 04:23:30 PM PDT 24 | 4254440000 ps | ||
| T22 | /workspace/coverage/default/9.prim_present_test.1278954366 | Jun 26 04:18:06 PM PDT 24 | Jun 26 04:19:09 PM PDT 24 | 8925520000 ps | ||
| T23 | /workspace/coverage/default/31.prim_present_test.2977427670 | Jun 26 04:23:20 PM PDT 24 | Jun 26 04:24:18 PM PDT 24 | 9745780000 ps | ||
| T24 | /workspace/coverage/default/32.prim_present_test.1910849165 | Jun 26 04:24:05 PM PDT 24 | Jun 26 04:25:15 PM PDT 24 | 12524000000 ps | ||
| T25 | /workspace/coverage/default/0.prim_present_test.210304781 | Jun 26 04:17:56 PM PDT 24 | Jun 26 04:18:20 PM PDT 24 | 3990320000 ps | ||
| T26 | /workspace/coverage/default/45.prim_present_test.687804886 | Jun 26 04:23:54 PM PDT 24 | Jun 26 04:24:16 PM PDT 24 | 3879340000 ps | ||
| T27 | /workspace/coverage/default/22.prim_present_test.2126628890 | Jun 26 04:23:00 PM PDT 24 | Jun 26 04:24:15 PM PDT 24 | 12161300000 ps | ||
| T28 | /workspace/coverage/default/15.prim_present_test.1645189209 | Jun 26 04:20:56 PM PDT 24 | Jun 26 04:21:51 PM PDT 24 | 7720240000 ps | ||
| T29 | /workspace/coverage/default/47.prim_present_test.2894876709 | Jun 26 04:19:38 PM PDT 24 | Jun 26 04:20:20 PM PDT 24 | 5369820000 ps | ||
| T30 | /workspace/coverage/default/40.prim_present_test.841300757 | Jun 26 04:19:24 PM PDT 24 | Jun 26 04:21:02 PM PDT 24 | 13631320000 ps | ||
| T31 | /workspace/coverage/default/18.prim_present_test.41168542 | Jun 26 04:22:47 PM PDT 24 | Jun 26 04:24:22 PM PDT 24 | 15225960000 ps | ||
| T32 | /workspace/coverage/default/17.prim_present_test.1292620962 | Jun 26 04:23:14 PM PDT 24 | Jun 26 04:23:44 PM PDT 24 | 4950080000 ps | ||
| T33 | /workspace/coverage/default/23.prim_present_test.3659566231 | Jun 26 04:23:00 PM PDT 24 | Jun 26 04:24:29 PM PDT 24 | 15069100000 ps | ||
| T34 | /workspace/coverage/default/5.prim_present_test.1799159306 | Jun 26 04:17:57 PM PDT 24 | Jun 26 04:18:34 PM PDT 24 | 6217360000 ps | ||
| T35 | /workspace/coverage/default/42.prim_present_test.1070465902 | Jun 26 04:18:45 PM PDT 24 | Jun 26 04:19:18 PM PDT 24 | 4544600000 ps | ||
| T36 | /workspace/coverage/default/12.prim_present_test.2511449079 | Jun 26 04:23:57 PM PDT 24 | Jun 26 04:24:53 PM PDT 24 | 9562880000 ps | ||
| T37 | /workspace/coverage/default/38.prim_present_test.1940287160 | Jun 26 04:24:34 PM PDT 24 | Jun 26 04:26:00 PM PDT 24 | 13256220000 ps | ||
| T38 | /workspace/coverage/default/29.prim_present_test.418731881 | Jun 26 04:23:55 PM PDT 24 | Jun 26 04:24:46 PM PDT 24 | 8308620000 ps | ||
| T39 | /workspace/coverage/default/39.prim_present_test.2195815041 | Jun 26 04:23:02 PM PDT 24 | Jun 26 04:23:27 PM PDT 24 | 4109360000 ps | ||
| T40 | /workspace/coverage/default/1.prim_present_test.766647820 | Jun 26 04:17:56 PM PDT 24 | Jun 26 04:19:01 PM PDT 24 | 10713600000 ps | ||
| T41 | /workspace/coverage/default/11.prim_present_test.575120260 | Jun 26 04:23:57 PM PDT 24 | Jun 26 04:24:28 PM PDT 24 | 5004640000 ps | ||
| T42 | /workspace/coverage/default/46.prim_present_test.4054637188 | Jun 26 04:23:31 PM PDT 24 | Jun 26 04:24:49 PM PDT 24 | 12872440000 ps | ||
| T43 | /workspace/coverage/default/33.prim_present_test.2507662312 | Jun 26 04:23:20 PM PDT 24 | Jun 26 04:23:41 PM PDT 24 | 3171920000 ps | ||
| T44 | /workspace/coverage/default/20.prim_present_test.2930870561 | Jun 26 04:23:01 PM PDT 24 | Jun 26 04:24:00 PM PDT 24 | 8616760000 ps | ||
| T45 | /workspace/coverage/default/37.prim_present_test.4205323230 | Jun 26 04:20:26 PM PDT 24 | Jun 26 04:21:47 PM PDT 24 | 12828420000 ps | ||
| T46 | /workspace/coverage/default/48.prim_present_test.1246761482 | Jun 26 04:19:39 PM PDT 24 | Jun 26 04:21:28 PM PDT 24 | 15398940000 ps | ||
| T47 | /workspace/coverage/default/10.prim_present_test.1489782729 | Jun 26 04:19:55 PM PDT 24 | Jun 26 04:20:41 PM PDT 24 | 5735620000 ps | ||
| T48 | /workspace/coverage/default/41.prim_present_test.1682471773 | Jun 26 04:19:19 PM PDT 24 | Jun 26 04:21:06 PM PDT 24 | 15458460000 ps | ||
| T49 | /workspace/coverage/default/26.prim_present_test.476109617 | Jun 26 04:20:25 PM PDT 24 | Jun 26 04:21:45 PM PDT 24 | 12414260000 ps | ||
| T50 | /workspace/coverage/default/30.prim_present_test.2139893352 | Jun 26 04:19:21 PM PDT 24 | Jun 26 04:20:36 PM PDT 24 | 9815220000 ps |
| Test location | /workspace/coverage/default/14.prim_present_test.1092860084 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12223300000 ps |
| CPU time | 41.95 seconds |
| Started | Jun 26 04:20:42 PM PDT 24 |
| Finished | Jun 26 04:22:00 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-82f31a77-d06a-49b3-97ba-f0286d27748e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092860084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1092860084 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.210304781 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3990320000 ps |
| CPU time | 12.82 seconds |
| Started | Jun 26 04:17:56 PM PDT 24 |
| Finished | Jun 26 04:18:20 PM PDT 24 |
| Peak memory | 144364 kb |
| Host | smart-2aed4e7b-144a-4690-aae8-96cd9cfbfc7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210304781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.210304781 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.766647820 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10713600000 ps |
| CPU time | 35.32 seconds |
| Started | Jun 26 04:17:56 PM PDT 24 |
| Finished | Jun 26 04:19:01 PM PDT 24 |
| Peak memory | 143608 kb |
| Host | smart-5b81a0c5-b20e-4264-8dd1-fcaad35a9034 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766647820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.766647820 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1489782729 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5735620000 ps |
| CPU time | 23.49 seconds |
| Started | Jun 26 04:19:55 PM PDT 24 |
| Finished | Jun 26 04:20:41 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-55dfb159-b82d-46cc-8043-8a149b6e5fba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489782729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1489782729 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.575120260 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5004640000 ps |
| CPU time | 16.12 seconds |
| Started | Jun 26 04:23:57 PM PDT 24 |
| Finished | Jun 26 04:24:28 PM PDT 24 |
| Peak memory | 143820 kb |
| Host | smart-e3bc7255-5b38-45e9-b35a-35f0fd4992f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575120260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.575120260 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2511449079 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9562880000 ps |
| CPU time | 29.92 seconds |
| Started | Jun 26 04:23:57 PM PDT 24 |
| Finished | Jun 26 04:24:53 PM PDT 24 |
| Peak memory | 143816 kb |
| Host | smart-54017f5d-e6fe-418e-891e-8f7c7d196320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511449079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2511449079 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.302553638 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7825640000 ps |
| CPU time | 23.92 seconds |
| Started | Jun 26 04:22:57 PM PDT 24 |
| Finished | Jun 26 04:23:41 PM PDT 24 |
| Peak memory | 143740 kb |
| Host | smart-4760f7b6-8b16-4289-a531-95fb9354f746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302553638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.302553638 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1645189209 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7720240000 ps |
| CPU time | 29.1 seconds |
| Started | Jun 26 04:20:56 PM PDT 24 |
| Finished | Jun 26 04:21:51 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-7ef76186-2333-4272-8808-9a5538d485d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645189209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1645189209 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3565416276 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4720060000 ps |
| CPU time | 13.42 seconds |
| Started | Jun 26 04:22:56 PM PDT 24 |
| Finished | Jun 26 04:23:21 PM PDT 24 |
| Peak memory | 144484 kb |
| Host | smart-7433d626-cb4f-4c42-8785-cafc38a194c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3565416276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3565416276 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1292620962 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4950080000 ps |
| CPU time | 15.45 seconds |
| Started | Jun 26 04:23:14 PM PDT 24 |
| Finished | Jun 26 04:23:44 PM PDT 24 |
| Peak memory | 143992 kb |
| Host | smart-31aa5db4-2a3b-4cca-a947-25804ea1fed7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292620962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1292620962 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.41168542 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15225960000 ps |
| CPU time | 50.59 seconds |
| Started | Jun 26 04:22:47 PM PDT 24 |
| Finished | Jun 26 04:24:22 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-68a3080f-6a49-49b3-bc9f-7241fcfb7346 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41168542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.41168542 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3898393576 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13681540000 ps |
| CPU time | 47.08 seconds |
| Started | Jun 26 04:23:01 PM PDT 24 |
| Finished | Jun 26 04:24:30 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-fb67d908-dcfb-432b-b22f-68d9c4cb2f98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898393576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3898393576 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1768462105 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12957380000 ps |
| CPU time | 41.37 seconds |
| Started | Jun 26 04:18:58 PM PDT 24 |
| Finished | Jun 26 04:20:15 PM PDT 24 |
| Peak memory | 143452 kb |
| Host | smart-b76a641a-b295-4af9-8b3c-00a01cc3ecc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768462105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1768462105 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2930870561 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8616760000 ps |
| CPU time | 30.74 seconds |
| Started | Jun 26 04:23:01 PM PDT 24 |
| Finished | Jun 26 04:24:00 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-879b36e2-0f81-4db7-8396-2a018cd8e953 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930870561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2930870561 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2419221077 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4254440000 ps |
| CPU time | 16.13 seconds |
| Started | Jun 26 04:22:59 PM PDT 24 |
| Finished | Jun 26 04:23:30 PM PDT 24 |
| Peak memory | 144336 kb |
| Host | smart-63f8b46f-39fd-45e4-b905-25334cabbf7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419221077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2419221077 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2126628890 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12161300000 ps |
| CPU time | 40.46 seconds |
| Started | Jun 26 04:23:00 PM PDT 24 |
| Finished | Jun 26 04:24:15 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-72d59d28-b1e4-4cf7-bb95-2fdb79c1bd15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126628890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2126628890 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3659566231 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 15069100000 ps |
| CPU time | 48.74 seconds |
| Started | Jun 26 04:23:00 PM PDT 24 |
| Finished | Jun 26 04:24:29 PM PDT 24 |
| Peak memory | 144544 kb |
| Host | smart-a78bf221-b47a-4d22-9a24-ee61c7a42197 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659566231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3659566231 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3459454878 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7739460000 ps |
| CPU time | 30.46 seconds |
| Started | Jun 26 04:19:23 PM PDT 24 |
| Finished | Jun 26 04:20:21 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-46fea2d1-c73d-4f1a-8bd7-3a87c9048776 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3459454878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3459454878 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4101207748 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12925140000 ps |
| CPU time | 49.33 seconds |
| Started | Jun 26 04:21:55 PM PDT 24 |
| Finished | Jun 26 04:23:29 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-0067efea-e6e1-44d0-8225-b425e6f0f1dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101207748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4101207748 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.476109617 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12414260000 ps |
| CPU time | 42.45 seconds |
| Started | Jun 26 04:20:25 PM PDT 24 |
| Finished | Jun 26 04:21:45 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-5f44ea30-c747-4621-907f-adcd2e5156bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=476109617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.476109617 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1022628385 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7519360000 ps |
| CPU time | 26.68 seconds |
| Started | Jun 26 04:22:01 PM PDT 24 |
| Finished | Jun 26 04:22:51 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-d67e0432-1cc9-431a-a88f-f75eb56df72d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022628385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1022628385 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1159744666 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10683840000 ps |
| CPU time | 33.51 seconds |
| Started | Jun 26 04:23:55 PM PDT 24 |
| Finished | Jun 26 04:24:58 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-f9e2da1f-bcda-4195-a4a8-568445d52ebd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159744666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1159744666 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.418731881 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8308620000 ps |
| CPU time | 26.99 seconds |
| Started | Jun 26 04:23:55 PM PDT 24 |
| Finished | Jun 26 04:24:46 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-11ad4726-0153-4ec2-a270-1464f8cfc1c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418731881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.418731881 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3532240669 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6215500000 ps |
| CPU time | 24.08 seconds |
| Started | Jun 26 04:18:49 PM PDT 24 |
| Finished | Jun 26 04:19:35 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-4d277a2d-26cc-41cd-99f8-c901a9cd7427 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532240669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3532240669 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2139893352 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9815220000 ps |
| CPU time | 39.34 seconds |
| Started | Jun 26 04:19:21 PM PDT 24 |
| Finished | Jun 26 04:20:36 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-2f4c4f3e-2bb8-4c51-aa54-4384a3498747 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139893352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2139893352 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2977427670 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9745780000 ps |
| CPU time | 31.48 seconds |
| Started | Jun 26 04:23:20 PM PDT 24 |
| Finished | Jun 26 04:24:18 PM PDT 24 |
| Peak memory | 143352 kb |
| Host | smart-fb84bfaf-5a47-4da9-a5ec-a24849d618ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977427670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2977427670 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1910849165 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12524000000 ps |
| CPU time | 37.26 seconds |
| Started | Jun 26 04:24:05 PM PDT 24 |
| Finished | Jun 26 04:25:15 PM PDT 24 |
| Peak memory | 143988 kb |
| Host | smart-ce7a02f6-7217-4082-b4ff-649f15036e7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910849165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1910849165 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2507662312 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3171920000 ps |
| CPU time | 11.24 seconds |
| Started | Jun 26 04:23:20 PM PDT 24 |
| Finished | Jun 26 04:23:41 PM PDT 24 |
| Peak memory | 143068 kb |
| Host | smart-350e5921-303e-488d-866e-7579e5acf335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507662312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2507662312 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.780794737 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14672920000 ps |
| CPU time | 49.21 seconds |
| Started | Jun 26 04:21:01 PM PDT 24 |
| Finished | Jun 26 04:22:34 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-69690f79-a6c4-49b9-901b-05e1d922885d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780794737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.780794737 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1150188021 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13992780000 ps |
| CPU time | 43.02 seconds |
| Started | Jun 26 04:23:20 PM PDT 24 |
| Finished | Jun 26 04:24:39 PM PDT 24 |
| Peak memory | 143356 kb |
| Host | smart-88b32e7e-bcf0-407c-95ff-d0e2821a57db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150188021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1150188021 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.7586144 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11672120000 ps |
| CPU time | 38.72 seconds |
| Started | Jun 26 04:23:34 PM PDT 24 |
| Finished | Jun 26 04:24:47 PM PDT 24 |
| Peak memory | 143952 kb |
| Host | smart-d35ac4ed-ff75-4200-9369-c5377a42d3b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7586144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.7586144 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.4205323230 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12828420000 ps |
| CPU time | 43.51 seconds |
| Started | Jun 26 04:20:26 PM PDT 24 |
| Finished | Jun 26 04:21:47 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-2fc4aa27-0386-410d-99e6-909f51042597 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205323230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.4205323230 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1940287160 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13256220000 ps |
| CPU time | 45.12 seconds |
| Started | Jun 26 04:24:34 PM PDT 24 |
| Finished | Jun 26 04:26:00 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-f6987de7-1315-4c28-8dbd-1f784a4944f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940287160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1940287160 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2195815041 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4109360000 ps |
| CPU time | 12.94 seconds |
| Started | Jun 26 04:23:02 PM PDT 24 |
| Finished | Jun 26 04:23:27 PM PDT 24 |
| Peak memory | 144340 kb |
| Host | smart-d88c5fbb-fbc0-4582-9d33-f8aa3ef5b6e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195815041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2195815041 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3918148920 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14525980000 ps |
| CPU time | 52.84 seconds |
| Started | Jun 26 04:17:47 PM PDT 24 |
| Finished | Jun 26 04:19:28 PM PDT 24 |
| Peak memory | 143992 kb |
| Host | smart-b6315163-987d-438a-90df-242671ad53b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918148920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3918148920 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.841300757 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13631320000 ps |
| CPU time | 51.52 seconds |
| Started | Jun 26 04:19:24 PM PDT 24 |
| Finished | Jun 26 04:21:02 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-f8fbeee9-8ddc-4cac-821f-9b3894d7c28a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=841300757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.841300757 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1682471773 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 15458460000 ps |
| CPU time | 56.39 seconds |
| Started | Jun 26 04:19:19 PM PDT 24 |
| Finished | Jun 26 04:21:06 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-0f0fe48e-74e6-46d6-be50-ac2fa462c82e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682471773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1682471773 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1070465902 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4544600000 ps |
| CPU time | 17.1 seconds |
| Started | Jun 26 04:18:45 PM PDT 24 |
| Finished | Jun 26 04:19:18 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-04fb0d66-2172-4c69-8ddb-7f06086d2635 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070465902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1070465902 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2545731084 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7314760000 ps |
| CPU time | 24.44 seconds |
| Started | Jun 26 04:23:54 PM PDT 24 |
| Finished | Jun 26 04:24:41 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-4c985a83-0e58-4047-981e-2842aa746060 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545731084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2545731084 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2682060928 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4031240000 ps |
| CPU time | 14.29 seconds |
| Started | Jun 26 04:18:47 PM PDT 24 |
| Finished | Jun 26 04:19:15 PM PDT 24 |
| Peak memory | 144732 kb |
| Host | smart-dd17c7c9-53b4-48fc-b2ee-8cf11c5def16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682060928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2682060928 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.687804886 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3879340000 ps |
| CPU time | 11.61 seconds |
| Started | Jun 26 04:23:54 PM PDT 24 |
| Finished | Jun 26 04:24:16 PM PDT 24 |
| Peak memory | 144364 kb |
| Host | smart-151c2f8f-8604-435e-9da6-eb87b609353b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687804886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.687804886 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4054637188 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12872440000 ps |
| CPU time | 41.59 seconds |
| Started | Jun 26 04:23:31 PM PDT 24 |
| Finished | Jun 26 04:24:49 PM PDT 24 |
| Peak memory | 143532 kb |
| Host | smart-4adaf63c-ffc1-41f1-81de-eeac7af02ffe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054637188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4054637188 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2894876709 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5369820000 ps |
| CPU time | 21.86 seconds |
| Started | Jun 26 04:19:38 PM PDT 24 |
| Finished | Jun 26 04:20:20 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-663a9e69-5318-40ef-bb21-430c04dd325c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894876709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2894876709 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1246761482 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15398940000 ps |
| CPU time | 57.44 seconds |
| Started | Jun 26 04:19:39 PM PDT 24 |
| Finished | Jun 26 04:21:28 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-fc7ee72e-adfb-43ce-b343-66e0dd0cf045 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246761482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1246761482 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.451777501 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12055900000 ps |
| CPU time | 45.06 seconds |
| Started | Jun 26 04:19:59 PM PDT 24 |
| Finished | Jun 26 04:21:24 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-62de2846-8ec5-444b-a1d1-6fcd57e60b53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451777501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.451777501 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1799159306 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6217360000 ps |
| CPU time | 19.98 seconds |
| Started | Jun 26 04:17:57 PM PDT 24 |
| Finished | Jun 26 04:18:34 PM PDT 24 |
| Peak memory | 144568 kb |
| Host | smart-9bbe7024-bc37-45a1-be6c-e56cb5eaf9a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799159306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1799159306 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.7126452 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13137800000 ps |
| CPU time | 42.06 seconds |
| Started | Jun 26 04:18:58 PM PDT 24 |
| Finished | Jun 26 04:20:16 PM PDT 24 |
| Peak memory | 143316 kb |
| Host | smart-910c099e-8861-4a1a-a54f-6215e820fac4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7126452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.7126452 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.4286414529 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10722280000 ps |
| CPU time | 37.94 seconds |
| Started | Jun 26 04:17:58 PM PDT 24 |
| Finished | Jun 26 04:19:10 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-ca380d3b-247e-4597-aa99-38f8c4e68f71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286414529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.4286414529 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1951911316 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9389280000 ps |
| CPU time | 37.59 seconds |
| Started | Jun 26 04:19:55 PM PDT 24 |
| Finished | Jun 26 04:21:07 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-4a7ffb7f-05b2-4fc9-98a2-5a90d4e810b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951911316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1951911316 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1278954366 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8925520000 ps |
| CPU time | 33.35 seconds |
| Started | Jun 26 04:18:06 PM PDT 24 |
| Finished | Jun 26 04:19:09 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-ce3649f4-a87a-43d8-9b4c-7b88145ce4f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278954366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1278954366 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |