| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.356856948 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.310146737 |
| /workspace/coverage/default/1.prim_present_test.4095447173 |
| /workspace/coverage/default/11.prim_present_test.3362002097 |
| /workspace/coverage/default/12.prim_present_test.2506913643 |
| /workspace/coverage/default/13.prim_present_test.1003481457 |
| /workspace/coverage/default/14.prim_present_test.3643596221 |
| /workspace/coverage/default/15.prim_present_test.2596126780 |
| /workspace/coverage/default/16.prim_present_test.3080545740 |
| /workspace/coverage/default/17.prim_present_test.1675585147 |
| /workspace/coverage/default/18.prim_present_test.2972617173 |
| /workspace/coverage/default/19.prim_present_test.1880938337 |
| /workspace/coverage/default/2.prim_present_test.1277490236 |
| /workspace/coverage/default/20.prim_present_test.1550804338 |
| /workspace/coverage/default/21.prim_present_test.1903140869 |
| /workspace/coverage/default/22.prim_present_test.3705869402 |
| /workspace/coverage/default/23.prim_present_test.1542648407 |
| /workspace/coverage/default/24.prim_present_test.2627499086 |
| /workspace/coverage/default/25.prim_present_test.2346017575 |
| /workspace/coverage/default/26.prim_present_test.61626155 |
| /workspace/coverage/default/27.prim_present_test.3857949888 |
| /workspace/coverage/default/28.prim_present_test.3794900497 |
| /workspace/coverage/default/29.prim_present_test.2358095780 |
| /workspace/coverage/default/3.prim_present_test.981788806 |
| /workspace/coverage/default/30.prim_present_test.330858029 |
| /workspace/coverage/default/31.prim_present_test.4163252038 |
| /workspace/coverage/default/32.prim_present_test.3758465372 |
| /workspace/coverage/default/33.prim_present_test.3767856276 |
| /workspace/coverage/default/34.prim_present_test.1163075906 |
| /workspace/coverage/default/35.prim_present_test.1466552950 |
| /workspace/coverage/default/36.prim_present_test.3661086095 |
| /workspace/coverage/default/37.prim_present_test.647724155 |
| /workspace/coverage/default/38.prim_present_test.441833608 |
| /workspace/coverage/default/39.prim_present_test.418094479 |
| /workspace/coverage/default/4.prim_present_test.529353129 |
| /workspace/coverage/default/40.prim_present_test.2197653165 |
| /workspace/coverage/default/41.prim_present_test.1309252105 |
| /workspace/coverage/default/42.prim_present_test.3250120107 |
| /workspace/coverage/default/43.prim_present_test.4159782232 |
| /workspace/coverage/default/44.prim_present_test.340865401 |
| /workspace/coverage/default/45.prim_present_test.3614215059 |
| /workspace/coverage/default/46.prim_present_test.3512847545 |
| /workspace/coverage/default/47.prim_present_test.2684753237 |
| /workspace/coverage/default/48.prim_present_test.3710612586 |
| /workspace/coverage/default/49.prim_present_test.5853594 |
| /workspace/coverage/default/5.prim_present_test.2904611486 |
| /workspace/coverage/default/6.prim_present_test.1879589063 |
| /workspace/coverage/default/7.prim_present_test.715864574 |
| /workspace/coverage/default/8.prim_present_test.2431409181 |
| /workspace/coverage/default/9.prim_present_test.1963991406 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/8.prim_present_test.2431409181 | Jun 27 06:09:56 PM PDT 24 | Jun 27 06:12:02 PM PDT 24 | 14313320000 ps | ||
| T2 | /workspace/coverage/default/32.prim_present_test.3758465372 | Jun 27 06:10:06 PM PDT 24 | Jun 27 06:10:33 PM PDT 24 | 3564380000 ps | ||
| T3 | /workspace/coverage/default/28.prim_present_test.3794900497 | Jun 27 06:09:58 PM PDT 24 | Jun 27 06:10:25 PM PDT 24 | 4196780000 ps | ||
| T4 | /workspace/coverage/default/45.prim_present_test.3614215059 | Jun 27 06:10:01 PM PDT 24 | Jun 27 06:10:38 PM PDT 24 | 3881820000 ps | ||
| T5 | /workspace/coverage/default/26.prim_present_test.61626155 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:10:34 PM PDT 24 | 3785100000 ps | ||
| T6 | /workspace/coverage/default/36.prim_present_test.3661086095 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:10:34 PM PDT 24 | 4845920000 ps | ||
| T7 | /workspace/coverage/default/13.prim_present_test.1003481457 | Jun 27 06:09:59 PM PDT 24 | Jun 27 06:10:30 PM PDT 24 | 4785780000 ps | ||
| T8 | /workspace/coverage/default/41.prim_present_test.1309252105 | Jun 27 06:10:04 PM PDT 24 | Jun 27 06:11:20 PM PDT 24 | 9954720000 ps | ||
| T9 | /workspace/coverage/default/10.prim_present_test.356856948 | Jun 27 06:09:56 PM PDT 24 | Jun 27 06:12:09 PM PDT 24 | 15497520000 ps | ||
| T10 | /workspace/coverage/default/22.prim_present_test.3705869402 | Jun 27 06:10:01 PM PDT 24 | Jun 27 06:11:57 PM PDT 24 | 14454680000 ps | ||
| T11 | /workspace/coverage/default/49.prim_present_test.5853594 | Jun 27 06:09:55 PM PDT 24 | Jun 27 06:10:37 PM PDT 24 | 6689180000 ps | ||
| T12 | /workspace/coverage/default/29.prim_present_test.2358095780 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:10:36 PM PDT 24 | 4187480000 ps | ||
| T13 | /workspace/coverage/default/40.prim_present_test.2197653165 | Jun 27 06:10:04 PM PDT 24 | Jun 27 06:10:51 PM PDT 24 | 6160940000 ps | ||
| T14 | /workspace/coverage/default/25.prim_present_test.2346017575 | Jun 27 06:09:57 PM PDT 24 | Jun 27 06:10:27 PM PDT 24 | 3519120000 ps | ||
| T15 | /workspace/coverage/default/11.prim_present_test.3362002097 | Jun 27 06:09:55 PM PDT 24 | Jun 27 06:11:28 PM PDT 24 | 15072820000 ps | ||
| T16 | /workspace/coverage/default/37.prim_present_test.647724155 | Jun 27 06:10:02 PM PDT 24 | Jun 27 06:11:33 PM PDT 24 | 14245120000 ps | ||
| T17 | /workspace/coverage/default/38.prim_present_test.441833608 | Jun 27 06:10:06 PM PDT 24 | Jun 27 06:10:56 PM PDT 24 | 6890060000 ps | ||
| T18 | /workspace/coverage/default/21.prim_present_test.1903140869 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:11:51 PM PDT 24 | 13906600000 ps | ||
| T19 | /workspace/coverage/default/42.prim_present_test.3250120107 | Jun 27 06:10:04 PM PDT 24 | Jun 27 06:11:19 PM PDT 24 | 9934880000 ps | ||
| T20 | /workspace/coverage/default/1.prim_present_test.4095447173 | Jun 27 06:09:56 PM PDT 24 | Jun 27 06:11:36 PM PDT 24 | 15393980000 ps | ||
| T21 | /workspace/coverage/default/46.prim_present_test.3512847545 | Jun 27 06:10:05 PM PDT 24 | Jun 27 06:11:18 PM PDT 24 | 10332300000 ps | ||
| T22 | /workspace/coverage/default/3.prim_present_test.981788806 | Jun 27 06:09:53 PM PDT 24 | Jun 27 06:10:26 PM PDT 24 | 3909100000 ps | ||
| T23 | /workspace/coverage/default/30.prim_present_test.330858029 | Jun 27 06:09:58 PM PDT 24 | Jun 27 06:11:17 PM PDT 24 | 12621960000 ps | ||
| T24 | /workspace/coverage/default/31.prim_present_test.4163252038 | Jun 27 06:10:06 PM PDT 24 | Jun 27 06:11:17 PM PDT 24 | 10540620000 ps | ||
| T25 | /workspace/coverage/default/33.prim_present_test.3767856276 | Jun 27 06:10:06 PM PDT 24 | Jun 27 06:10:32 PM PDT 24 | 3374040000 ps | ||
| T26 | /workspace/coverage/default/4.prim_present_test.529353129 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:11:00 PM PDT 24 | 9523820000 ps | ||
| T27 | /workspace/coverage/default/18.prim_present_test.2972617173 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:11:07 PM PDT 24 | 7875860000 ps | ||
| T28 | /workspace/coverage/default/27.prim_present_test.3857949888 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:12:00 PM PDT 24 | 15019500000 ps | ||
| T29 | /workspace/coverage/default/35.prim_present_test.1466552950 | Jun 27 06:09:58 PM PDT 24 | Jun 27 06:10:55 PM PDT 24 | 8206320000 ps | ||
| T30 | /workspace/coverage/default/44.prim_present_test.340865401 | Jun 27 06:10:04 PM PDT 24 | Jun 27 06:11:50 PM PDT 24 | 14439180000 ps | ||
| T31 | /workspace/coverage/default/24.prim_present_test.2627499086 | Jun 27 06:09:57 PM PDT 24 | Jun 27 06:11:26 PM PDT 24 | 11466280000 ps | ||
| T32 | /workspace/coverage/default/12.prim_present_test.2506913643 | Jun 27 06:09:56 PM PDT 24 | Jun 27 06:11:45 PM PDT 24 | 15243940000 ps | ||
| T33 | /workspace/coverage/default/6.prim_present_test.1879589063 | Jun 27 06:10:01 PM PDT 24 | Jun 27 06:11:39 PM PDT 24 | 10990120000 ps | ||
| T34 | /workspace/coverage/default/20.prim_present_test.1550804338 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:10:40 PM PDT 24 | 4787640000 ps | ||
| T35 | /workspace/coverage/default/34.prim_present_test.1163075906 | Jun 27 06:10:05 PM PDT 24 | Jun 27 06:11:20 PM PDT 24 | 11223240000 ps | ||
| T36 | /workspace/coverage/default/0.prim_present_test.310146737 | Jun 27 06:10:01 PM PDT 24 | Jun 27 06:11:38 PM PDT 24 | 11923840000 ps | ||
| T37 | /workspace/coverage/default/47.prim_present_test.2684753237 | Jun 27 06:10:06 PM PDT 24 | Jun 27 06:10:37 PM PDT 24 | 4045500000 ps | ||
| T38 | /workspace/coverage/default/14.prim_present_test.3643596221 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:11:49 PM PDT 24 | 13356660000 ps | ||
| T39 | /workspace/coverage/default/17.prim_present_test.1675585147 | Jun 27 06:09:57 PM PDT 24 | Jun 27 06:10:56 PM PDT 24 | 9032780000 ps | ||
| T40 | /workspace/coverage/default/16.prim_present_test.3080545740 | Jun 27 06:09:55 PM PDT 24 | Jun 27 06:10:26 PM PDT 24 | 4969920000 ps | ||
| T41 | /workspace/coverage/default/15.prim_present_test.2596126780 | Jun 27 06:09:55 PM PDT 24 | Jun 27 06:10:55 PM PDT 24 | 8106500000 ps | ||
| T42 | /workspace/coverage/default/5.prim_present_test.2904611486 | Jun 27 06:09:56 PM PDT 24 | Jun 27 06:10:25 PM PDT 24 | 3690860000 ps | ||
| T43 | /workspace/coverage/default/2.prim_present_test.1277490236 | Jun 27 06:09:56 PM PDT 24 | Jun 27 06:11:32 PM PDT 24 | 14229620000 ps | ||
| T44 | /workspace/coverage/default/48.prim_present_test.3710612586 | Jun 27 06:10:05 PM PDT 24 | Jun 27 06:10:58 PM PDT 24 | 7080400000 ps | ||
| T45 | /workspace/coverage/default/9.prim_present_test.1963991406 | Jun 27 06:10:01 PM PDT 24 | Jun 27 06:11:40 PM PDT 24 | 11080640000 ps | ||
| T46 | /workspace/coverage/default/39.prim_present_test.418094479 | Jun 27 06:10:01 PM PDT 24 | Jun 27 06:10:46 PM PDT 24 | 6811940000 ps | ||
| T47 | /workspace/coverage/default/43.prim_present_test.4159782232 | Jun 27 06:10:04 PM PDT 24 | Jun 27 06:11:41 PM PDT 24 | 13179340000 ps | ||
| T48 | /workspace/coverage/default/19.prim_present_test.1880938337 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:11:30 PM PDT 24 | 11765120000 ps | ||
| T49 | /workspace/coverage/default/23.prim_present_test.1542648407 | Jun 27 06:10:00 PM PDT 24 | Jun 27 06:11:02 PM PDT 24 | 7801460000 ps | ||
| T50 | /workspace/coverage/default/7.prim_present_test.715864574 | Jun 27 06:09:56 PM PDT 24 | Jun 27 06:11:16 PM PDT 24 | 10933080000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.356856948 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 15497520000 ps |
| CPU time | 64.95 seconds |
| Started | Jun 27 06:09:56 PM PDT 24 |
| Finished | Jun 27 06:12:09 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-6e1a5d26-ec30-4ac2-850d-6e5f4e05bb05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356856948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.356856948 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.310146737 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11923840000 ps |
| CPU time | 47.14 seconds |
| Started | Jun 27 06:10:01 PM PDT 24 |
| Finished | Jun 27 06:11:38 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-1df7d2f5-c621-45c0-9a3b-3436953029cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310146737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.310146737 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4095447173 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 15393980000 ps |
| CPU time | 50.95 seconds |
| Started | Jun 27 06:09:56 PM PDT 24 |
| Finished | Jun 27 06:11:36 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-b94c1d9d-d71c-4d66-95e8-edd7b0f732e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095447173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4095447173 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3362002097 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15072820000 ps |
| CPU time | 47.16 seconds |
| Started | Jun 27 06:09:55 PM PDT 24 |
| Finished | Jun 27 06:11:28 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-af3a46fd-f732-43e7-bf9a-9291416da129 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362002097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3362002097 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2506913643 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 15243940000 ps |
| CPU time | 55.68 seconds |
| Started | Jun 27 06:09:56 PM PDT 24 |
| Finished | Jun 27 06:11:45 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a75e581b-1b67-4311-945d-7db2e312afc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2506913643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2506913643 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1003481457 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4785780000 ps |
| CPU time | 14.97 seconds |
| Started | Jun 27 06:09:59 PM PDT 24 |
| Finished | Jun 27 06:10:30 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-88c1e795-e530-4ce1-8d75-b0e2b6e61686 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003481457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1003481457 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3643596221 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13356660000 ps |
| CPU time | 53.01 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:11:49 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-98cdca04-8d40-4d49-9c53-30ab99336a9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3643596221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3643596221 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2596126780 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8106500000 ps |
| CPU time | 30.19 seconds |
| Started | Jun 27 06:09:55 PM PDT 24 |
| Finished | Jun 27 06:10:55 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-41118a73-37e8-4ac4-b7a7-046c5a9a0b95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596126780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2596126780 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3080545740 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4969920000 ps |
| CPU time | 14.7 seconds |
| Started | Jun 27 06:09:55 PM PDT 24 |
| Finished | Jun 27 06:10:26 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-c0420b52-6bcf-40aa-b69e-5e6e4104bc26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3080545740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3080545740 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1675585147 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9032780000 ps |
| CPU time | 29.89 seconds |
| Started | Jun 27 06:09:57 PM PDT 24 |
| Finished | Jun 27 06:10:56 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-2cefa471-0950-4d4f-afd4-a111bab76fe2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675585147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1675585147 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2972617173 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7875860000 ps |
| CPU time | 32.62 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:11:07 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-dc1ec031-5bdf-4467-9ab0-0b8a40cf649f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972617173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2972617173 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1880938337 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11765120000 ps |
| CPU time | 45.73 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:11:30 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-bf9aab23-0673-447d-bcc8-81c8dd1efa64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880938337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1880938337 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1277490236 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14229620000 ps |
| CPU time | 49.81 seconds |
| Started | Jun 27 06:09:56 PM PDT 24 |
| Finished | Jun 27 06:11:32 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-12c122d4-69cc-45ca-a2c5-75ada23a9fed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277490236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1277490236 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1550804338 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4787640000 ps |
| CPU time | 18.97 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:10:40 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-e9089365-9c96-443a-953f-919b5367f056 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550804338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1550804338 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1903140869 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13906600000 ps |
| CPU time | 55.94 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:11:51 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-2a0ba718-c546-4f10-a3f1-86c785e9561e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1903140869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1903140869 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3705869402 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 14454680000 ps |
| CPU time | 57.16 seconds |
| Started | Jun 27 06:10:01 PM PDT 24 |
| Finished | Jun 27 06:11:57 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-089dd5f5-9c38-4e97-9cda-b6f33e6fefbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705869402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3705869402 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1542648407 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7801460000 ps |
| CPU time | 30.85 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:11:02 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-0dcb5296-6c10-42d1-8abe-fdf5d071da4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1542648407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1542648407 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2627499086 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11466280000 ps |
| CPU time | 44.76 seconds |
| Started | Jun 27 06:09:57 PM PDT 24 |
| Finished | Jun 27 06:11:26 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-482efd5d-6486-49e7-9ce7-b0655de4174e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627499086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2627499086 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2346017575 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3519120000 ps |
| CPU time | 13.72 seconds |
| Started | Jun 27 06:09:57 PM PDT 24 |
| Finished | Jun 27 06:10:27 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-ce83defe-8829-4797-b7f3-660a958ddf4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346017575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2346017575 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.61626155 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3785100000 ps |
| CPU time | 15.91 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:10:34 PM PDT 24 |
| Peak memory | 144624 kb |
| Host | smart-e8eb4e26-f17d-4830-95b1-f5ad5f496eea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61626155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.61626155 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3857949888 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 15019500000 ps |
| CPU time | 59.32 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:12:00 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-dbf2f6bf-5624-4c8f-aa5b-248273797064 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857949888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3857949888 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3794900497 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4196780000 ps |
| CPU time | 12.7 seconds |
| Started | Jun 27 06:09:58 PM PDT 24 |
| Finished | Jun 27 06:10:25 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-96ebfc0e-b673-41fe-afd9-5d277726a39e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794900497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3794900497 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2358095780 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4187480000 ps |
| CPU time | 17.27 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:10:36 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-e4b70ac6-47cd-48fe-b369-73849558424c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2358095780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2358095780 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.981788806 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3909100000 ps |
| CPU time | 14.79 seconds |
| Started | Jun 27 06:09:53 PM PDT 24 |
| Finished | Jun 27 06:10:26 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-0874e83e-aa18-4ee3-862c-c163108849eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981788806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.981788806 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.330858029 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12621960000 ps |
| CPU time | 40.34 seconds |
| Started | Jun 27 06:09:58 PM PDT 24 |
| Finished | Jun 27 06:11:17 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-f99167b2-1dfc-43e3-913b-461a0f447299 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330858029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.330858029 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.4163252038 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10540620000 ps |
| CPU time | 37.51 seconds |
| Started | Jun 27 06:10:06 PM PDT 24 |
| Finished | Jun 27 06:11:17 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-1501f75c-1fd0-4042-b4b2-6721418f2c53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163252038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4163252038 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3758465372 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3564380000 ps |
| CPU time | 13.9 seconds |
| Started | Jun 27 06:10:06 PM PDT 24 |
| Finished | Jun 27 06:10:33 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-541b39c5-6efc-4132-b9d9-012cca3a6659 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3758465372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3758465372 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3767856276 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3374040000 ps |
| CPU time | 13.23 seconds |
| Started | Jun 27 06:10:06 PM PDT 24 |
| Finished | Jun 27 06:10:32 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-b717ca75-e880-421f-9637-6ea92d5d462d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767856276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3767856276 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1163075906 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11223240000 ps |
| CPU time | 39.4 seconds |
| Started | Jun 27 06:10:05 PM PDT 24 |
| Finished | Jun 27 06:11:20 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-f23e54b9-c098-407e-8c05-f032600e1839 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163075906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1163075906 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1466552950 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8206320000 ps |
| CPU time | 29.2 seconds |
| Started | Jun 27 06:09:58 PM PDT 24 |
| Finished | Jun 27 06:10:55 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-4c2092c1-d166-4f2b-9bef-28e0104065f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466552950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1466552950 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3661086095 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4845920000 ps |
| CPU time | 16.5 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:10:34 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-cbff3ba9-4edd-4119-bda8-9539cc4e461c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661086095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3661086095 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.647724155 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 14245120000 ps |
| CPU time | 47.4 seconds |
| Started | Jun 27 06:10:02 PM PDT 24 |
| Finished | Jun 27 06:11:33 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-1d004016-e199-41a5-be98-d31de13b044e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647724155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.647724155 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.441833608 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6890060000 ps |
| CPU time | 26.12 seconds |
| Started | Jun 27 06:10:06 PM PDT 24 |
| Finished | Jun 27 06:10:56 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-09cbea85-82db-4a19-ba0e-6eeec39a977c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441833608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.441833608 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.418094479 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6811940000 ps |
| CPU time | 22.26 seconds |
| Started | Jun 27 06:10:01 PM PDT 24 |
| Finished | Jun 27 06:10:46 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-0958916d-620d-4c95-b846-7450564f78d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418094479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.418094479 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.529353129 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9523820000 ps |
| CPU time | 30.32 seconds |
| Started | Jun 27 06:10:00 PM PDT 24 |
| Finished | Jun 27 06:11:00 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-8c1a6547-a5de-4dc2-bf2a-f0a1080fc164 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=529353129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.529353129 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2197653165 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6160940000 ps |
| CPU time | 23.72 seconds |
| Started | Jun 27 06:10:04 PM PDT 24 |
| Finished | Jun 27 06:10:51 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-cdfcf78c-5712-4c60-b444-d00228ead339 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197653165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2197653165 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1309252105 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9954720000 ps |
| CPU time | 38.98 seconds |
| Started | Jun 27 06:10:04 PM PDT 24 |
| Finished | Jun 27 06:11:20 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-94da38fd-da76-4afb-88e9-714c72beb8e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1309252105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1309252105 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3250120107 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9934880000 ps |
| CPU time | 38.24 seconds |
| Started | Jun 27 06:10:04 PM PDT 24 |
| Finished | Jun 27 06:11:19 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-473e4229-af6f-4333-8451-10055db16282 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250120107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3250120107 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4159782232 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13179340000 ps |
| CPU time | 49.55 seconds |
| Started | Jun 27 06:10:04 PM PDT 24 |
| Finished | Jun 27 06:11:41 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-12e2519d-cd5f-4136-aa30-75fa887aca64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4159782232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4159782232 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.340865401 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14439180000 ps |
| CPU time | 54.26 seconds |
| Started | Jun 27 06:10:04 PM PDT 24 |
| Finished | Jun 27 06:11:50 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-9eb80320-e4dd-46c1-bf76-b93db6b82b82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340865401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.340865401 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3614215059 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3881820000 ps |
| CPU time | 17.33 seconds |
| Started | Jun 27 06:10:01 PM PDT 24 |
| Finished | Jun 27 06:10:38 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-2fa5b5c0-155d-4b26-ba26-f578dbb7699b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614215059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3614215059 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3512847545 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10332300000 ps |
| CPU time | 38.52 seconds |
| Started | Jun 27 06:10:05 PM PDT 24 |
| Finished | Jun 27 06:11:18 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-8e520778-b907-452b-ac14-aacff079b1a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3512847545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3512847545 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2684753237 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4045500000 ps |
| CPU time | 16.04 seconds |
| Started | Jun 27 06:10:06 PM PDT 24 |
| Finished | Jun 27 06:10:37 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-f80807a0-6cd9-41a5-8fee-196530fba983 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2684753237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2684753237 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3710612586 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7080400000 ps |
| CPU time | 26.99 seconds |
| Started | Jun 27 06:10:05 PM PDT 24 |
| Finished | Jun 27 06:10:58 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-ad257b40-7d86-4641-9695-096940b836d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710612586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3710612586 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.5853594 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6689180000 ps |
| CPU time | 20.76 seconds |
| Started | Jun 27 06:09:55 PM PDT 24 |
| Finished | Jun 27 06:10:37 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-b17dee05-f997-454f-9cae-50f26bb9eef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5853594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.5853594 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2904611486 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3690860000 ps |
| CPU time | 13.23 seconds |
| Started | Jun 27 06:09:56 PM PDT 24 |
| Finished | Jun 27 06:10:25 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-efc819b3-ae5f-4aba-a00f-75c7d403af1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904611486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2904611486 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1879589063 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10990120000 ps |
| CPU time | 47.75 seconds |
| Started | Jun 27 06:10:01 PM PDT 24 |
| Finished | Jun 27 06:11:39 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-9143b624-a26d-4516-9481-9541ed9d9f5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879589063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1879589063 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.715864574 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10933080000 ps |
| CPU time | 40.02 seconds |
| Started | Jun 27 06:09:56 PM PDT 24 |
| Finished | Jun 27 06:11:16 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-902530d7-8081-4498-b9e5-0d6afc12f51a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715864574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.715864574 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2431409181 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14313320000 ps |
| CPU time | 60.64 seconds |
| Started | Jun 27 06:09:56 PM PDT 24 |
| Finished | Jun 27 06:12:02 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-ec76672d-97a9-45b7-9767-0a40c28ded9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431409181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2431409181 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1963991406 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11080640000 ps |
| CPU time | 48.32 seconds |
| Started | Jun 27 06:10:01 PM PDT 24 |
| Finished | Jun 27 06:11:40 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-58333be0-6de5-4c93-b522-fbf8cd94e81a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963991406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1963991406 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |