| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/18.prim_present_test.2583524452 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2823145420 |
| /workspace/coverage/default/1.prim_present_test.1017492073 |
| /workspace/coverage/default/10.prim_present_test.1954418139 |
| /workspace/coverage/default/11.prim_present_test.3615165491 |
| /workspace/coverage/default/12.prim_present_test.2343194885 |
| /workspace/coverage/default/13.prim_present_test.3787704298 |
| /workspace/coverage/default/14.prim_present_test.2028919831 |
| /workspace/coverage/default/15.prim_present_test.1952555206 |
| /workspace/coverage/default/16.prim_present_test.3023268244 |
| /workspace/coverage/default/17.prim_present_test.841395157 |
| /workspace/coverage/default/19.prim_present_test.3910680634 |
| /workspace/coverage/default/2.prim_present_test.3276078063 |
| /workspace/coverage/default/20.prim_present_test.210106849 |
| /workspace/coverage/default/21.prim_present_test.1549320043 |
| /workspace/coverage/default/22.prim_present_test.1440451974 |
| /workspace/coverage/default/23.prim_present_test.713092106 |
| /workspace/coverage/default/24.prim_present_test.3280408903 |
| /workspace/coverage/default/25.prim_present_test.3297722596 |
| /workspace/coverage/default/26.prim_present_test.3116031510 |
| /workspace/coverage/default/27.prim_present_test.2814090286 |
| /workspace/coverage/default/28.prim_present_test.443588839 |
| /workspace/coverage/default/29.prim_present_test.3549554360 |
| /workspace/coverage/default/3.prim_present_test.349885538 |
| /workspace/coverage/default/30.prim_present_test.1802844514 |
| /workspace/coverage/default/31.prim_present_test.3008121594 |
| /workspace/coverage/default/32.prim_present_test.3031173866 |
| /workspace/coverage/default/33.prim_present_test.4258115187 |
| /workspace/coverage/default/34.prim_present_test.4206785368 |
| /workspace/coverage/default/35.prim_present_test.3192900319 |
| /workspace/coverage/default/36.prim_present_test.3894303231 |
| /workspace/coverage/default/37.prim_present_test.4037668358 |
| /workspace/coverage/default/38.prim_present_test.2412505221 |
| /workspace/coverage/default/39.prim_present_test.3083387023 |
| /workspace/coverage/default/4.prim_present_test.2779842503 |
| /workspace/coverage/default/40.prim_present_test.4062035988 |
| /workspace/coverage/default/41.prim_present_test.1903341340 |
| /workspace/coverage/default/42.prim_present_test.2817516317 |
| /workspace/coverage/default/43.prim_present_test.1080680919 |
| /workspace/coverage/default/44.prim_present_test.1426784883 |
| /workspace/coverage/default/45.prim_present_test.2997469198 |
| /workspace/coverage/default/46.prim_present_test.2461662502 |
| /workspace/coverage/default/47.prim_present_test.3013872140 |
| /workspace/coverage/default/48.prim_present_test.1153913893 |
| /workspace/coverage/default/49.prim_present_test.756888628 |
| /workspace/coverage/default/5.prim_present_test.3014560870 |
| /workspace/coverage/default/6.prim_present_test.2455478518 |
| /workspace/coverage/default/7.prim_present_test.3279210534 |
| /workspace/coverage/default/8.prim_present_test.4126231999 |
| /workspace/coverage/default/9.prim_present_test.1997388740 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_present_test.2583524452 | Jun 28 04:17:33 PM PDT 24 | Jun 28 04:18:18 PM PDT 24 | 4539020000 ps | ||
| T2 | /workspace/coverage/default/38.prim_present_test.2412505221 | Jun 28 04:17:33 PM PDT 24 | Jun 28 04:18:30 PM PDT 24 | 5920380000 ps | ||
| T3 | /workspace/coverage/default/46.prim_present_test.2461662502 | Jun 28 04:17:32 PM PDT 24 | Jun 28 04:19:12 PM PDT 24 | 12735420000 ps | ||
| T4 | /workspace/coverage/default/30.prim_present_test.1802844514 | Jun 28 04:20:08 PM PDT 24 | Jun 28 04:21:48 PM PDT 24 | 15429320000 ps | ||
| T5 | /workspace/coverage/default/20.prim_present_test.210106849 | Jun 28 04:17:40 PM PDT 24 | Jun 28 04:18:01 PM PDT 24 | 3255620000 ps | ||
| T6 | /workspace/coverage/default/24.prim_present_test.3280408903 | Jun 28 04:17:31 PM PDT 24 | Jun 28 04:18:41 PM PDT 24 | 8560960000 ps | ||
| T7 | /workspace/coverage/default/35.prim_present_test.3192900319 | Jun 28 04:17:44 PM PDT 24 | Jun 28 04:18:13 PM PDT 24 | 3885540000 ps | ||
| T8 | /workspace/coverage/default/40.prim_present_test.4062035988 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:18:29 PM PDT 24 | 5723220000 ps | ||
| T9 | /workspace/coverage/default/33.prim_present_test.4258115187 | Jun 28 04:17:31 PM PDT 24 | Jun 28 04:18:42 PM PDT 24 | 8707280000 ps | ||
| T10 | /workspace/coverage/default/21.prim_present_test.1549320043 | Jun 28 04:18:47 PM PDT 24 | Jun 28 04:19:37 PM PDT 24 | 8038300000 ps | ||
| T11 | /workspace/coverage/default/6.prim_present_test.2455478518 | Jun 28 04:17:38 PM PDT 24 | Jun 28 04:18:26 PM PDT 24 | 7082260000 ps | ||
| T12 | /workspace/coverage/default/0.prim_present_test.2823145420 | Jun 28 04:17:33 PM PDT 24 | Jun 28 04:18:37 PM PDT 24 | 6756760000 ps | ||
| T13 | /workspace/coverage/default/23.prim_present_test.713092106 | Jun 28 04:17:31 PM PDT 24 | Jun 28 04:18:09 PM PDT 24 | 4637600000 ps | ||
| T14 | /workspace/coverage/default/9.prim_present_test.1997388740 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:18:18 PM PDT 24 | 4429900000 ps | ||
| T15 | /workspace/coverage/default/26.prim_present_test.3116031510 | Jun 28 04:17:25 PM PDT 24 | Jun 28 04:18:21 PM PDT 24 | 7533000000 ps | ||
| T16 | /workspace/coverage/default/12.prim_present_test.2343194885 | Jun 28 04:22:45 PM PDT 24 | Jun 28 04:23:43 PM PDT 24 | 11318720000 ps | ||
| T17 | /workspace/coverage/default/41.prim_present_test.1903341340 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:19:23 PM PDT 24 | 11932520000 ps | ||
| T18 | /workspace/coverage/default/32.prim_present_test.3031173866 | Jun 28 04:18:32 PM PDT 24 | Jun 28 04:19:37 PM PDT 24 | 10982060000 ps | ||
| T19 | /workspace/coverage/default/25.prim_present_test.3297722596 | Jun 28 04:17:33 PM PDT 24 | Jun 28 04:18:51 PM PDT 24 | 11246180000 ps | ||
| T20 | /workspace/coverage/default/44.prim_present_test.1426784883 | Jun 28 04:17:35 PM PDT 24 | Jun 28 04:19:04 PM PDT 24 | 12037920000 ps | ||
| T21 | /workspace/coverage/default/47.prim_present_test.3013872140 | Jun 28 04:17:41 PM PDT 24 | Jun 28 04:18:49 PM PDT 24 | 9730900000 ps | ||
| T22 | /workspace/coverage/default/15.prim_present_test.1952555206 | Jun 28 04:17:31 PM PDT 24 | Jun 28 04:19:31 PM PDT 24 | 15323920000 ps | ||
| T23 | /workspace/coverage/default/49.prim_present_test.756888628 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:18:54 PM PDT 24 | 10936180000 ps | ||
| T24 | /workspace/coverage/default/10.prim_present_test.1954418139 | Jun 28 04:17:44 PM PDT 24 | Jun 28 04:19:20 PM PDT 24 | 13958680000 ps | ||
| T25 | /workspace/coverage/default/13.prim_present_test.3787704298 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:19:32 PM PDT 24 | 12794320000 ps | ||
| T26 | /workspace/coverage/default/3.prim_present_test.349885538 | Jun 28 04:17:44 PM PDT 24 | Jun 28 04:19:06 PM PDT 24 | 11378860000 ps | ||
| T27 | /workspace/coverage/default/16.prim_present_test.3023268244 | Jun 28 04:17:44 PM PDT 24 | Jun 28 04:18:20 PM PDT 24 | 4883120000 ps | ||
| T28 | /workspace/coverage/default/17.prim_present_test.841395157 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:18:48 PM PDT 24 | 7785340000 ps | ||
| T29 | /workspace/coverage/default/37.prim_present_test.4037668358 | Jun 28 04:17:44 PM PDT 24 | Jun 28 04:19:08 PM PDT 24 | 11753960000 ps | ||
| T30 | /workspace/coverage/default/39.prim_present_test.3083387023 | Jun 28 04:17:35 PM PDT 24 | Jun 28 04:18:14 PM PDT 24 | 3940100000 ps | ||
| T31 | /workspace/coverage/default/4.prim_present_test.2779842503 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:19:08 PM PDT 24 | 12939400000 ps | ||
| T32 | /workspace/coverage/default/22.prim_present_test.1440451974 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:19:18 PM PDT 24 | 15011440000 ps | ||
| T33 | /workspace/coverage/default/2.prim_present_test.3276078063 | Jun 28 04:17:23 PM PDT 24 | Jun 28 04:18:17 PM PDT 24 | 7270740000 ps | ||
| T34 | /workspace/coverage/default/11.prim_present_test.3615165491 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:19:21 PM PDT 24 | 14568760000 ps | ||
| T35 | /workspace/coverage/default/5.prim_present_test.3014560870 | Jun 28 04:17:35 PM PDT 24 | Jun 28 04:19:14 PM PDT 24 | 10991360000 ps | ||
| T36 | /workspace/coverage/default/27.prim_present_test.2814090286 | Jun 28 04:17:35 PM PDT 24 | Jun 28 04:18:46 PM PDT 24 | 10065080000 ps | ||
| T37 | /workspace/coverage/default/45.prim_present_test.2997469198 | Jun 28 04:20:12 PM PDT 24 | Jun 28 04:20:39 PM PDT 24 | 3946300000 ps | ||
| T38 | /workspace/coverage/default/36.prim_present_test.3894303231 | Jun 28 04:17:23 PM PDT 24 | Jun 28 04:18:42 PM PDT 24 | 11093040000 ps | ||
| T39 | /workspace/coverage/default/7.prim_present_test.3279210534 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:19:18 PM PDT 24 | 11771320000 ps | ||
| T40 | /workspace/coverage/default/19.prim_present_test.3910680634 | Jun 28 04:20:04 PM PDT 24 | Jun 28 04:20:41 PM PDT 24 | 4991620000 ps | ||
| T41 | /workspace/coverage/default/31.prim_present_test.3008121594 | Jun 28 04:17:35 PM PDT 24 | Jun 28 04:18:19 PM PDT 24 | 6436840000 ps | ||
| T42 | /workspace/coverage/default/28.prim_present_test.443588839 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:18:47 PM PDT 24 | 10478620000 ps | ||
| T43 | /workspace/coverage/default/29.prim_present_test.3549554360 | Jun 28 04:17:33 PM PDT 24 | Jun 28 04:19:22 PM PDT 24 | 12121620000 ps | ||
| T44 | /workspace/coverage/default/42.prim_present_test.2817516317 | Jun 28 04:17:44 PM PDT 24 | Jun 28 04:19:00 PM PDT 24 | 10352760000 ps | ||
| T45 | /workspace/coverage/default/8.prim_present_test.4126231999 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:19:03 PM PDT 24 | 9606280000 ps | ||
| T46 | /workspace/coverage/default/14.prim_present_test.2028919831 | Jun 28 04:17:35 PM PDT 24 | Jun 28 04:18:13 PM PDT 24 | 3710700000 ps | ||
| T47 | /workspace/coverage/default/43.prim_present_test.1080680919 | Jun 28 04:17:33 PM PDT 24 | Jun 28 04:19:45 PM PDT 24 | 15452880000 ps | ||
| T48 | /workspace/coverage/default/48.prim_present_test.1153913893 | Jun 28 04:17:33 PM PDT 24 | Jun 28 04:18:59 PM PDT 24 | 9438880000 ps | ||
| T49 | /workspace/coverage/default/34.prim_present_test.4206785368 | Jun 28 04:17:34 PM PDT 24 | Jun 28 04:18:47 PM PDT 24 | 10735300000 ps | ||
| T50 | /workspace/coverage/default/1.prim_present_test.1017492073 | Jun 28 04:17:35 PM PDT 24 | Jun 28 04:18:00 PM PDT 24 | 3305220000 ps |
| Test location | /workspace/coverage/default/18.prim_present_test.2583524452 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4539020000 ps |
| CPU time | 20.97 seconds |
| Started | Jun 28 04:17:33 PM PDT 24 |
| Finished | Jun 28 04:18:18 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-f7ff175f-b9a7-4557-aad5-e40e1cc88ce7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583524452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2583524452 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2823145420 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6756760000 ps |
| CPU time | 30.84 seconds |
| Started | Jun 28 04:17:33 PM PDT 24 |
| Finished | Jun 28 04:18:37 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-8e20ca53-70e4-4c5c-87e7-44e59402f3c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823145420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2823145420 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1017492073 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3305220000 ps |
| CPU time | 12.73 seconds |
| Started | Jun 28 04:17:35 PM PDT 24 |
| Finished | Jun 28 04:18:00 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-767ee636-63bb-4310-8dc0-4513bfc54453 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017492073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1017492073 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1954418139 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 13958680000 ps |
| CPU time | 51.29 seconds |
| Started | Jun 28 04:17:44 PM PDT 24 |
| Finished | Jun 28 04:19:20 PM PDT 24 |
| Peak memory | 142612 kb |
| Host | smart-5206f7f1-3281-4f0e-9f60-991042295ba5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954418139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1954418139 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3615165491 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 14568760000 ps |
| CPU time | 55.34 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:19:21 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-17a97048-dffa-48c5-9f18-b6c5a067f5c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615165491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3615165491 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2343194885 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11318720000 ps |
| CPU time | 32.06 seconds |
| Started | Jun 28 04:22:45 PM PDT 24 |
| Finished | Jun 28 04:23:43 PM PDT 24 |
| Peak memory | 143992 kb |
| Host | smart-2985f309-5a27-4995-b3ae-2c33f73f3f9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343194885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2343194885 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3787704298 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12794320000 ps |
| CPU time | 58.89 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:19:32 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-98751839-10e1-4cf0-b5fe-174cca893410 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787704298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3787704298 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2028919831 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3710700000 ps |
| CPU time | 17.69 seconds |
| Started | Jun 28 04:17:35 PM PDT 24 |
| Finished | Jun 28 04:18:13 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-e7475eff-83ae-4a1c-81c2-64867bd752bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028919831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2028919831 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1952555206 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 15323920000 ps |
| CPU time | 62.34 seconds |
| Started | Jun 28 04:17:31 PM PDT 24 |
| Finished | Jun 28 04:19:31 PM PDT 24 |
| Peak memory | 144348 kb |
| Host | smart-81ae9178-431d-4dec-b16f-9341a7411bdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1952555206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1952555206 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3023268244 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4883120000 ps |
| CPU time | 18.69 seconds |
| Started | Jun 28 04:17:44 PM PDT 24 |
| Finished | Jun 28 04:18:20 PM PDT 24 |
| Peak memory | 142904 kb |
| Host | smart-793a037f-c78c-4125-8282-bb68966a4cec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023268244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3023268244 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.841395157 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7785340000 ps |
| CPU time | 35.93 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:18:48 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-59f0ef67-1678-4196-b754-a07686880202 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=841395157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.841395157 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3910680634 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4991620000 ps |
| CPU time | 19.14 seconds |
| Started | Jun 28 04:20:04 PM PDT 24 |
| Finished | Jun 28 04:20:41 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-777a6ef9-d9de-4321-856a-a268d58a855b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910680634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3910680634 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3276078063 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7270740000 ps |
| CPU time | 28.18 seconds |
| Started | Jun 28 04:17:23 PM PDT 24 |
| Finished | Jun 28 04:18:17 PM PDT 24 |
| Peak memory | 144176 kb |
| Host | smart-f5d3e3dc-a809-404e-b133-bb2cc4e4a9be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276078063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3276078063 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.210106849 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3255620000 ps |
| CPU time | 11.65 seconds |
| Started | Jun 28 04:17:40 PM PDT 24 |
| Finished | Jun 28 04:18:01 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-62fbb3b6-809a-4fa3-ba7e-36923b6e42c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210106849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.210106849 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1549320043 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8038300000 ps |
| CPU time | 26.76 seconds |
| Started | Jun 28 04:18:47 PM PDT 24 |
| Finished | Jun 28 04:19:37 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-36a24f7a-c72b-4e9f-b2cd-024302689812 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549320043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1549320043 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1440451974 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 15011440000 ps |
| CPU time | 54.22 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:19:18 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-933c59f6-8baa-4e5b-b37e-9da1b3beff25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440451974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1440451974 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.713092106 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4637600000 ps |
| CPU time | 19.49 seconds |
| Started | Jun 28 04:17:31 PM PDT 24 |
| Finished | Jun 28 04:18:09 PM PDT 24 |
| Peak memory | 143516 kb |
| Host | smart-3d83ae8e-cfba-4abb-9a31-db30586041eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713092106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.713092106 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3280408903 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8560960000 ps |
| CPU time | 35.79 seconds |
| Started | Jun 28 04:17:31 PM PDT 24 |
| Finished | Jun 28 04:18:41 PM PDT 24 |
| Peak memory | 143480 kb |
| Host | smart-147c2e24-5da2-4555-a0bd-39b3180dea56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280408903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3280408903 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3297722596 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11246180000 ps |
| CPU time | 40.91 seconds |
| Started | Jun 28 04:17:33 PM PDT 24 |
| Finished | Jun 28 04:18:51 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-d7f12432-94e3-48b6-bdd5-a4ea9921f0de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297722596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3297722596 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3116031510 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7533000000 ps |
| CPU time | 29.56 seconds |
| Started | Jun 28 04:17:25 PM PDT 24 |
| Finished | Jun 28 04:18:21 PM PDT 24 |
| Peak memory | 144564 kb |
| Host | smart-cd7472cc-6220-4eae-a1e5-a983a5a217ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116031510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3116031510 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2814090286 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10065080000 ps |
| CPU time | 36.85 seconds |
| Started | Jun 28 04:17:35 PM PDT 24 |
| Finished | Jun 28 04:18:46 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-b0ae97dd-77ff-440d-af46-09a3ad5cda94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814090286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2814090286 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.443588839 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10478620000 ps |
| CPU time | 38.42 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:18:47 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-cf663c2c-fc23-40c9-9a4d-c6ff7abf6d8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443588839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.443588839 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3549554360 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12121620000 ps |
| CPU time | 54.2 seconds |
| Started | Jun 28 04:17:33 PM PDT 24 |
| Finished | Jun 28 04:19:22 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-ce77d328-a704-4d4f-b46b-089e9e46abef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549554360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3549554360 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.349885538 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11378860000 ps |
| CPU time | 43.32 seconds |
| Started | Jun 28 04:17:44 PM PDT 24 |
| Finished | Jun 28 04:19:06 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-fc3165a1-4833-4b54-878a-11b00c838547 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=349885538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.349885538 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1802844514 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15429320000 ps |
| CPU time | 53 seconds |
| Started | Jun 28 04:20:08 PM PDT 24 |
| Finished | Jun 28 04:21:48 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-c8f46d62-ee73-48d0-a050-8470c70bfe8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802844514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1802844514 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3008121594 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6436840000 ps |
| CPU time | 22.54 seconds |
| Started | Jun 28 04:17:35 PM PDT 24 |
| Finished | Jun 28 04:18:19 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-f7d57ac9-0e3f-4e28-9e41-af62f4503595 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008121594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3008121594 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3031173866 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10982060000 ps |
| CPU time | 34.44 seconds |
| Started | Jun 28 04:18:32 PM PDT 24 |
| Finished | Jun 28 04:19:37 PM PDT 24 |
| Peak memory | 143056 kb |
| Host | smart-a35fa5ef-5d24-4728-b173-e11f327f6520 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031173866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3031173866 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.4258115187 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8707280000 ps |
| CPU time | 36.43 seconds |
| Started | Jun 28 04:17:31 PM PDT 24 |
| Finished | Jun 28 04:18:42 PM PDT 24 |
| Peak memory | 143944 kb |
| Host | smart-861eb261-25c8-4705-9cbf-9f2ae7b2a271 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258115187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.4258115187 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.4206785368 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10735300000 ps |
| CPU time | 38.75 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:18:47 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-bee0bc49-99ac-4094-a79a-0d939d64e8af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206785368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.4206785368 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3192900319 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3885540000 ps |
| CPU time | 15.2 seconds |
| Started | Jun 28 04:17:44 PM PDT 24 |
| Finished | Jun 28 04:18:13 PM PDT 24 |
| Peak memory | 143000 kb |
| Host | smart-3c987a80-c8e5-4048-9184-2ece84f4bdde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192900319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3192900319 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3894303231 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11093040000 ps |
| CPU time | 41.7 seconds |
| Started | Jun 28 04:17:23 PM PDT 24 |
| Finished | Jun 28 04:18:42 PM PDT 24 |
| Peak memory | 143616 kb |
| Host | smart-49059e41-69a2-442e-adfb-2ac3a60b9c4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894303231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3894303231 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.4037668358 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11753960000 ps |
| CPU time | 44.47 seconds |
| Started | Jun 28 04:17:44 PM PDT 24 |
| Finished | Jun 28 04:19:08 PM PDT 24 |
| Peak memory | 142776 kb |
| Host | smart-9f10e7eb-b453-4052-a32d-10315a1f5413 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037668358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.4037668358 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2412505221 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5920380000 ps |
| CPU time | 27.35 seconds |
| Started | Jun 28 04:17:33 PM PDT 24 |
| Finished | Jun 28 04:18:30 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-2326cac2-0830-40d5-8706-a68a50a6327b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412505221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2412505221 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3083387023 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3940100000 ps |
| CPU time | 18.38 seconds |
| Started | Jun 28 04:17:35 PM PDT 24 |
| Finished | Jun 28 04:18:14 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-f74405be-49b8-4d6f-8145-971bbdc27295 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083387023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3083387023 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2779842503 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12939400000 ps |
| CPU time | 48.1 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:19:08 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-b9cb50da-e2d6-407f-9d64-e1f48edd90c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779842503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2779842503 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4062035988 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5723220000 ps |
| CPU time | 26.23 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:18:29 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-5d909f09-4827-4ed9-ad21-a99af1605a47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062035988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4062035988 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1903341340 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11932520000 ps |
| CPU time | 53.18 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:19:23 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-2a2ff8d3-0979-49d0-94e8-e014b5bc4836 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1903341340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1903341340 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2817516317 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10352760000 ps |
| CPU time | 39.42 seconds |
| Started | Jun 28 04:17:44 PM PDT 24 |
| Finished | Jun 28 04:19:00 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-c0ee57e9-df7b-4b76-b239-5c7658300686 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817516317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2817516317 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1080680919 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15452880000 ps |
| CPU time | 66.46 seconds |
| Started | Jun 28 04:17:33 PM PDT 24 |
| Finished | Jun 28 04:19:45 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-57d7bd42-8ddc-4d0a-9e9c-12895f7bbb74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080680919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1080680919 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1426784883 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12037920000 ps |
| CPU time | 45.92 seconds |
| Started | Jun 28 04:17:35 PM PDT 24 |
| Finished | Jun 28 04:19:04 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-146b2bd2-8af0-402b-9c25-d31e216c1a4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426784883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1426784883 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2997469198 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3946300000 ps |
| CPU time | 14.68 seconds |
| Started | Jun 28 04:20:12 PM PDT 24 |
| Finished | Jun 28 04:20:39 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-d90ba007-2f21-4f8b-901b-3376c5b91090 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997469198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2997469198 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2461662502 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12735420000 ps |
| CPU time | 51.84 seconds |
| Started | Jun 28 04:17:32 PM PDT 24 |
| Finished | Jun 28 04:19:12 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-b459b766-a511-4c23-8bbb-85efbf94285e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461662502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2461662502 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3013872140 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9730900000 ps |
| CPU time | 36.06 seconds |
| Started | Jun 28 04:17:41 PM PDT 24 |
| Finished | Jun 28 04:18:49 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-8f5ad5a8-bbd5-4f11-9842-1ce8ccba963f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013872140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3013872140 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1153913893 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9438880000 ps |
| CPU time | 42.4 seconds |
| Started | Jun 28 04:17:33 PM PDT 24 |
| Finished | Jun 28 04:18:59 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-ce9e99d3-67bd-4feb-af6d-c8089f276b81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153913893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1153913893 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.756888628 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10936180000 ps |
| CPU time | 41.16 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:18:54 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-1b8de0b2-c704-4a20-8e69-3b2d322c6539 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756888628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.756888628 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3014560870 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10991360000 ps |
| CPU time | 48.85 seconds |
| Started | Jun 28 04:17:35 PM PDT 24 |
| Finished | Jun 28 04:19:14 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-81b34d74-6568-4481-8bc4-17c4cfb46dcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014560870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3014560870 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2455478518 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7082260000 ps |
| CPU time | 25.61 seconds |
| Started | Jun 28 04:17:38 PM PDT 24 |
| Finished | Jun 28 04:18:26 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-b7f28878-3e13-44d4-bf10-778ea4518338 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455478518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2455478518 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3279210534 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11771320000 ps |
| CPU time | 52.01 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:19:18 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-9c88eb84-4d4c-4322-a4a6-32853b5e5252 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279210534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3279210534 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4126231999 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9606280000 ps |
| CPU time | 43.1 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:19:03 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-38ffb1ae-e8e4-4785-8106-59a2651e275d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126231999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4126231999 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1997388740 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4429900000 ps |
| CPU time | 20.53 seconds |
| Started | Jun 28 04:17:34 PM PDT 24 |
| Finished | Jun 28 04:18:18 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-5b716d7e-57ad-4918-b3da-7580bfe73d39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997388740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1997388740 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |