| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.860405143 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1234878194 |
| /workspace/coverage/default/10.prim_present_test.1055268783 |
| /workspace/coverage/default/11.prim_present_test.4057263978 |
| /workspace/coverage/default/12.prim_present_test.2583096407 |
| /workspace/coverage/default/13.prim_present_test.482141106 |
| /workspace/coverage/default/14.prim_present_test.1339018548 |
| /workspace/coverage/default/15.prim_present_test.2668955740 |
| /workspace/coverage/default/16.prim_present_test.3302336047 |
| /workspace/coverage/default/17.prim_present_test.2844812829 |
| /workspace/coverage/default/18.prim_present_test.598946037 |
| /workspace/coverage/default/19.prim_present_test.1969481822 |
| /workspace/coverage/default/2.prim_present_test.3399624367 |
| /workspace/coverage/default/20.prim_present_test.1566500217 |
| /workspace/coverage/default/21.prim_present_test.2463910762 |
| /workspace/coverage/default/22.prim_present_test.4097407233 |
| /workspace/coverage/default/23.prim_present_test.3608255659 |
| /workspace/coverage/default/24.prim_present_test.4178744786 |
| /workspace/coverage/default/25.prim_present_test.3687887365 |
| /workspace/coverage/default/26.prim_present_test.2791963814 |
| /workspace/coverage/default/27.prim_present_test.3842178074 |
| /workspace/coverage/default/28.prim_present_test.2785542218 |
| /workspace/coverage/default/29.prim_present_test.3269852656 |
| /workspace/coverage/default/3.prim_present_test.3263505577 |
| /workspace/coverage/default/30.prim_present_test.2154338290 |
| /workspace/coverage/default/31.prim_present_test.1713648794 |
| /workspace/coverage/default/32.prim_present_test.2302782404 |
| /workspace/coverage/default/33.prim_present_test.41384793 |
| /workspace/coverage/default/34.prim_present_test.976870571 |
| /workspace/coverage/default/35.prim_present_test.2802587876 |
| /workspace/coverage/default/36.prim_present_test.2737165474 |
| /workspace/coverage/default/37.prim_present_test.572217249 |
| /workspace/coverage/default/38.prim_present_test.3246454243 |
| /workspace/coverage/default/39.prim_present_test.1326797949 |
| /workspace/coverage/default/4.prim_present_test.1527742825 |
| /workspace/coverage/default/40.prim_present_test.2816036731 |
| /workspace/coverage/default/41.prim_present_test.179708982 |
| /workspace/coverage/default/42.prim_present_test.2240578485 |
| /workspace/coverage/default/43.prim_present_test.23648183 |
| /workspace/coverage/default/44.prim_present_test.1608040317 |
| /workspace/coverage/default/45.prim_present_test.3966927826 |
| /workspace/coverage/default/46.prim_present_test.2348850928 |
| /workspace/coverage/default/47.prim_present_test.319945420 |
| /workspace/coverage/default/48.prim_present_test.1870734482 |
| /workspace/coverage/default/49.prim_present_test.740287532 |
| /workspace/coverage/default/5.prim_present_test.2575719850 |
| /workspace/coverage/default/6.prim_present_test.2490364357 |
| /workspace/coverage/default/7.prim_present_test.2381425760 |
| /workspace/coverage/default/8.prim_present_test.1092899561 |
| /workspace/coverage/default/9.prim_present_test.2922842288 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.prim_present_test.860405143 | Jun 29 06:17:25 PM PDT 24 | Jun 29 06:19:03 PM PDT 24 | 11978400000 ps | ||
| T2 | /workspace/coverage/default/18.prim_present_test.598946037 | Jun 29 06:17:30 PM PDT 24 | Jun 29 06:18:14 PM PDT 24 | 5271240000 ps | ||
| T3 | /workspace/coverage/default/26.prim_present_test.2791963814 | Jun 29 06:17:37 PM PDT 24 | Jun 29 06:18:20 PM PDT 24 | 4515460000 ps | ||
| T4 | /workspace/coverage/default/42.prim_present_test.2240578485 | Jun 29 06:17:41 PM PDT 24 | Jun 29 06:18:52 PM PDT 24 | 9561640000 ps | ||
| T5 | /workspace/coverage/default/38.prim_present_test.3246454243 | Jun 29 06:17:40 PM PDT 24 | Jun 29 06:18:38 PM PDT 24 | 7632820000 ps | ||
| T6 | /workspace/coverage/default/36.prim_present_test.2737165474 | Jun 29 06:17:40 PM PDT 24 | Jun 29 06:19:25 PM PDT 24 | 10391820000 ps | ||
| T7 | /workspace/coverage/default/5.prim_present_test.2575719850 | Jun 29 06:17:22 PM PDT 24 | Jun 29 06:18:51 PM PDT 24 | 14162660000 ps | ||
| T8 | /workspace/coverage/default/24.prim_present_test.4178744786 | Jun 29 06:17:32 PM PDT 24 | Jun 29 06:18:42 PM PDT 24 | 8127580000 ps | ||
| T9 | /workspace/coverage/default/10.prim_present_test.1055268783 | Jun 29 06:17:23 PM PDT 24 | Jun 29 06:18:07 PM PDT 24 | 6215500000 ps | ||
| T10 | /workspace/coverage/default/19.prim_present_test.1969481822 | Jun 29 06:17:31 PM PDT 24 | Jun 29 06:19:03 PM PDT 24 | 14820480000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.1326797949 | Jun 29 06:17:40 PM PDT 24 | Jun 29 06:19:01 PM PDT 24 | 9194600000 ps | ||
| T12 | /workspace/coverage/default/44.prim_present_test.1608040317 | Jun 29 06:17:40 PM PDT 24 | Jun 29 06:19:02 PM PDT 24 | 10234960000 ps | ||
| T13 | /workspace/coverage/default/0.prim_present_test.1234878194 | Jun 29 06:17:24 PM PDT 24 | Jun 29 06:19:03 PM PDT 24 | 14060980000 ps | ||
| T14 | /workspace/coverage/default/43.prim_present_test.23648183 | Jun 29 06:17:39 PM PDT 24 | Jun 29 06:18:59 PM PDT 24 | 10517060000 ps | ||
| T15 | /workspace/coverage/default/32.prim_present_test.2302782404 | Jun 29 06:17:40 PM PDT 24 | Jun 29 06:18:16 PM PDT 24 | 4841580000 ps | ||
| T16 | /workspace/coverage/default/47.prim_present_test.319945420 | Jun 29 06:17:40 PM PDT 24 | Jun 29 06:18:25 PM PDT 24 | 5097020000 ps | ||
| T17 | /workspace/coverage/default/45.prim_present_test.3966927826 | Jun 29 06:17:44 PM PDT 24 | Jun 29 06:18:23 PM PDT 24 | 5379740000 ps | ||
| T18 | /workspace/coverage/default/25.prim_present_test.3687887365 | Jun 29 06:17:31 PM PDT 24 | Jun 29 06:18:19 PM PDT 24 | 5775300000 ps | ||
| T19 | /workspace/coverage/default/35.prim_present_test.2802587876 | Jun 29 06:17:44 PM PDT 24 | Jun 29 06:19:23 PM PDT 24 | 11091180000 ps | ||
| T20 | /workspace/coverage/default/48.prim_present_test.1870734482 | Jun 29 06:17:45 PM PDT 24 | Jun 29 06:18:29 PM PDT 24 | 6110720000 ps | ||
| T21 | /workspace/coverage/default/9.prim_present_test.2922842288 | Jun 29 06:17:25 PM PDT 24 | Jun 29 06:19:03 PM PDT 24 | 13411220000 ps | ||
| T22 | /workspace/coverage/default/33.prim_present_test.41384793 | Jun 29 06:17:41 PM PDT 24 | Jun 29 06:18:36 PM PDT 24 | 6265100000 ps | ||
| T23 | /workspace/coverage/default/37.prim_present_test.572217249 | Jun 29 06:17:38 PM PDT 24 | Jun 29 06:19:27 PM PDT 24 | 14062840000 ps | ||
| T24 | /workspace/coverage/default/17.prim_present_test.2844812829 | Jun 29 06:17:33 PM PDT 24 | Jun 29 06:18:27 PM PDT 24 | 6376700000 ps | ||
| T25 | /workspace/coverage/default/23.prim_present_test.3608255659 | Jun 29 06:17:32 PM PDT 24 | Jun 29 06:18:02 PM PDT 24 | 3922120000 ps | ||
| T26 | /workspace/coverage/default/34.prim_present_test.976870571 | Jun 29 06:17:40 PM PDT 24 | Jun 29 06:18:25 PM PDT 24 | 6594940000 ps | ||
| T27 | /workspace/coverage/default/21.prim_present_test.2463910762 | Jun 29 06:17:31 PM PDT 24 | Jun 29 06:18:38 PM PDT 24 | 8568400000 ps | ||
| T28 | /workspace/coverage/default/41.prim_present_test.179708982 | Jun 29 06:17:45 PM PDT 24 | Jun 29 06:18:54 PM PDT 24 | 10457540000 ps | ||
| T29 | /workspace/coverage/default/15.prim_present_test.2668955740 | Jun 29 06:17:38 PM PDT 24 | Jun 29 06:18:26 PM PDT 24 | 4938920000 ps | ||
| T30 | /workspace/coverage/default/31.prim_present_test.1713648794 | Jun 29 06:17:32 PM PDT 24 | Jun 29 06:18:33 PM PDT 24 | 6671200000 ps | ||
| T31 | /workspace/coverage/default/22.prim_present_test.4097407233 | Jun 29 06:17:31 PM PDT 24 | Jun 29 06:18:50 PM PDT 24 | 10587120000 ps | ||
| T32 | /workspace/coverage/default/3.prim_present_test.3263505577 | Jun 29 06:17:25 PM PDT 24 | Jun 29 06:18:05 PM PDT 24 | 5617820000 ps | ||
| T33 | /workspace/coverage/default/27.prim_present_test.3842178074 | Jun 29 06:17:33 PM PDT 24 | Jun 29 06:18:48 PM PDT 24 | 8737040000 ps | ||
| T34 | /workspace/coverage/default/4.prim_present_test.1527742825 | Jun 29 06:17:22 PM PDT 24 | Jun 29 06:19:10 PM PDT 24 | 15193720000 ps | ||
| T35 | /workspace/coverage/default/30.prim_present_test.2154338290 | Jun 29 06:17:32 PM PDT 24 | Jun 29 06:18:36 PM PDT 24 | 7246560000 ps | ||
| T36 | /workspace/coverage/default/49.prim_present_test.740287532 | Jun 29 06:17:42 PM PDT 24 | Jun 29 06:19:44 PM PDT 24 | 14439800000 ps | ||
| T37 | /workspace/coverage/default/46.prim_present_test.2348850928 | Jun 29 06:17:42 PM PDT 24 | Jun 29 06:18:37 PM PDT 24 | 6327720000 ps | ||
| T38 | /workspace/coverage/default/40.prim_present_test.2816036731 | Jun 29 06:17:40 PM PDT 24 | Jun 29 06:18:32 PM PDT 24 | 6446760000 ps | ||
| T39 | /workspace/coverage/default/14.prim_present_test.1339018548 | Jun 29 06:17:37 PM PDT 24 | Jun 29 06:19:29 PM PDT 24 | 13083240000 ps | ||
| T40 | /workspace/coverage/default/8.prim_present_test.1092899561 | Jun 29 06:17:27 PM PDT 24 | Jun 29 06:18:24 PM PDT 24 | 6765440000 ps | ||
| T41 | /workspace/coverage/default/6.prim_present_test.2490364357 | Jun 29 06:17:21 PM PDT 24 | Jun 29 06:18:59 PM PDT 24 | 9922480000 ps | ||
| T42 | /workspace/coverage/default/11.prim_present_test.4057263978 | Jun 29 06:17:31 PM PDT 24 | Jun 29 06:19:21 PM PDT 24 | 15196200000 ps | ||
| T43 | /workspace/coverage/default/20.prim_present_test.1566500217 | Jun 29 06:17:32 PM PDT 24 | Jun 29 06:18:41 PM PDT 24 | 8966440000 ps | ||
| T44 | /workspace/coverage/default/7.prim_present_test.2381425760 | Jun 29 06:17:23 PM PDT 24 | Jun 29 06:18:33 PM PDT 24 | 8052560000 ps | ||
| T45 | /workspace/coverage/default/13.prim_present_test.482141106 | Jun 29 06:17:30 PM PDT 24 | Jun 29 06:18:39 PM PDT 24 | 8580180000 ps | ||
| T46 | /workspace/coverage/default/28.prim_present_test.2785542218 | Jun 29 06:17:35 PM PDT 24 | Jun 29 06:19:26 PM PDT 24 | 14237680000 ps | ||
| T47 | /workspace/coverage/default/16.prim_present_test.3302336047 | Jun 29 06:17:31 PM PDT 24 | Jun 29 06:18:09 PM PDT 24 | 4461520000 ps | ||
| T48 | /workspace/coverage/default/12.prim_present_test.2583096407 | Jun 29 06:17:32 PM PDT 24 | Jun 29 06:19:03 PM PDT 24 | 13615200000 ps | ||
| T49 | /workspace/coverage/default/29.prim_present_test.3269852656 | Jun 29 06:17:34 PM PDT 24 | Jun 29 06:18:04 PM PDT 24 | 3556320000 ps | ||
| T50 | /workspace/coverage/default/2.prim_present_test.3399624367 | Jun 29 06:17:27 PM PDT 24 | Jun 29 06:18:27 PM PDT 24 | 7158520000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.860405143 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11978400000 ps |
| CPU time | 49.32 seconds |
| Started | Jun 29 06:17:25 PM PDT 24 |
| Finished | Jun 29 06:19:03 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-040132eb-18df-4c0e-a998-5d94eaaed77b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860405143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.860405143 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1234878194 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14060980000 ps |
| CPU time | 50.31 seconds |
| Started | Jun 29 06:17:24 PM PDT 24 |
| Finished | Jun 29 06:19:03 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-47a347ca-93e2-4187-b909-69dc89a3fe3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234878194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1234878194 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1055268783 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6215500000 ps |
| CPU time | 23.23 seconds |
| Started | Jun 29 06:17:23 PM PDT 24 |
| Finished | Jun 29 06:18:07 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-1d2fd291-4c3a-42ae-9b46-e36bc31f9324 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1055268783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1055268783 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4057263978 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15196200000 ps |
| CPU time | 57.21 seconds |
| Started | Jun 29 06:17:31 PM PDT 24 |
| Finished | Jun 29 06:19:21 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-40be416b-c388-4fcc-b5c2-0022c2c65c58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057263978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4057263978 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2583096407 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13615200000 ps |
| CPU time | 47.84 seconds |
| Started | Jun 29 06:17:32 PM PDT 24 |
| Finished | Jun 29 06:19:03 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-1ab5e89f-375c-4db5-afa8-b95d29a7685c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583096407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2583096407 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.482141106 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8580180000 ps |
| CPU time | 34.63 seconds |
| Started | Jun 29 06:17:30 PM PDT 24 |
| Finished | Jun 29 06:18:39 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-2bdf38a3-10ac-45d9-bb36-980512b630ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482141106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.482141106 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1339018548 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13083240000 ps |
| CPU time | 55.51 seconds |
| Started | Jun 29 06:17:37 PM PDT 24 |
| Finished | Jun 29 06:19:29 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-2d598465-d055-4cf5-9466-7cf44640c86a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1339018548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1339018548 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2668955740 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4938920000 ps |
| CPU time | 22.99 seconds |
| Started | Jun 29 06:17:38 PM PDT 24 |
| Finished | Jun 29 06:18:26 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-23771f02-dc35-47e7-9195-d55f6884d9c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668955740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2668955740 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3302336047 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4461520000 ps |
| CPU time | 19.05 seconds |
| Started | Jun 29 06:17:31 PM PDT 24 |
| Finished | Jun 29 06:18:09 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-650ffc04-e04a-48bd-bc38-ccde1387ec21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302336047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3302336047 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2844812829 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6376700000 ps |
| CPU time | 27.8 seconds |
| Started | Jun 29 06:17:33 PM PDT 24 |
| Finished | Jun 29 06:18:27 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-fe53a147-6d10-4880-90a7-71295777aece |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844812829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2844812829 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.598946037 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5271240000 ps |
| CPU time | 22.67 seconds |
| Started | Jun 29 06:17:30 PM PDT 24 |
| Finished | Jun 29 06:18:14 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-91a583e1-525d-4844-af16-1f6a306e0675 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598946037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.598946037 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1969481822 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 14820480000 ps |
| CPU time | 49.94 seconds |
| Started | Jun 29 06:17:31 PM PDT 24 |
| Finished | Jun 29 06:19:03 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-78bd784e-2f90-4b5c-843c-fe71089b382b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969481822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1969481822 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3399624367 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7158520000 ps |
| CPU time | 30.77 seconds |
| Started | Jun 29 06:17:27 PM PDT 24 |
| Finished | Jun 29 06:18:27 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-ddfdfb73-566a-459b-bfb4-01bf8e21614d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399624367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3399624367 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1566500217 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8966440000 ps |
| CPU time | 35.38 seconds |
| Started | Jun 29 06:17:32 PM PDT 24 |
| Finished | Jun 29 06:18:41 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-f62459e3-8444-4d4a-99e9-d38442365afc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566500217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1566500217 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2463910762 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8568400000 ps |
| CPU time | 34.71 seconds |
| Started | Jun 29 06:17:31 PM PDT 24 |
| Finished | Jun 29 06:18:38 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-2c3995f4-8315-40b1-900d-993e1ad6f6d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463910762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2463910762 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.4097407233 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10587120000 ps |
| CPU time | 39.73 seconds |
| Started | Jun 29 06:17:31 PM PDT 24 |
| Finished | Jun 29 06:18:50 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-5aabb15a-0b26-4fce-b537-b8a771772247 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097407233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.4097407233 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3608255659 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3922120000 ps |
| CPU time | 14.6 seconds |
| Started | Jun 29 06:17:32 PM PDT 24 |
| Finished | Jun 29 06:18:02 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-3c7aa01e-ec92-43d1-a794-c3872153fd30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608255659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3608255659 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4178744786 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8127580000 ps |
| CPU time | 33.83 seconds |
| Started | Jun 29 06:17:32 PM PDT 24 |
| Finished | Jun 29 06:18:42 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-21d734d5-0588-4a66-842b-aa5f052cae8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178744786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4178744786 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3687887365 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5775300000 ps |
| CPU time | 24.09 seconds |
| Started | Jun 29 06:17:31 PM PDT 24 |
| Finished | Jun 29 06:18:19 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-61bf2b9c-419a-4601-9e3d-cfdaf1027854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687887365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3687887365 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2791963814 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4515460000 ps |
| CPU time | 20.98 seconds |
| Started | Jun 29 06:17:37 PM PDT 24 |
| Finished | Jun 29 06:18:20 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-9d3e00a7-a9a7-497d-9f1e-ce7c3a6172ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791963814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2791963814 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3842178074 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8737040000 ps |
| CPU time | 36.63 seconds |
| Started | Jun 29 06:17:33 PM PDT 24 |
| Finished | Jun 29 06:18:48 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-20c107a7-7198-48d4-b8c7-7cb2126b652e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842178074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3842178074 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2785542218 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14237680000 ps |
| CPU time | 57.57 seconds |
| Started | Jun 29 06:17:35 PM PDT 24 |
| Finished | Jun 29 06:19:26 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-effc87e4-bbb4-478e-807f-257664fc7f0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785542218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2785542218 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3269852656 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3556320000 ps |
| CPU time | 15.04 seconds |
| Started | Jun 29 06:17:34 PM PDT 24 |
| Finished | Jun 29 06:18:04 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-57f3c25b-7a5c-4baa-aeaf-4e9ffe31672b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269852656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3269852656 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3263505577 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5617820000 ps |
| CPU time | 20.12 seconds |
| Started | Jun 29 06:17:25 PM PDT 24 |
| Finished | Jun 29 06:18:05 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-94609526-4fe0-49b6-a63e-d28bb4e4ec2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263505577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3263505577 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2154338290 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7246560000 ps |
| CPU time | 32.51 seconds |
| Started | Jun 29 06:17:32 PM PDT 24 |
| Finished | Jun 29 06:18:36 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-0ae6b8b7-bb09-4855-8707-2750de6fae51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154338290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2154338290 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1713648794 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6671200000 ps |
| CPU time | 30.12 seconds |
| Started | Jun 29 06:17:32 PM PDT 24 |
| Finished | Jun 29 06:18:33 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-9d31fad2-81ea-4922-8dad-bc914e733a03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1713648794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1713648794 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2302782404 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4841580000 ps |
| CPU time | 18.08 seconds |
| Started | Jun 29 06:17:40 PM PDT 24 |
| Finished | Jun 29 06:18:16 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-39ca2098-69bc-4553-b01f-99ac50112d7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302782404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2302782404 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.41384793 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6265100000 ps |
| CPU time | 25.59 seconds |
| Started | Jun 29 06:17:41 PM PDT 24 |
| Finished | Jun 29 06:18:36 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-5420ce0a-c35f-430f-bb74-4a91a74fdf0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41384793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.41384793 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.976870571 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6594940000 ps |
| CPU time | 24.1 seconds |
| Started | Jun 29 06:17:40 PM PDT 24 |
| Finished | Jun 29 06:18:25 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-b554448e-11aa-4fb0-84c6-ba12e95e506a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976870571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.976870571 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2802587876 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11091180000 ps |
| CPU time | 49.27 seconds |
| Started | Jun 29 06:17:44 PM PDT 24 |
| Finished | Jun 29 06:19:23 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-70ec36dd-7975-4480-ab77-7f717d37bf32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802587876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2802587876 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2737165474 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 10391820000 ps |
| CPU time | 52 seconds |
| Started | Jun 29 06:17:40 PM PDT 24 |
| Finished | Jun 29 06:19:25 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-5fc22c71-2e17-4f25-baf5-f61f9925b270 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737165474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2737165474 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.572217249 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14062840000 ps |
| CPU time | 55.97 seconds |
| Started | Jun 29 06:17:38 PM PDT 24 |
| Finished | Jun 29 06:19:27 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-b5e27186-5c27-404e-bb13-b5e7470d700b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572217249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.572217249 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3246454243 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7632820000 ps |
| CPU time | 29.17 seconds |
| Started | Jun 29 06:17:40 PM PDT 24 |
| Finished | Jun 29 06:18:38 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-78edc941-fe24-4f0a-b20c-64129995585e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3246454243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3246454243 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1326797949 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9194600000 ps |
| CPU time | 42.68 seconds |
| Started | Jun 29 06:17:40 PM PDT 24 |
| Finished | Jun 29 06:19:01 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-93fca153-a120-499d-a7cf-63e82252df0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326797949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1326797949 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1527742825 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 15193720000 ps |
| CPU time | 53.74 seconds |
| Started | Jun 29 06:17:22 PM PDT 24 |
| Finished | Jun 29 06:19:10 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-44e48040-f0f6-4a20-9936-e5f469270a22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527742825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1527742825 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2816036731 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6446760000 ps |
| CPU time | 25.33 seconds |
| Started | Jun 29 06:17:40 PM PDT 24 |
| Finished | Jun 29 06:18:32 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-96f9d581-d7bc-4a47-b553-dbb181423172 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816036731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2816036731 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.179708982 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10457540000 ps |
| CPU time | 36.18 seconds |
| Started | Jun 29 06:17:45 PM PDT 24 |
| Finished | Jun 29 06:18:54 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-78356cbf-4fc0-4e22-be77-d462b3647bc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179708982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.179708982 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2240578485 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9561640000 ps |
| CPU time | 36.28 seconds |
| Started | Jun 29 06:17:41 PM PDT 24 |
| Finished | Jun 29 06:18:52 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-52f75551-791c-42e6-897f-e08295a060c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240578485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2240578485 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.23648183 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10517060000 ps |
| CPU time | 40.6 seconds |
| Started | Jun 29 06:17:39 PM PDT 24 |
| Finished | Jun 29 06:18:59 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-1f4b7009-4abc-49f5-aaa9-a20a8942a102 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23648183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.23648183 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1608040317 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10234960000 ps |
| CPU time | 40.89 seconds |
| Started | Jun 29 06:17:40 PM PDT 24 |
| Finished | Jun 29 06:19:02 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-6f27abe3-a4bf-4e7d-8761-77239bdb76ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608040317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1608040317 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3966927826 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5379740000 ps |
| CPU time | 19.4 seconds |
| Started | Jun 29 06:17:44 PM PDT 24 |
| Finished | Jun 29 06:18:23 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-7d1e2b03-81a1-475b-b19d-f67034a34d59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966927826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3966927826 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2348850928 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6327720000 ps |
| CPU time | 26.46 seconds |
| Started | Jun 29 06:17:42 PM PDT 24 |
| Finished | Jun 29 06:18:37 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-22d19b8c-c47e-44e4-afe6-fdb01f60d565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348850928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2348850928 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.319945420 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5097020000 ps |
| CPU time | 22.52 seconds |
| Started | Jun 29 06:17:40 PM PDT 24 |
| Finished | Jun 29 06:18:25 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-d8369e8d-4da1-46ed-b771-86c1f23da7c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319945420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.319945420 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1870734482 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6110720000 ps |
| CPU time | 22.58 seconds |
| Started | Jun 29 06:17:45 PM PDT 24 |
| Finished | Jun 29 06:18:29 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-508be9a3-e123-4b6d-b96a-242ea41d98a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870734482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1870734482 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.740287532 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14439800000 ps |
| CPU time | 60.19 seconds |
| Started | Jun 29 06:17:42 PM PDT 24 |
| Finished | Jun 29 06:19:44 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-bf79789a-3bc4-40e7-9009-50e4d7999cb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=740287532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.740287532 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2575719850 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14162660000 ps |
| CPU time | 46.88 seconds |
| Started | Jun 29 06:17:22 PM PDT 24 |
| Finished | Jun 29 06:18:51 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-77aca489-af8a-4c67-9c4d-531b75a534f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575719850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2575719850 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2490364357 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9922480000 ps |
| CPU time | 48.29 seconds |
| Started | Jun 29 06:17:21 PM PDT 24 |
| Finished | Jun 29 06:18:59 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-ecb5200d-fb72-44f6-a6f8-e5135206f67a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490364357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2490364357 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2381425760 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8052560000 ps |
| CPU time | 34.12 seconds |
| Started | Jun 29 06:17:23 PM PDT 24 |
| Finished | Jun 29 06:18:33 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-33901856-dde4-47e5-913c-10d47795746b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2381425760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2381425760 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1092899561 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6765440000 ps |
| CPU time | 28.72 seconds |
| Started | Jun 29 06:17:27 PM PDT 24 |
| Finished | Jun 29 06:18:24 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-d7d643c7-b701-4a40-8dd1-9387829edc12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092899561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1092899561 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2922842288 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13411220000 ps |
| CPU time | 50.42 seconds |
| Started | Jun 29 06:17:25 PM PDT 24 |
| Finished | Jun 29 06:19:03 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-5ed530fb-754a-440b-b154-6e8fd75552f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922842288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2922842288 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |