| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.2396229615 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3406894155 |
| /workspace/coverage/default/1.prim_present_test.2642764868 |
| /workspace/coverage/default/10.prim_present_test.51658762 |
| /workspace/coverage/default/12.prim_present_test.2755478038 |
| /workspace/coverage/default/13.prim_present_test.662617596 |
| /workspace/coverage/default/14.prim_present_test.280172397 |
| /workspace/coverage/default/15.prim_present_test.1298998184 |
| /workspace/coverage/default/16.prim_present_test.672973182 |
| /workspace/coverage/default/17.prim_present_test.1638307096 |
| /workspace/coverage/default/18.prim_present_test.4035736203 |
| /workspace/coverage/default/19.prim_present_test.3479502905 |
| /workspace/coverage/default/2.prim_present_test.4109808362 |
| /workspace/coverage/default/20.prim_present_test.535923303 |
| /workspace/coverage/default/21.prim_present_test.2295699217 |
| /workspace/coverage/default/22.prim_present_test.1642342165 |
| /workspace/coverage/default/23.prim_present_test.670462770 |
| /workspace/coverage/default/24.prim_present_test.423332250 |
| /workspace/coverage/default/25.prim_present_test.2002972673 |
| /workspace/coverage/default/26.prim_present_test.437153359 |
| /workspace/coverage/default/27.prim_present_test.312876360 |
| /workspace/coverage/default/28.prim_present_test.2651700628 |
| /workspace/coverage/default/29.prim_present_test.3629285054 |
| /workspace/coverage/default/3.prim_present_test.2987854417 |
| /workspace/coverage/default/30.prim_present_test.2287010478 |
| /workspace/coverage/default/31.prim_present_test.2966350784 |
| /workspace/coverage/default/32.prim_present_test.2848240061 |
| /workspace/coverage/default/33.prim_present_test.2209583126 |
| /workspace/coverage/default/34.prim_present_test.3900325939 |
| /workspace/coverage/default/35.prim_present_test.3315596499 |
| /workspace/coverage/default/36.prim_present_test.1415148400 |
| /workspace/coverage/default/37.prim_present_test.689806799 |
| /workspace/coverage/default/38.prim_present_test.2099903255 |
| /workspace/coverage/default/39.prim_present_test.2248440168 |
| /workspace/coverage/default/4.prim_present_test.466080763 |
| /workspace/coverage/default/40.prim_present_test.1877358456 |
| /workspace/coverage/default/41.prim_present_test.443056153 |
| /workspace/coverage/default/42.prim_present_test.259680786 |
| /workspace/coverage/default/43.prim_present_test.311304209 |
| /workspace/coverage/default/44.prim_present_test.3100488893 |
| /workspace/coverage/default/45.prim_present_test.2361308705 |
| /workspace/coverage/default/46.prim_present_test.2735416597 |
| /workspace/coverage/default/47.prim_present_test.1400445338 |
| /workspace/coverage/default/48.prim_present_test.1608255332 |
| /workspace/coverage/default/49.prim_present_test.4142117836 |
| /workspace/coverage/default/5.prim_present_test.2160408407 |
| /workspace/coverage/default/6.prim_present_test.761012782 |
| /workspace/coverage/default/7.prim_present_test.2330036849 |
| /workspace/coverage/default/8.prim_present_test.518067482 |
| /workspace/coverage/default/9.prim_present_test.3412601488 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/48.prim_present_test.1608255332 | Jun 30 04:25:14 PM PDT 24 | Jun 30 04:25:58 PM PDT 24 | 5725080000 ps | ||
| T2 | /workspace/coverage/default/16.prim_present_test.672973182 | Jun 30 04:25:23 PM PDT 24 | Jun 30 04:26:09 PM PDT 24 | 6660040000 ps | ||
| T3 | /workspace/coverage/default/18.prim_present_test.4035736203 | Jun 30 04:25:01 PM PDT 24 | Jun 30 04:26:09 PM PDT 24 | 12383880000 ps | ||
| T4 | /workspace/coverage/default/30.prim_present_test.2287010478 | Jun 30 04:25:02 PM PDT 24 | Jun 30 04:25:36 PM PDT 24 | 5710820000 ps | ||
| T5 | /workspace/coverage/default/11.prim_present_test.2396229615 | Jun 30 04:25:04 PM PDT 24 | Jun 30 04:25:30 PM PDT 24 | 3866940000 ps | ||
| T6 | /workspace/coverage/default/12.prim_present_test.2755478038 | Jun 30 04:24:59 PM PDT 24 | Jun 30 04:26:11 PM PDT 24 | 13006980000 ps | ||
| T7 | /workspace/coverage/default/8.prim_present_test.518067482 | Jun 30 04:25:06 PM PDT 24 | Jun 30 04:26:28 PM PDT 24 | 14596040000 ps | ||
| T8 | /workspace/coverage/default/15.prim_present_test.1298998184 | Jun 30 04:25:21 PM PDT 24 | Jun 30 04:27:11 PM PDT 24 | 14539000000 ps | ||
| T9 | /workspace/coverage/default/47.prim_present_test.1400445338 | Jun 30 04:25:14 PM PDT 24 | Jun 30 04:25:46 PM PDT 24 | 5080280000 ps | ||
| T10 | /workspace/coverage/default/14.prim_present_test.280172397 | Jun 30 04:24:55 PM PDT 24 | Jun 30 04:25:18 PM PDT 24 | 4196780000 ps | ||
| T11 | /workspace/coverage/default/42.prim_present_test.259680786 | Jun 30 04:25:34 PM PDT 24 | Jun 30 04:26:19 PM PDT 24 | 7820060000 ps | ||
| T12 | /workspace/coverage/default/26.prim_present_test.437153359 | Jun 30 04:25:10 PM PDT 24 | Jun 30 04:25:38 PM PDT 24 | 5430580000 ps | ||
| T13 | /workspace/coverage/default/37.prim_present_test.689806799 | Jun 30 04:25:08 PM PDT 24 | Jun 30 04:25:58 PM PDT 24 | 8399760000 ps | ||
| T14 | /workspace/coverage/default/31.prim_present_test.2966350784 | Jun 30 04:25:33 PM PDT 24 | Jun 30 04:26:39 PM PDT 24 | 12488660000 ps | ||
| T15 | /workspace/coverage/default/38.prim_present_test.2099903255 | Jun 30 04:25:00 PM PDT 24 | Jun 30 04:26:09 PM PDT 24 | 12012500000 ps | ||
| T16 | /workspace/coverage/default/22.prim_present_test.1642342165 | Jun 30 04:25:26 PM PDT 24 | Jun 30 04:26:38 PM PDT 24 | 13015040000 ps | ||
| T17 | /workspace/coverage/default/19.prim_present_test.3479502905 | Jun 30 04:25:07 PM PDT 24 | Jun 30 04:25:46 PM PDT 24 | 7015920000 ps | ||
| T18 | /workspace/coverage/default/29.prim_present_test.3629285054 | Jun 30 04:25:01 PM PDT 24 | Jun 30 04:25:55 PM PDT 24 | 10151880000 ps | ||
| T19 | /workspace/coverage/default/44.prim_present_test.3100488893 | Jun 30 04:25:21 PM PDT 24 | Jun 30 04:26:22 PM PDT 24 | 10823960000 ps | ||
| T20 | /workspace/coverage/default/13.prim_present_test.662617596 | Jun 30 04:25:06 PM PDT 24 | Jun 30 04:25:48 PM PDT 24 | 6793340000 ps | ||
| T21 | /workspace/coverage/default/49.prim_present_test.4142117836 | Jun 30 04:25:09 PM PDT 24 | Jun 30 04:25:39 PM PDT 24 | 5525440000 ps | ||
| T22 | /workspace/coverage/default/40.prim_present_test.1877358456 | Jun 30 04:25:14 PM PDT 24 | Jun 30 04:26:10 PM PDT 24 | 10608200000 ps | ||
| T23 | /workspace/coverage/default/43.prim_present_test.311304209 | Jun 30 04:25:06 PM PDT 24 | Jun 30 04:26:21 PM PDT 24 | 14190560000 ps | ||
| T24 | /workspace/coverage/default/6.prim_present_test.761012782 | Jun 30 04:25:02 PM PDT 24 | Jun 30 04:25:55 PM PDT 24 | 9781120000 ps | ||
| T25 | /workspace/coverage/default/46.prim_present_test.2735416597 | Jun 30 04:25:04 PM PDT 24 | Jun 30 04:26:04 PM PDT 24 | 9414700000 ps | ||
| T26 | /workspace/coverage/default/21.prim_present_test.2295699217 | Jun 30 04:25:14 PM PDT 24 | Jun 30 04:26:37 PM PDT 24 | 14636960000 ps | ||
| T27 | /workspace/coverage/default/7.prim_present_test.2330036849 | Jun 30 04:25:15 PM PDT 24 | Jun 30 04:26:28 PM PDT 24 | 13349840000 ps | ||
| T28 | /workspace/coverage/default/41.prim_present_test.443056153 | Jun 30 04:25:09 PM PDT 24 | Jun 30 04:25:55 PM PDT 24 | 8596300000 ps | ||
| T29 | /workspace/coverage/default/25.prim_present_test.2002972673 | Jun 30 04:25:05 PM PDT 24 | Jun 30 04:25:27 PM PDT 24 | 3793780000 ps | ||
| T30 | /workspace/coverage/default/17.prim_present_test.1638307096 | Jun 30 04:25:01 PM PDT 24 | Jun 30 04:25:29 PM PDT 24 | 4762220000 ps | ||
| T31 | /workspace/coverage/default/45.prim_present_test.2361308705 | Jun 30 04:25:10 PM PDT 24 | Jun 30 04:25:55 PM PDT 24 | 7849200000 ps | ||
| T32 | /workspace/coverage/default/36.prim_present_test.1415148400 | Jun 30 04:25:03 PM PDT 24 | Jun 30 04:25:29 PM PDT 24 | 3959940000 ps | ||
| T33 | /workspace/coverage/default/23.prim_present_test.670462770 | Jun 30 04:25:21 PM PDT 24 | Jun 30 04:27:09 PM PDT 24 | 14054780000 ps | ||
| T34 | /workspace/coverage/default/24.prim_present_test.423332250 | Jun 30 04:25:05 PM PDT 24 | Jun 30 04:25:41 PM PDT 24 | 5862720000 ps | ||
| T35 | /workspace/coverage/default/4.prim_present_test.466080763 | Jun 30 04:25:06 PM PDT 24 | Jun 30 04:26:21 PM PDT 24 | 13720600000 ps | ||
| T36 | /workspace/coverage/default/3.prim_present_test.2987854417 | Jun 30 04:25:13 PM PDT 24 | Jun 30 04:26:13 PM PDT 24 | 10133900000 ps | ||
| T37 | /workspace/coverage/default/32.prim_present_test.2848240061 | Jun 30 04:25:01 PM PDT 24 | Jun 30 04:25:42 PM PDT 24 | 6900600000 ps | ||
| T38 | /workspace/coverage/default/27.prim_present_test.312876360 | Jun 30 04:25:21 PM PDT 24 | Jun 30 04:25:40 PM PDT 24 | 3202300000 ps | ||
| T39 | /workspace/coverage/default/35.prim_present_test.3315596499 | Jun 30 04:25:01 PM PDT 24 | Jun 30 04:26:06 PM PDT 24 | 10964700000 ps | ||
| T40 | /workspace/coverage/default/5.prim_present_test.2160408407 | Jun 30 04:25:03 PM PDT 24 | Jun 30 04:26:19 PM PDT 24 | 14815520000 ps | ||
| T41 | /workspace/coverage/default/10.prim_present_test.51658762 | Jun 30 04:26:07 PM PDT 24 | Jun 30 04:26:33 PM PDT 24 | 4774620000 ps | ||
| T42 | /workspace/coverage/default/1.prim_present_test.2642764868 | Jun 30 04:25:51 PM PDT 24 | Jun 30 04:26:38 PM PDT 24 | 9079900000 ps | ||
| T43 | /workspace/coverage/default/20.prim_present_test.535923303 | Jun 30 04:25:06 PM PDT 24 | Jun 30 04:25:57 PM PDT 24 | 9055100000 ps | ||
| T44 | /workspace/coverage/default/33.prim_present_test.2209583126 | Jun 30 04:25:00 PM PDT 24 | Jun 30 04:26:01 PM PDT 24 | 10717940000 ps | ||
| T45 | /workspace/coverage/default/39.prim_present_test.2248440168 | Jun 30 04:25:09 PM PDT 24 | Jun 30 04:26:23 PM PDT 24 | 12775100000 ps | ||
| T46 | /workspace/coverage/default/2.prim_present_test.4109808362 | Jun 30 04:24:52 PM PDT 24 | Jun 30 04:25:43 PM PDT 24 | 8339000000 ps | ||
| T47 | /workspace/coverage/default/9.prim_present_test.3412601488 | Jun 30 04:25:10 PM PDT 24 | Jun 30 04:26:30 PM PDT 24 | 14514820000 ps | ||
| T48 | /workspace/coverage/default/0.prim_present_test.3406894155 | Jun 30 04:26:27 PM PDT 24 | Jun 30 04:27:36 PM PDT 24 | 12480600000 ps | ||
| T49 | /workspace/coverage/default/34.prim_present_test.3900325939 | Jun 30 04:25:14 PM PDT 24 | Jun 30 04:25:52 PM PDT 24 | 5599220000 ps | ||
| T50 | /workspace/coverage/default/28.prim_present_test.2651700628 | Jun 30 04:25:03 PM PDT 24 | Jun 30 04:25:44 PM PDT 24 | 7083500000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.2396229615 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3866940000 ps |
| CPU time | 13.62 seconds |
| Started | Jun 30 04:25:04 PM PDT 24 |
| Finished | Jun 30 04:25:30 PM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-1486db71-c592-47cc-a6ca-86a63dfe2f35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396229615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2396229615 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3406894155 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12480600000 ps |
| CPU time | 37.57 seconds |
| Started | Jun 30 04:26:27 PM PDT 24 |
| Finished | Jun 30 04:27:36 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-6a634dbb-a156-43ad-a0f4-4ff86c974f49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3406894155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3406894155 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2642764868 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 9079900000 ps |
| CPU time | 25.39 seconds |
| Started | Jun 30 04:25:51 PM PDT 24 |
| Finished | Jun 30 04:26:38 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-6b2de1e6-f492-4ae6-a2aa-98a049a9d4c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642764868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2642764868 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.51658762 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4774620000 ps |
| CPU time | 14.17 seconds |
| Started | Jun 30 04:26:07 PM PDT 24 |
| Finished | Jun 30 04:26:33 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-e2ae88bc-0ff5-42fc-ac52-224401036695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51658762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.51658762 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2755478038 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13006980000 ps |
| CPU time | 39.24 seconds |
| Started | Jun 30 04:24:59 PM PDT 24 |
| Finished | Jun 30 04:26:11 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-1746f34d-9918-4d89-a990-d7f6acab20bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755478038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2755478038 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.662617596 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6793340000 ps |
| CPU time | 22.77 seconds |
| Started | Jun 30 04:25:06 PM PDT 24 |
| Finished | Jun 30 04:25:48 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-6fbfe2b9-7478-4cd2-abc4-e9fb737f8865 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662617596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.662617596 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.280172397 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4196780000 ps |
| CPU time | 12.06 seconds |
| Started | Jun 30 04:24:55 PM PDT 24 |
| Finished | Jun 30 04:25:18 PM PDT 24 |
| Peak memory | 144836 kb |
| Host | smart-f88fc563-a859-49fe-a23e-c9de912a5b87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280172397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.280172397 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1298998184 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14539000000 ps |
| CPU time | 56.33 seconds |
| Started | Jun 30 04:25:21 PM PDT 24 |
| Finished | Jun 30 04:27:11 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-65fcdc46-f8cc-4251-9183-1c39feeeb5ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298998184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1298998184 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.672973182 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6660040000 ps |
| CPU time | 21.99 seconds |
| Started | Jun 30 04:25:23 PM PDT 24 |
| Finished | Jun 30 04:26:09 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-186f61e2-26a6-41f8-9979-3fed721681cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672973182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.672973182 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1638307096 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4762220000 ps |
| CPU time | 14.93 seconds |
| Started | Jun 30 04:25:01 PM PDT 24 |
| Finished | Jun 30 04:25:29 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-269d280d-27ba-41e4-9431-3a85749e840a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638307096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1638307096 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.4035736203 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12383880000 ps |
| CPU time | 37.04 seconds |
| Started | Jun 30 04:25:01 PM PDT 24 |
| Finished | Jun 30 04:26:09 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-c1d959a9-6677-4e2c-af44-8394efafc1b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035736203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4035736203 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3479502905 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7015920000 ps |
| CPU time | 20.76 seconds |
| Started | Jun 30 04:25:07 PM PDT 24 |
| Finished | Jun 30 04:25:46 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-46b01f57-d535-4084-aa6d-f952cc81f668 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3479502905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3479502905 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4109808362 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8339000000 ps |
| CPU time | 27.1 seconds |
| Started | Jun 30 04:24:52 PM PDT 24 |
| Finished | Jun 30 04:25:43 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-49bca5a0-19f5-4ae0-91de-dd81b4607630 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109808362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4109808362 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.535923303 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 9055100000 ps |
| CPU time | 27.61 seconds |
| Started | Jun 30 04:25:06 PM PDT 24 |
| Finished | Jun 30 04:25:57 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-06e2ef1c-46bb-4ad4-8e35-37814ae5d1f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535923303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.535923303 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2295699217 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14636960000 ps |
| CPU time | 44.43 seconds |
| Started | Jun 30 04:25:14 PM PDT 24 |
| Finished | Jun 30 04:26:37 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-cf614556-ce38-463d-8bc2-f00c82318339 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295699217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2295699217 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1642342165 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13015040000 ps |
| CPU time | 38.83 seconds |
| Started | Jun 30 04:25:26 PM PDT 24 |
| Finished | Jun 30 04:26:38 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-81cca65b-0d6e-44d9-95e1-8996e2cb4946 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642342165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1642342165 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.670462770 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14054780000 ps |
| CPU time | 55.58 seconds |
| Started | Jun 30 04:25:21 PM PDT 24 |
| Finished | Jun 30 04:27:09 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-76ef9093-9d5b-47c2-b6f1-c9698e2a613e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670462770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.670462770 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.423332250 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5862720000 ps |
| CPU time | 19.25 seconds |
| Started | Jun 30 04:25:05 PM PDT 24 |
| Finished | Jun 30 04:25:41 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-d3f1d893-955a-43e2-bb7b-f737b8bbdef9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423332250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.423332250 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2002972673 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3793780000 ps |
| CPU time | 11.43 seconds |
| Started | Jun 30 04:25:05 PM PDT 24 |
| Finished | Jun 30 04:25:27 PM PDT 24 |
| Peak memory | 144836 kb |
| Host | smart-fa5df751-0762-4bca-a128-0199bf850c8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002972673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2002972673 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.437153359 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5430580000 ps |
| CPU time | 15.05 seconds |
| Started | Jun 30 04:25:10 PM PDT 24 |
| Finished | Jun 30 04:25:38 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-649b9c7f-66b3-4794-bcd6-83f32e05236f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437153359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.437153359 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.312876360 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3202300000 ps |
| CPU time | 10.15 seconds |
| Started | Jun 30 04:25:21 PM PDT 24 |
| Finished | Jun 30 04:25:40 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-3beac366-ce7e-4bee-bfa3-374b159fdf9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312876360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.312876360 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2651700628 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7083500000 ps |
| CPU time | 21.87 seconds |
| Started | Jun 30 04:25:03 PM PDT 24 |
| Finished | Jun 30 04:25:44 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-e1c02d84-c4de-4daa-95da-729f6b616d24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2651700628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2651700628 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3629285054 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10151880000 ps |
| CPU time | 29.29 seconds |
| Started | Jun 30 04:25:01 PM PDT 24 |
| Finished | Jun 30 04:25:55 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-e0ff2398-471b-4e7c-a5c0-eec4c1c0a9bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629285054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3629285054 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2987854417 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10133900000 ps |
| CPU time | 31.67 seconds |
| Started | Jun 30 04:25:13 PM PDT 24 |
| Finished | Jun 30 04:26:13 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-7a1abfa7-b668-41c5-8bdc-00cc02ffd7bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987854417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2987854417 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2287010478 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5710820000 ps |
| CPU time | 18 seconds |
| Started | Jun 30 04:25:02 PM PDT 24 |
| Finished | Jun 30 04:25:36 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-b4d1f709-9e32-46c1-b768-6e8fd346c1a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287010478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2287010478 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2966350784 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12488660000 ps |
| CPU time | 35.78 seconds |
| Started | Jun 30 04:25:33 PM PDT 24 |
| Finished | Jun 30 04:26:39 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-c2cc7bbb-f7d0-4382-9de4-0c197e9def07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2966350784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2966350784 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2848240061 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6900600000 ps |
| CPU time | 21.49 seconds |
| Started | Jun 30 04:25:01 PM PDT 24 |
| Finished | Jun 30 04:25:42 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-09c601ce-fb3e-4550-8576-084f3145f3f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2848240061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2848240061 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2209583126 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10717940000 ps |
| CPU time | 32.5 seconds |
| Started | Jun 30 04:25:00 PM PDT 24 |
| Finished | Jun 30 04:26:01 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-4a8b6ee0-7d54-4c49-8926-31a45fffad39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209583126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2209583126 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3900325939 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5599220000 ps |
| CPU time | 17.77 seconds |
| Started | Jun 30 04:25:14 PM PDT 24 |
| Finished | Jun 30 04:25:52 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-b88d230e-ea72-49a1-8db4-a8fedf3e4ec8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900325939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3900325939 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3315596499 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10964700000 ps |
| CPU time | 34.61 seconds |
| Started | Jun 30 04:25:01 PM PDT 24 |
| Finished | Jun 30 04:26:06 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-83d4e68e-a09f-4b00-b4ea-6b935bfdc537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315596499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3315596499 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1415148400 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3959940000 ps |
| CPU time | 14.01 seconds |
| Started | Jun 30 04:25:03 PM PDT 24 |
| Finished | Jun 30 04:25:29 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-e3bbe948-dc90-4700-b8f1-cee17abba60f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415148400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1415148400 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.689806799 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8399760000 ps |
| CPU time | 27.22 seconds |
| Started | Jun 30 04:25:08 PM PDT 24 |
| Finished | Jun 30 04:25:58 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-0ad9b7d5-d711-4abd-84ab-b6cd66da4ac3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689806799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.689806799 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2099903255 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12012500000 ps |
| CPU time | 38.02 seconds |
| Started | Jun 30 04:25:00 PM PDT 24 |
| Finished | Jun 30 04:26:09 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-22d98550-a32e-4fd2-bf91-ddc158191739 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099903255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2099903255 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2248440168 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12775100000 ps |
| CPU time | 40 seconds |
| Started | Jun 30 04:25:09 PM PDT 24 |
| Finished | Jun 30 04:26:23 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-20e9ee43-e5c5-4f1a-aee7-a17c35787b44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248440168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2248440168 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.466080763 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13720600000 ps |
| CPU time | 40.74 seconds |
| Started | Jun 30 04:25:06 PM PDT 24 |
| Finished | Jun 30 04:26:21 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-2668d47a-1ac1-492c-a82b-c144e2c4727b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466080763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.466080763 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1877358456 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10608200000 ps |
| CPU time | 30.59 seconds |
| Started | Jun 30 04:25:14 PM PDT 24 |
| Finished | Jun 30 04:26:10 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-37ae1ee3-fde2-45bf-b21e-6c55b873a8cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877358456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1877358456 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.443056153 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8596300000 ps |
| CPU time | 25.19 seconds |
| Started | Jun 30 04:25:09 PM PDT 24 |
| Finished | Jun 30 04:25:55 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-41c7f90c-468a-4b97-8430-b872ee3862d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443056153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.443056153 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.259680786 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7820060000 ps |
| CPU time | 24.15 seconds |
| Started | Jun 30 04:25:34 PM PDT 24 |
| Finished | Jun 30 04:26:19 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-5038956a-b78b-454b-9dee-a5ff9d701d9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259680786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.259680786 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.311304209 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14190560000 ps |
| CPU time | 40.54 seconds |
| Started | Jun 30 04:25:06 PM PDT 24 |
| Finished | Jun 30 04:26:21 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-7eab04fe-b7d5-413f-9d91-5e2f5eb823fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311304209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.311304209 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3100488893 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10823960000 ps |
| CPU time | 32.49 seconds |
| Started | Jun 30 04:25:21 PM PDT 24 |
| Finished | Jun 30 04:26:22 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-f35d58e5-499a-45f6-b62f-ed15efc897a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100488893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3100488893 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2361308705 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7849200000 ps |
| CPU time | 24.34 seconds |
| Started | Jun 30 04:25:10 PM PDT 24 |
| Finished | Jun 30 04:25:55 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-820217c2-5a5f-4170-b5af-ccb9ba407f42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361308705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2361308705 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2735416597 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9414700000 ps |
| CPU time | 31.73 seconds |
| Started | Jun 30 04:25:04 PM PDT 24 |
| Finished | Jun 30 04:26:04 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-4f8fa764-4924-4378-9abf-9c9ea8f3434e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735416597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2735416597 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1400445338 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5080280000 ps |
| CPU time | 16.8 seconds |
| Started | Jun 30 04:25:14 PM PDT 24 |
| Finished | Jun 30 04:25:46 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-0025c95e-2d13-4f4d-945a-a5cc0d2a81d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400445338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1400445338 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1608255332 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5725080000 ps |
| CPU time | 22.05 seconds |
| Started | Jun 30 04:25:14 PM PDT 24 |
| Finished | Jun 30 04:25:58 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-7851ec92-4faf-4a88-83b5-27a0be6aed68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608255332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1608255332 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.4142117836 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5525440000 ps |
| CPU time | 16.33 seconds |
| Started | Jun 30 04:25:09 PM PDT 24 |
| Finished | Jun 30 04:25:39 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-dc07bd16-88a7-4aad-a7d6-8157ed30f7c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142117836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4142117836 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2160408407 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14815520000 ps |
| CPU time | 41.98 seconds |
| Started | Jun 30 04:25:03 PM PDT 24 |
| Finished | Jun 30 04:26:19 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-e7ddf839-9971-4352-ab8e-e6a3158b784c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160408407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2160408407 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.761012782 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9781120000 ps |
| CPU time | 28.74 seconds |
| Started | Jun 30 04:25:02 PM PDT 24 |
| Finished | Jun 30 04:25:55 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-86cdc9b9-0a5c-43c5-a7c2-f02fdb2bea2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761012782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.761012782 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2330036849 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13349840000 ps |
| CPU time | 39.08 seconds |
| Started | Jun 30 04:25:15 PM PDT 24 |
| Finished | Jun 30 04:26:28 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-1a994e00-e9d1-4cf8-89e5-79ed781616bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330036849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2330036849 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.518067482 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14596040000 ps |
| CPU time | 44.27 seconds |
| Started | Jun 30 04:25:06 PM PDT 24 |
| Finished | Jun 30 04:26:28 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-4d2daa60-65f2-41b4-8c79-26865db1f9ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=518067482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.518067482 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3412601488 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14514820000 ps |
| CPU time | 43.54 seconds |
| Started | Jun 30 04:25:10 PM PDT 24 |
| Finished | Jun 30 04:26:30 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-77e65206-7dfe-4cac-b697-23f1141b6b8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412601488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3412601488 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |