| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.2233930749 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3429899600 |
| /workspace/coverage/default/1.prim_present_test.219244928 |
| /workspace/coverage/default/10.prim_present_test.2968543453 |
| /workspace/coverage/default/12.prim_present_test.2444856178 |
| /workspace/coverage/default/13.prim_present_test.2577805300 |
| /workspace/coverage/default/14.prim_present_test.2335318125 |
| /workspace/coverage/default/15.prim_present_test.1527855267 |
| /workspace/coverage/default/16.prim_present_test.722454785 |
| /workspace/coverage/default/17.prim_present_test.2132684914 |
| /workspace/coverage/default/18.prim_present_test.333850889 |
| /workspace/coverage/default/19.prim_present_test.3526935520 |
| /workspace/coverage/default/2.prim_present_test.1631338444 |
| /workspace/coverage/default/20.prim_present_test.1666019804 |
| /workspace/coverage/default/21.prim_present_test.3014207084 |
| /workspace/coverage/default/22.prim_present_test.2762825684 |
| /workspace/coverage/default/23.prim_present_test.3240526411 |
| /workspace/coverage/default/24.prim_present_test.1023852531 |
| /workspace/coverage/default/25.prim_present_test.2074478532 |
| /workspace/coverage/default/26.prim_present_test.267708743 |
| /workspace/coverage/default/27.prim_present_test.3594228481 |
| /workspace/coverage/default/28.prim_present_test.2177952853 |
| /workspace/coverage/default/29.prim_present_test.3617411394 |
| /workspace/coverage/default/3.prim_present_test.278253916 |
| /workspace/coverage/default/30.prim_present_test.3187793656 |
| /workspace/coverage/default/31.prim_present_test.2487559464 |
| /workspace/coverage/default/32.prim_present_test.2156715837 |
| /workspace/coverage/default/33.prim_present_test.4076133463 |
| /workspace/coverage/default/34.prim_present_test.2002419980 |
| /workspace/coverage/default/35.prim_present_test.383123033 |
| /workspace/coverage/default/36.prim_present_test.567307139 |
| /workspace/coverage/default/37.prim_present_test.4042521417 |
| /workspace/coverage/default/38.prim_present_test.1490516223 |
| /workspace/coverage/default/39.prim_present_test.1981420087 |
| /workspace/coverage/default/4.prim_present_test.4197573609 |
| /workspace/coverage/default/40.prim_present_test.3895573805 |
| /workspace/coverage/default/41.prim_present_test.4174545782 |
| /workspace/coverage/default/42.prim_present_test.3860095473 |
| /workspace/coverage/default/43.prim_present_test.4062174287 |
| /workspace/coverage/default/44.prim_present_test.3122687112 |
| /workspace/coverage/default/45.prim_present_test.2900689237 |
| /workspace/coverage/default/46.prim_present_test.3565979229 |
| /workspace/coverage/default/47.prim_present_test.1074438455 |
| /workspace/coverage/default/48.prim_present_test.1774864857 |
| /workspace/coverage/default/49.prim_present_test.1449235906 |
| /workspace/coverage/default/5.prim_present_test.2883696202 |
| /workspace/coverage/default/6.prim_present_test.80335941 |
| /workspace/coverage/default/7.prim_present_test.1902462430 |
| /workspace/coverage/default/8.prim_present_test.621819303 |
| /workspace/coverage/default/9.prim_present_test.1921346986 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/11.prim_present_test.2233930749 | Jul 01 10:34:55 AM PDT 24 | Jul 01 10:35:52 AM PDT 24 | 9916900000 ps | ||
| T2 | /workspace/coverage/default/26.prim_present_test.267708743 | Jul 01 10:34:32 AM PDT 24 | Jul 01 10:35:29 AM PDT 24 | 9929920000 ps | ||
| T3 | /workspace/coverage/default/7.prim_present_test.1902462430 | Jul 01 10:34:21 AM PDT 24 | Jul 01 10:34:47 AM PDT 24 | 4022560000 ps | ||
| T4 | /workspace/coverage/default/20.prim_present_test.1666019804 | Jul 01 10:34:29 AM PDT 24 | Jul 01 10:34:54 AM PDT 24 | 3860740000 ps | ||
| T5 | /workspace/coverage/default/22.prim_present_test.2762825684 | Jul 01 10:34:40 AM PDT 24 | Jul 01 10:36:09 AM PDT 24 | 12800520000 ps | ||
| T6 | /workspace/coverage/default/31.prim_present_test.2487559464 | Jul 01 10:34:50 AM PDT 24 | Jul 01 10:35:13 AM PDT 24 | 3122940000 ps | ||
| T7 | /workspace/coverage/default/14.prim_present_test.2335318125 | Jul 01 10:34:32 AM PDT 24 | Jul 01 10:35:05 AM PDT 24 | 5289220000 ps | ||
| T8 | /workspace/coverage/default/2.prim_present_test.1631338444 | Jul 01 10:34:24 AM PDT 24 | Jul 01 10:35:04 AM PDT 24 | 6673680000 ps | ||
| T9 | /workspace/coverage/default/19.prim_present_test.3526935520 | Jul 01 10:34:38 AM PDT 24 | Jul 01 10:35:32 AM PDT 24 | 8770520000 ps | ||
| T10 | /workspace/coverage/default/28.prim_present_test.2177952853 | Jul 01 10:34:48 AM PDT 24 | Jul 01 10:35:21 AM PDT 24 | 5731900000 ps | ||
| T11 | /workspace/coverage/default/18.prim_present_test.333850889 | Jul 01 10:34:43 AM PDT 24 | Jul 01 10:36:13 AM PDT 24 | 14766540000 ps | ||
| T12 | /workspace/coverage/default/23.prim_present_test.3240526411 | Jul 01 10:34:35 AM PDT 24 | Jul 01 10:35:40 AM PDT 24 | 10726620000 ps | ||
| T13 | /workspace/coverage/default/21.prim_present_test.3014207084 | Jul 01 10:34:38 AM PDT 24 | Jul 01 10:35:41 AM PDT 24 | 10118400000 ps | ||
| T14 | /workspace/coverage/default/37.prim_present_test.4042521417 | Jul 01 10:34:31 AM PDT 24 | Jul 01 10:35:23 AM PDT 24 | 8497720000 ps | ||
| T15 | /workspace/coverage/default/10.prim_present_test.2968543453 | Jul 01 10:34:44 AM PDT 24 | Jul 01 10:35:52 AM PDT 24 | 11629340000 ps | ||
| T16 | /workspace/coverage/default/36.prim_present_test.567307139 | Jul 01 10:34:35 AM PDT 24 | Jul 01 10:35:21 AM PDT 24 | 6650740000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.1981420087 | Jul 01 10:34:32 AM PDT 24 | Jul 01 10:35:40 AM PDT 24 | 11413580000 ps | ||
| T18 | /workspace/coverage/default/5.prim_present_test.2883696202 | Jul 01 10:34:28 AM PDT 24 | Jul 01 10:35:08 AM PDT 24 | 7066760000 ps | ||
| T19 | /workspace/coverage/default/6.prim_present_test.80335941 | Jul 01 10:34:28 AM PDT 24 | Jul 01 10:35:35 AM PDT 24 | 11216420000 ps | ||
| T20 | /workspace/coverage/default/44.prim_present_test.3122687112 | Jul 01 10:34:46 AM PDT 24 | Jul 01 10:35:38 AM PDT 24 | 8157960000 ps | ||
| T21 | /workspace/coverage/default/15.prim_present_test.1527855267 | Jul 01 10:34:36 AM PDT 24 | Jul 01 10:35:08 AM PDT 24 | 4330700000 ps | ||
| T22 | /workspace/coverage/default/25.prim_present_test.2074478532 | Jul 01 10:34:47 AM PDT 24 | Jul 01 10:36:02 AM PDT 24 | 10893400000 ps | ||
| T23 | /workspace/coverage/default/12.prim_present_test.2444856178 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:36:27 AM PDT 24 | 14155840000 ps | ||
| T24 | /workspace/coverage/default/16.prim_present_test.722454785 | Jul 01 10:34:37 AM PDT 24 | Jul 01 10:35:32 AM PDT 24 | 10372600000 ps | ||
| T25 | /workspace/coverage/default/33.prim_present_test.4076133463 | Jul 01 10:34:51 AM PDT 24 | Jul 01 10:35:26 AM PDT 24 | 5766620000 ps | ||
| T26 | /workspace/coverage/default/30.prim_present_test.3187793656 | Jul 01 10:34:39 AM PDT 24 | Jul 01 10:36:00 AM PDT 24 | 11884160000 ps | ||
| T27 | /workspace/coverage/default/3.prim_present_test.278253916 | Jul 01 10:34:32 AM PDT 24 | Jul 01 10:35:20 AM PDT 24 | 8104020000 ps | ||
| T28 | /workspace/coverage/default/1.prim_present_test.219244928 | Jul 01 10:34:34 AM PDT 24 | Jul 01 10:36:00 AM PDT 24 | 13533980000 ps | ||
| T29 | /workspace/coverage/default/48.prim_present_test.1774864857 | Jul 01 10:34:53 AM PDT 24 | Jul 01 10:36:01 AM PDT 24 | 11938720000 ps | ||
| T30 | /workspace/coverage/default/32.prim_present_test.2156715837 | Jul 01 10:34:52 AM PDT 24 | Jul 01 10:36:28 AM PDT 24 | 15188140000 ps | ||
| T31 | /workspace/coverage/default/38.prim_present_test.1490516223 | Jul 01 10:34:37 AM PDT 24 | Jul 01 10:36:02 AM PDT 24 | 14819240000 ps | ||
| T32 | /workspace/coverage/default/17.prim_present_test.2132684914 | Jul 01 10:34:39 AM PDT 24 | Jul 01 10:35:04 AM PDT 24 | 3515400000 ps | ||
| T33 | /workspace/coverage/default/4.prim_present_test.4197573609 | Jul 01 10:34:40 AM PDT 24 | Jul 01 10:35:51 AM PDT 24 | 9796620000 ps | ||
| T34 | /workspace/coverage/default/43.prim_present_test.4062174287 | Jul 01 10:34:33 AM PDT 24 | Jul 01 10:36:16 AM PDT 24 | 15420020000 ps | ||
| T35 | /workspace/coverage/default/49.prim_present_test.1449235906 | Jul 01 10:34:54 AM PDT 24 | Jul 01 10:35:24 AM PDT 24 | 5118100000 ps | ||
| T36 | /workspace/coverage/default/29.prim_present_test.3617411394 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:35:17 AM PDT 24 | 6485820000 ps | ||
| T37 | /workspace/coverage/default/42.prim_present_test.3860095473 | Jul 01 10:34:42 AM PDT 24 | Jul 01 10:36:11 AM PDT 24 | 12987760000 ps | ||
| T38 | /workspace/coverage/default/40.prim_present_test.3895573805 | Jul 01 10:34:33 AM PDT 24 | Jul 01 10:35:56 AM PDT 24 | 12539500000 ps | ||
| T39 | /workspace/coverage/default/8.prim_present_test.621819303 | Jul 01 10:34:29 AM PDT 24 | Jul 01 10:35:21 AM PDT 24 | 8922420000 ps | ||
| T40 | /workspace/coverage/default/46.prim_present_test.3565979229 | Jul 01 10:34:38 AM PDT 24 | Jul 01 10:35:53 AM PDT 24 | 14329440000 ps | ||
| T41 | /workspace/coverage/default/24.prim_present_test.1023852531 | Jul 01 10:34:38 AM PDT 24 | Jul 01 10:35:46 AM PDT 24 | 11662820000 ps | ||
| T42 | /workspace/coverage/default/34.prim_present_test.2002419980 | Jul 01 10:34:43 AM PDT 24 | Jul 01 10:35:10 AM PDT 24 | 3911580000 ps | ||
| T43 | /workspace/coverage/default/9.prim_present_test.1921346986 | Jul 01 10:34:37 AM PDT 24 | Jul 01 10:35:56 AM PDT 24 | 13188640000 ps | ||
| T44 | /workspace/coverage/default/35.prim_present_test.383123033 | Jul 01 10:34:38 AM PDT 24 | Jul 01 10:35:32 AM PDT 24 | 8802140000 ps | ||
| T45 | /workspace/coverage/default/41.prim_present_test.4174545782 | Jul 01 10:34:28 AM PDT 24 | Jul 01 10:35:15 AM PDT 24 | 6722660000 ps | ||
| T46 | /workspace/coverage/default/0.prim_present_test.3429899600 | Jul 01 10:34:36 AM PDT 24 | Jul 01 10:35:45 AM PDT 24 | 11288340000 ps | ||
| T47 | /workspace/coverage/default/45.prim_present_test.2900689237 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:36:26 AM PDT 24 | 14085160000 ps | ||
| T48 | /workspace/coverage/default/47.prim_present_test.1074438455 | Jul 01 10:34:55 AM PDT 24 | Jul 01 10:36:10 AM PDT 24 | 12420460000 ps | ||
| T49 | /workspace/coverage/default/13.prim_present_test.2577805300 | Jul 01 10:34:44 AM PDT 24 | Jul 01 10:35:11 AM PDT 24 | 4163300000 ps | ||
| T50 | /workspace/coverage/default/27.prim_present_test.3594228481 | Jul 01 10:34:42 AM PDT 24 | Jul 01 10:35:45 AM PDT 24 | 11354060000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.2233930749 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 9916900000 ps |
| CPU time | 30.12 seconds |
| Started | Jul 01 10:34:55 AM PDT 24 |
| Finished | Jul 01 10:35:52 AM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-35b43e07-1010-4631-9a8a-95d97c679e73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233930749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2233930749 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3429899600 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11288340000 ps |
| CPU time | 37.08 seconds |
| Started | Jul 01 10:34:36 AM PDT 24 |
| Finished | Jul 01 10:35:45 AM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-ee66a197-5f00-4731-a9b4-fef67f2101f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429899600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3429899600 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.219244928 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13533980000 ps |
| CPU time | 45.16 seconds |
| Started | Jul 01 10:34:34 AM PDT 24 |
| Finished | Jul 01 10:36:00 AM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-78d947ae-a73f-40fb-8920-414676e83886 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219244928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.219244928 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2968543453 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11629340000 ps |
| CPU time | 36.04 seconds |
| Started | Jul 01 10:34:44 AM PDT 24 |
| Finished | Jul 01 10:35:52 AM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-344e1d14-7090-41ee-b724-64b730bfc2db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968543453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2968543453 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2444856178 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14155840000 ps |
| CPU time | 45.84 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:36:27 AM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-650a094f-6aef-4461-885f-8767f916c0a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444856178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2444856178 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2577805300 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4163300000 ps |
| CPU time | 14.17 seconds |
| Started | Jul 01 10:34:44 AM PDT 24 |
| Finished | Jul 01 10:35:11 AM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-cb0706d8-4a02-4d4a-8a78-357828331dc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577805300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2577805300 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2335318125 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5289220000 ps |
| CPU time | 17.34 seconds |
| Started | Jul 01 10:34:32 AM PDT 24 |
| Finished | Jul 01 10:35:05 AM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-77859bbb-8ce3-4be1-89dd-62f1c0659bc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335318125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2335318125 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1527855267 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4330700000 ps |
| CPU time | 13.91 seconds |
| Started | Jul 01 10:34:36 AM PDT 24 |
| Finished | Jul 01 10:35:08 AM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-059d0263-6a65-4da8-94e4-c907bde2a6f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527855267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1527855267 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.722454785 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10372600000 ps |
| CPU time | 30.14 seconds |
| Started | Jul 01 10:34:37 AM PDT 24 |
| Finished | Jul 01 10:35:32 AM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-bfae60ed-a96b-4c7d-b69b-13162bdf28cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722454785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.722454785 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2132684914 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3515400000 ps |
| CPU time | 12.87 seconds |
| Started | Jul 01 10:34:39 AM PDT 24 |
| Finished | Jul 01 10:35:04 AM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-5036705e-0c0b-4372-b2ce-bd313e1102a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132684914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2132684914 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.333850889 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14766540000 ps |
| CPU time | 47.99 seconds |
| Started | Jul 01 10:34:43 AM PDT 24 |
| Finished | Jul 01 10:36:13 AM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-295d2f8c-6beb-4cd5-b495-892c24b070c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333850889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.333850889 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3526935520 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8770520000 ps |
| CPU time | 28.84 seconds |
| Started | Jul 01 10:34:38 AM PDT 24 |
| Finished | Jul 01 10:35:32 AM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-5da1c3a8-d869-481f-847b-df55f861bf7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526935520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3526935520 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1631338444 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6673680000 ps |
| CPU time | 21 seconds |
| Started | Jul 01 10:34:24 AM PDT 24 |
| Finished | Jul 01 10:35:04 AM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-d0b7aa72-adf4-454c-b1cc-a0d1d0ee09f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631338444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1631338444 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1666019804 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3860740000 ps |
| CPU time | 13.45 seconds |
| Started | Jul 01 10:34:29 AM PDT 24 |
| Finished | Jul 01 10:34:54 AM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-69b29402-39ec-4c20-87e6-3e73677502e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666019804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1666019804 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3014207084 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10118400000 ps |
| CPU time | 33.61 seconds |
| Started | Jul 01 10:34:38 AM PDT 24 |
| Finished | Jul 01 10:35:41 AM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-89da16cc-7e5e-4e60-b957-607eaf016289 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014207084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3014207084 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2762825684 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12800520000 ps |
| CPU time | 46.41 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:36:09 AM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-e62ced47-098a-4918-bfa7-c74b2e989434 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762825684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2762825684 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3240526411 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10726620000 ps |
| CPU time | 34.65 seconds |
| Started | Jul 01 10:34:35 AM PDT 24 |
| Finished | Jul 01 10:35:40 AM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-fcbb88a9-e3d7-4820-b0a7-44d1c867bd2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240526411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3240526411 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1023852531 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11662820000 ps |
| CPU time | 36.35 seconds |
| Started | Jul 01 10:34:38 AM PDT 24 |
| Finished | Jul 01 10:35:46 AM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-6e7cdbfd-9e60-47f3-9d15-a3cefcdf644d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023852531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1023852531 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2074478532 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10893400000 ps |
| CPU time | 38.9 seconds |
| Started | Jul 01 10:34:47 AM PDT 24 |
| Finished | Jul 01 10:36:02 AM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-29511688-f212-4423-bd87-768c8bd46dbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074478532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2074478532 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.267708743 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9929920000 ps |
| CPU time | 31.19 seconds |
| Started | Jul 01 10:34:32 AM PDT 24 |
| Finished | Jul 01 10:35:29 AM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-73b18c71-d662-43c7-a209-01fd12911a74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267708743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.267708743 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3594228481 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11354060000 ps |
| CPU time | 33.73 seconds |
| Started | Jul 01 10:34:42 AM PDT 24 |
| Finished | Jul 01 10:35:45 AM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-85b94772-6049-482d-9821-2d9b9edbb751 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594228481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3594228481 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2177952853 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5731900000 ps |
| CPU time | 17.5 seconds |
| Started | Jul 01 10:34:48 AM PDT 24 |
| Finished | Jul 01 10:35:21 AM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-0dccb8e4-2b46-4f81-be97-0ecb3b3e3be3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2177952853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2177952853 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3617411394 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6485820000 ps |
| CPU time | 18.99 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:35:17 AM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-f2eb13cc-5bd4-4de8-8857-7153e59c4445 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617411394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3617411394 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.278253916 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8104020000 ps |
| CPU time | 26.2 seconds |
| Started | Jul 01 10:34:32 AM PDT 24 |
| Finished | Jul 01 10:35:20 AM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-80cb59ae-9c22-463b-ab50-ca3969fce107 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=278253916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.278253916 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3187793656 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11884160000 ps |
| CPU time | 42.82 seconds |
| Started | Jul 01 10:34:39 AM PDT 24 |
| Finished | Jul 01 10:36:00 AM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-0ac91491-2d72-49fc-ab87-5a5dc0b46c86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3187793656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3187793656 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2487559464 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3122940000 ps |
| CPU time | 11.39 seconds |
| Started | Jul 01 10:34:50 AM PDT 24 |
| Finished | Jul 01 10:35:13 AM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-d28fee50-d433-43c7-9e74-7108e0f09bee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487559464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2487559464 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2156715837 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 15188140000 ps |
| CPU time | 50.91 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 10:36:28 AM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-53d39e42-c035-48f4-af72-caf37d06ab18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156715837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2156715837 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.4076133463 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5766620000 ps |
| CPU time | 18.45 seconds |
| Started | Jul 01 10:34:51 AM PDT 24 |
| Finished | Jul 01 10:35:26 AM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-ba444d6f-2f48-48fd-b452-d2936f130819 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076133463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.4076133463 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2002419980 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3911580000 ps |
| CPU time | 13.58 seconds |
| Started | Jul 01 10:34:43 AM PDT 24 |
| Finished | Jul 01 10:35:10 AM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-c21fb6c8-4d48-47e6-b315-988062899517 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002419980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2002419980 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.383123033 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8802140000 ps |
| CPU time | 28.83 seconds |
| Started | Jul 01 10:34:38 AM PDT 24 |
| Finished | Jul 01 10:35:32 AM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-1dd91ec0-1000-43ec-9b04-799d1afc3149 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383123033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.383123033 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.567307139 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6650740000 ps |
| CPU time | 24.03 seconds |
| Started | Jul 01 10:34:35 AM PDT 24 |
| Finished | Jul 01 10:35:21 AM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-0f59eed5-b1c1-429d-b115-ed2f68d2a5fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567307139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.567307139 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.4042521417 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8497720000 ps |
| CPU time | 27.9 seconds |
| Started | Jul 01 10:34:31 AM PDT 24 |
| Finished | Jul 01 10:35:23 AM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-c2114bdc-709b-4b2c-b1d7-5b1e01681bfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042521417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.4042521417 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1490516223 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14819240000 ps |
| CPU time | 45.45 seconds |
| Started | Jul 01 10:34:37 AM PDT 24 |
| Finished | Jul 01 10:36:02 AM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-01ea4335-900f-4bf9-b74a-eccc5ab55f3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490516223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1490516223 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1981420087 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11413580000 ps |
| CPU time | 36.39 seconds |
| Started | Jul 01 10:34:32 AM PDT 24 |
| Finished | Jul 01 10:35:40 AM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-bcb6cf73-b9b6-4958-bc86-bcc40569ca1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981420087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1981420087 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4197573609 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9796620000 ps |
| CPU time | 37.34 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:35:51 AM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-518c0334-4d6e-4fa2-b8f6-d913dd19dac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197573609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4197573609 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3895573805 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12539500000 ps |
| CPU time | 44.06 seconds |
| Started | Jul 01 10:34:33 AM PDT 24 |
| Finished | Jul 01 10:35:56 AM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-5258c8e3-40ca-44b6-8ba1-70e60736e61d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895573805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3895573805 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.4174545782 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6722660000 ps |
| CPU time | 24.43 seconds |
| Started | Jul 01 10:34:28 AM PDT 24 |
| Finished | Jul 01 10:35:15 AM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-d78ea425-e3df-4ddf-bcf5-7326a33086c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174545782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4174545782 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3860095473 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12987760000 ps |
| CPU time | 45.98 seconds |
| Started | Jul 01 10:34:42 AM PDT 24 |
| Finished | Jul 01 10:36:11 AM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-9adedf8e-02d3-4f1a-b242-cd798e3da4c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860095473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3860095473 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4062174287 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 15420020000 ps |
| CPU time | 54.13 seconds |
| Started | Jul 01 10:34:33 AM PDT 24 |
| Finished | Jul 01 10:36:16 AM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-cac36068-5995-44e6-8c38-3ec33f9731f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062174287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4062174287 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3122687112 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8157960000 ps |
| CPU time | 27.75 seconds |
| Started | Jul 01 10:34:46 AM PDT 24 |
| Finished | Jul 01 10:35:38 AM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-92dacb10-3ba3-45cc-bd13-d5847838ed3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122687112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3122687112 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2900689237 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14085160000 ps |
| CPU time | 45.06 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:36:26 AM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-1c996913-f32a-49a4-b728-2ffe7f4fb086 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900689237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2900689237 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3565979229 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14329440000 ps |
| CPU time | 40.96 seconds |
| Started | Jul 01 10:34:38 AM PDT 24 |
| Finished | Jul 01 10:35:53 AM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-8f99fb52-bc5f-47ef-8971-54c9339a0471 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3565979229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3565979229 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1074438455 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12420460000 ps |
| CPU time | 39.1 seconds |
| Started | Jul 01 10:34:55 AM PDT 24 |
| Finished | Jul 01 10:36:10 AM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-efeb4578-1e19-407e-a6df-58301c276e3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074438455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1074438455 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1774864857 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11938720000 ps |
| CPU time | 36.67 seconds |
| Started | Jul 01 10:34:53 AM PDT 24 |
| Finished | Jul 01 10:36:01 AM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-40bb83fd-2a99-4faf-b478-5c95e681e4b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774864857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1774864857 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1449235906 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5118100000 ps |
| CPU time | 15.27 seconds |
| Started | Jul 01 10:34:54 AM PDT 24 |
| Finished | Jul 01 10:35:24 AM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-70be7bce-f522-42d9-a27b-1153a29a6734 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449235906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1449235906 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2883696202 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7066760000 ps |
| CPU time | 21.63 seconds |
| Started | Jul 01 10:34:28 AM PDT 24 |
| Finished | Jul 01 10:35:08 AM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-95374819-5a62-4eb0-8307-dea26b242469 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883696202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2883696202 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.80335941 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11216420000 ps |
| CPU time | 35.43 seconds |
| Started | Jul 01 10:34:28 AM PDT 24 |
| Finished | Jul 01 10:35:35 AM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-1cdca164-fbba-4e93-b04d-1ec2edbe7282 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80335941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.80335941 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1902462430 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4022560000 ps |
| CPU time | 13.46 seconds |
| Started | Jul 01 10:34:21 AM PDT 24 |
| Finished | Jul 01 10:34:47 AM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-3dc5f74f-c61c-4eb7-adae-824c15fe5537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902462430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1902462430 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.621819303 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8922420000 ps |
| CPU time | 27.78 seconds |
| Started | Jul 01 10:34:29 AM PDT 24 |
| Finished | Jul 01 10:35:21 AM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-475c0303-6855-47dc-a487-2fc0da26117b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621819303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.621819303 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1921346986 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13188640000 ps |
| CPU time | 41.97 seconds |
| Started | Jul 01 10:34:37 AM PDT 24 |
| Finished | Jul 01 10:35:56 AM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-cfd97d71-d7e9-49db-bf37-516ad6e33320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921346986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1921346986 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |