| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/12.prim_present_test.470404499 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3696975638 |
| /workspace/coverage/default/1.prim_present_test.1186775724 |
| /workspace/coverage/default/10.prim_present_test.738931953 |
| /workspace/coverage/default/11.prim_present_test.1574984688 |
| /workspace/coverage/default/13.prim_present_test.1697427932 |
| /workspace/coverage/default/14.prim_present_test.2837407358 |
| /workspace/coverage/default/15.prim_present_test.2165370651 |
| /workspace/coverage/default/16.prim_present_test.1637367950 |
| /workspace/coverage/default/17.prim_present_test.1362988526 |
| /workspace/coverage/default/18.prim_present_test.248600993 |
| /workspace/coverage/default/19.prim_present_test.3553297939 |
| /workspace/coverage/default/2.prim_present_test.2750600313 |
| /workspace/coverage/default/20.prim_present_test.1296315894 |
| /workspace/coverage/default/21.prim_present_test.4199756384 |
| /workspace/coverage/default/22.prim_present_test.56113126 |
| /workspace/coverage/default/23.prim_present_test.1833848428 |
| /workspace/coverage/default/24.prim_present_test.113589413 |
| /workspace/coverage/default/25.prim_present_test.1055284930 |
| /workspace/coverage/default/26.prim_present_test.1587919581 |
| /workspace/coverage/default/27.prim_present_test.1875475053 |
| /workspace/coverage/default/28.prim_present_test.1982197108 |
| /workspace/coverage/default/29.prim_present_test.2908926364 |
| /workspace/coverage/default/3.prim_present_test.3952344998 |
| /workspace/coverage/default/30.prim_present_test.2660822921 |
| /workspace/coverage/default/31.prim_present_test.1485501642 |
| /workspace/coverage/default/32.prim_present_test.2653347117 |
| /workspace/coverage/default/33.prim_present_test.3012916672 |
| /workspace/coverage/default/34.prim_present_test.2998315361 |
| /workspace/coverage/default/35.prim_present_test.3706597099 |
| /workspace/coverage/default/36.prim_present_test.2752730642 |
| /workspace/coverage/default/37.prim_present_test.1846428590 |
| /workspace/coverage/default/38.prim_present_test.3346543021 |
| /workspace/coverage/default/39.prim_present_test.851118566 |
| /workspace/coverage/default/4.prim_present_test.3873109321 |
| /workspace/coverage/default/40.prim_present_test.3144321175 |
| /workspace/coverage/default/41.prim_present_test.2902132654 |
| /workspace/coverage/default/42.prim_present_test.1004275501 |
| /workspace/coverage/default/43.prim_present_test.235188751 |
| /workspace/coverage/default/44.prim_present_test.3592706076 |
| /workspace/coverage/default/45.prim_present_test.2642993201 |
| /workspace/coverage/default/46.prim_present_test.328496171 |
| /workspace/coverage/default/47.prim_present_test.670245364 |
| /workspace/coverage/default/48.prim_present_test.3355877405 |
| /workspace/coverage/default/49.prim_present_test.2165389346 |
| /workspace/coverage/default/5.prim_present_test.4006345664 |
| /workspace/coverage/default/6.prim_present_test.3849016676 |
| /workspace/coverage/default/7.prim_present_test.2200624239 |
| /workspace/coverage/default/8.prim_present_test.749442938 |
| /workspace/coverage/default/9.prim_present_test.949369617 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/36.prim_present_test.2752730642 | Jul 01 04:21:27 PM PDT 24 | Jul 01 04:22:25 PM PDT 24 | 9456860000 ps | ||
| T2 | /workspace/coverage/default/12.prim_present_test.470404499 | Jul 01 04:18:08 PM PDT 24 | Jul 01 04:19:51 PM PDT 24 | 15132960000 ps | ||
| T3 | /workspace/coverage/default/27.prim_present_test.1875475053 | Jul 01 04:16:51 PM PDT 24 | Jul 01 04:17:57 PM PDT 24 | 9355800000 ps | ||
| T4 | /workspace/coverage/default/16.prim_present_test.1637367950 | Jul 01 04:21:33 PM PDT 24 | Jul 01 04:22:30 PM PDT 24 | 7105200000 ps | ||
| T5 | /workspace/coverage/default/15.prim_present_test.2165370651 | Jul 01 04:16:52 PM PDT 24 | Jul 01 04:17:25 PM PDT 24 | 5181960000 ps | ||
| T6 | /workspace/coverage/default/31.prim_present_test.1485501642 | Jul 01 04:20:51 PM PDT 24 | Jul 01 04:21:14 PM PDT 24 | 3391400000 ps | ||
| T7 | /workspace/coverage/default/7.prim_present_test.2200624239 | Jul 01 04:20:16 PM PDT 24 | Jul 01 04:22:03 PM PDT 24 | 14690280000 ps | ||
| T8 | /workspace/coverage/default/47.prim_present_test.670245364 | Jul 01 04:17:34 PM PDT 24 | Jul 01 04:18:52 PM PDT 24 | 11086840000 ps | ||
| T9 | /workspace/coverage/default/46.prim_present_test.328496171 | Jul 01 04:19:05 PM PDT 24 | Jul 01 04:20:37 PM PDT 24 | 13618300000 ps | ||
| T10 | /workspace/coverage/default/28.prim_present_test.1982197108 | Jul 01 04:21:12 PM PDT 24 | Jul 01 04:21:58 PM PDT 24 | 8136260000 ps | ||
| T11 | /workspace/coverage/default/25.prim_present_test.1055284930 | Jul 01 04:21:01 PM PDT 24 | Jul 01 04:21:40 PM PDT 24 | 5242720000 ps | ||
| T12 | /workspace/coverage/default/42.prim_present_test.1004275501 | Jul 01 04:17:42 PM PDT 24 | Jul 01 04:18:36 PM PDT 24 | 7934140000 ps | ||
| T13 | /workspace/coverage/default/21.prim_present_test.4199756384 | Jul 01 04:21:14 PM PDT 24 | Jul 01 04:22:43 PM PDT 24 | 13413700000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.2902132654 | Jul 01 04:21:53 PM PDT 24 | Jul 01 04:22:37 PM PDT 24 | 5845360000 ps | ||
| T15 | /workspace/coverage/default/34.prim_present_test.2998315361 | Jul 01 04:21:46 PM PDT 24 | Jul 01 04:22:29 PM PDT 24 | 6263860000 ps | ||
| T16 | /workspace/coverage/default/24.prim_present_test.113589413 | Jul 01 04:21:22 PM PDT 24 | Jul 01 04:22:02 PM PDT 24 | 5683540000 ps | ||
| T17 | /workspace/coverage/default/13.prim_present_test.1697427932 | Jul 01 04:17:38 PM PDT 24 | Jul 01 04:18:42 PM PDT 24 | 9604420000 ps | ||
| T18 | /workspace/coverage/default/10.prim_present_test.738931953 | Jul 01 04:18:25 PM PDT 24 | Jul 01 04:19:27 PM PDT 24 | 8908160000 ps | ||
| T19 | /workspace/coverage/default/17.prim_present_test.1362988526 | Jul 01 04:20:45 PM PDT 24 | Jul 01 04:21:25 PM PDT 24 | 7723960000 ps | ||
| T20 | /workspace/coverage/default/40.prim_present_test.3144321175 | Jul 01 04:21:21 PM PDT 24 | Jul 01 04:22:09 PM PDT 24 | 7591900000 ps | ||
| T21 | /workspace/coverage/default/35.prim_present_test.3706597099 | Jul 01 04:21:27 PM PDT 24 | Jul 01 04:21:59 PM PDT 24 | 4733080000 ps | ||
| T22 | /workspace/coverage/default/0.prim_present_test.3696975638 | Jul 01 04:17:40 PM PDT 24 | Jul 01 04:19:24 PM PDT 24 | 13107420000 ps | ||
| T23 | /workspace/coverage/default/11.prim_present_test.1574984688 | Jul 01 04:18:31 PM PDT 24 | Jul 01 04:19:13 PM PDT 24 | 5540320000 ps | ||
| T24 | /workspace/coverage/default/19.prim_present_test.3553297939 | Jul 01 04:21:24 PM PDT 24 | Jul 01 04:22:41 PM PDT 24 | 11729160000 ps | ||
| T25 | /workspace/coverage/default/43.prim_present_test.235188751 | Jul 01 04:21:30 PM PDT 24 | Jul 01 04:21:53 PM PDT 24 | 3294060000 ps | ||
| T26 | /workspace/coverage/default/14.prim_present_test.2837407358 | Jul 01 04:22:21 PM PDT 24 | Jul 01 04:23:25 PM PDT 24 | 9311160000 ps | ||
| T27 | /workspace/coverage/default/18.prim_present_test.248600993 | Jul 01 04:16:38 PM PDT 24 | Jul 01 04:18:20 PM PDT 24 | 14191800000 ps | ||
| T28 | /workspace/coverage/default/2.prim_present_test.2750600313 | Jul 01 04:21:35 PM PDT 24 | Jul 01 04:22:10 PM PDT 24 | 5112520000 ps | ||
| T29 | /workspace/coverage/default/48.prim_present_test.3355877405 | Jul 01 04:21:04 PM PDT 24 | Jul 01 04:21:35 PM PDT 24 | 5045560000 ps | ||
| T30 | /workspace/coverage/default/38.prim_present_test.3346543021 | Jul 01 04:21:30 PM PDT 24 | Jul 01 04:22:05 PM PDT 24 | 5197460000 ps | ||
| T31 | /workspace/coverage/default/6.prim_present_test.3849016676 | Jul 01 04:21:18 PM PDT 24 | Jul 01 04:21:50 PM PDT 24 | 5622160000 ps | ||
| T32 | /workspace/coverage/default/9.prim_present_test.949369617 | Jul 01 04:21:03 PM PDT 24 | Jul 01 04:21:50 PM PDT 24 | 7994280000 ps | ||
| T33 | /workspace/coverage/default/30.prim_present_test.2660822921 | Jul 01 04:20:51 PM PDT 24 | Jul 01 04:22:05 PM PDT 24 | 11629340000 ps | ||
| T34 | /workspace/coverage/default/39.prim_present_test.851118566 | Jul 01 04:21:30 PM PDT 24 | Jul 01 04:22:32 PM PDT 24 | 9703620000 ps | ||
| T35 | /workspace/coverage/default/29.prim_present_test.2908926364 | Jul 01 04:22:09 PM PDT 24 | Jul 01 04:23:12 PM PDT 24 | 8233600000 ps | ||
| T36 | /workspace/coverage/default/22.prim_present_test.56113126 | Jul 01 04:18:37 PM PDT 24 | Jul 01 04:19:06 PM PDT 24 | 4069680000 ps | ||
| T37 | /workspace/coverage/default/20.prim_present_test.1296315894 | Jul 01 04:19:33 PM PDT 24 | Jul 01 04:20:53 PM PDT 24 | 10784280000 ps | ||
| T38 | /workspace/coverage/default/23.prim_present_test.1833848428 | Jul 01 04:20:51 PM PDT 24 | Jul 01 04:21:47 PM PDT 24 | 8777340000 ps | ||
| T39 | /workspace/coverage/default/5.prim_present_test.4006345664 | Jul 01 04:18:20 PM PDT 24 | Jul 01 04:19:31 PM PDT 24 | 10316180000 ps | ||
| T40 | /workspace/coverage/default/4.prim_present_test.3873109321 | Jul 01 04:16:45 PM PDT 24 | Jul 01 04:17:11 PM PDT 24 | 3915920000 ps | ||
| T41 | /workspace/coverage/default/45.prim_present_test.2642993201 | Jul 01 04:21:49 PM PDT 24 | Jul 01 04:22:49 PM PDT 24 | 9696180000 ps | ||
| T42 | /workspace/coverage/default/8.prim_present_test.749442938 | Jul 01 04:16:51 PM PDT 24 | Jul 01 04:18:29 PM PDT 24 | 13992780000 ps | ||
| T43 | /workspace/coverage/default/3.prim_present_test.3952344998 | Jul 01 04:22:11 PM PDT 24 | Jul 01 04:23:42 PM PDT 24 | 11750240000 ps | ||
| T44 | /workspace/coverage/default/44.prim_present_test.3592706076 | Jul 01 04:21:31 PM PDT 24 | Jul 01 04:22:56 PM PDT 24 | 13767720000 ps | ||
| T45 | /workspace/coverage/default/32.prim_present_test.2653347117 | Jul 01 04:21:28 PM PDT 24 | Jul 01 04:22:24 PM PDT 24 | 9049520000 ps | ||
| T46 | /workspace/coverage/default/1.prim_present_test.1186775724 | Jul 01 04:19:33 PM PDT 24 | Jul 01 04:21:09 PM PDT 24 | 12956140000 ps | ||
| T47 | /workspace/coverage/default/37.prim_present_test.1846428590 | Jul 01 04:18:38 PM PDT 24 | Jul 01 04:19:52 PM PDT 24 | 10778080000 ps | ||
| T48 | /workspace/coverage/default/49.prim_present_test.2165389346 | Jul 01 04:21:30 PM PDT 24 | Jul 01 04:22:41 PM PDT 24 | 9922480000 ps | ||
| T49 | /workspace/coverage/default/33.prim_present_test.3012916672 | Jul 01 04:16:54 PM PDT 24 | Jul 01 04:17:21 PM PDT 24 | 4108740000 ps | ||
| T50 | /workspace/coverage/default/26.prim_present_test.1587919581 | Jul 01 04:21:24 PM PDT 24 | Jul 01 04:22:41 PM PDT 24 | 11024840000 ps |
| Test location | /workspace/coverage/default/12.prim_present_test.470404499 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15132960000 ps |
| CPU time | 55.14 seconds |
| Started | Jul 01 04:18:08 PM PDT 24 |
| Finished | Jul 01 04:19:51 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-7bfe227d-44cf-47f2-a9cb-f3189ea652e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470404499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.470404499 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3696975638 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13107420000 ps |
| CPU time | 53.88 seconds |
| Started | Jul 01 04:17:40 PM PDT 24 |
| Finished | Jul 01 04:19:24 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-ae09f3fd-32ad-469f-89f0-6c2c8a0c90db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696975638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3696975638 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1186775724 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12956140000 ps |
| CPU time | 50.31 seconds |
| Started | Jul 01 04:19:33 PM PDT 24 |
| Finished | Jul 01 04:21:09 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-6da5338a-2f26-4b78-bad9-02b76cc21118 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186775724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1186775724 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.738931953 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8908160000 ps |
| CPU time | 32.43 seconds |
| Started | Jul 01 04:18:25 PM PDT 24 |
| Finished | Jul 01 04:19:27 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-d7a8331c-77dc-4c9b-9bdf-d0335d4666d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738931953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.738931953 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1574984688 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5540320000 ps |
| CPU time | 22.2 seconds |
| Started | Jul 01 04:18:31 PM PDT 24 |
| Finished | Jul 01 04:19:13 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-388da3c1-bd09-4381-b2a1-ed6a223c9b3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574984688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1574984688 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1697427932 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9604420000 ps |
| CPU time | 33.48 seconds |
| Started | Jul 01 04:17:38 PM PDT 24 |
| Finished | Jul 01 04:18:42 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-22a1d02e-854f-4cd9-b1b3-985bfbe57ff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697427932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1697427932 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2837407358 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9311160000 ps |
| CPU time | 30.94 seconds |
| Started | Jul 01 04:22:21 PM PDT 24 |
| Finished | Jul 01 04:23:25 PM PDT 24 |
| Peak memory | 143676 kb |
| Host | smart-dd4e8a9e-5c18-49e4-bbe2-003cfafe80d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2837407358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2837407358 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2165370651 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5181960000 ps |
| CPU time | 17.52 seconds |
| Started | Jul 01 04:16:52 PM PDT 24 |
| Finished | Jul 01 04:17:25 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-86ae45cf-d594-4aa3-94c0-56ad756245fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165370651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2165370651 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1637367950 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7105200000 ps |
| CPU time | 28.04 seconds |
| Started | Jul 01 04:21:33 PM PDT 24 |
| Finished | Jul 01 04:22:30 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-fa6547ad-9f04-4d28-ade1-5649629a1f26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637367950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1637367950 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1362988526 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7723960000 ps |
| CPU time | 21.97 seconds |
| Started | Jul 01 04:20:45 PM PDT 24 |
| Finished | Jul 01 04:21:25 PM PDT 24 |
| Peak memory | 144484 kb |
| Host | smart-23f59ea7-b7b8-45cd-aa2d-48c5da831542 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362988526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1362988526 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.248600993 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14191800000 ps |
| CPU time | 53.85 seconds |
| Started | Jul 01 04:16:38 PM PDT 24 |
| Finished | Jul 01 04:18:20 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-e4cef3f3-21ab-4a1f-8873-db86ce1cbdc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248600993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.248600993 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3553297939 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11729160000 ps |
| CPU time | 39.87 seconds |
| Started | Jul 01 04:21:24 PM PDT 24 |
| Finished | Jul 01 04:22:41 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-18893728-9c4c-4cbe-a147-0871d2408792 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553297939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3553297939 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2750600313 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5112520000 ps |
| CPU time | 18.12 seconds |
| Started | Jul 01 04:21:35 PM PDT 24 |
| Finished | Jul 01 04:22:10 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-762a8372-31a7-443a-8148-890620f3d4fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750600313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2750600313 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1296315894 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10784280000 ps |
| CPU time | 41.93 seconds |
| Started | Jul 01 04:19:33 PM PDT 24 |
| Finished | Jul 01 04:20:53 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-ef6db380-8a4a-454f-8b19-4c5a75d98b2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296315894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1296315894 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4199756384 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13413700000 ps |
| CPU time | 47.45 seconds |
| Started | Jul 01 04:21:14 PM PDT 24 |
| Finished | Jul 01 04:22:43 PM PDT 24 |
| Peak memory | 143840 kb |
| Host | smart-2cee8776-f8ac-4ce7-ad8a-6222aaa44f54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4199756384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4199756384 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.56113126 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4069680000 ps |
| CPU time | 14.91 seconds |
| Started | Jul 01 04:18:37 PM PDT 24 |
| Finished | Jul 01 04:19:06 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-77a6e4aa-7399-4a51-9b4f-4dfc5fc2bc67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56113126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.56113126 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1833848428 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8777340000 ps |
| CPU time | 29.63 seconds |
| Started | Jul 01 04:20:51 PM PDT 24 |
| Finished | Jul 01 04:21:47 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-a851e113-3727-4e76-8705-edf312b6ab2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833848428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1833848428 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.113589413 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5683540000 ps |
| CPU time | 20.42 seconds |
| Started | Jul 01 04:21:22 PM PDT 24 |
| Finished | Jul 01 04:22:02 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-6e11b478-2ebb-4af4-b097-34f043a83434 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113589413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.113589413 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1055284930 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5242720000 ps |
| CPU time | 20.32 seconds |
| Started | Jul 01 04:21:01 PM PDT 24 |
| Finished | Jul 01 04:21:40 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-b0d35b30-ad33-49e7-957a-43b8c651f0dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1055284930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1055284930 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1587919581 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11024840000 ps |
| CPU time | 39.81 seconds |
| Started | Jul 01 04:21:24 PM PDT 24 |
| Finished | Jul 01 04:22:41 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-e311941a-852c-4620-89d6-f14f5e7e2204 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587919581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1587919581 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1875475053 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9355800000 ps |
| CPU time | 34.48 seconds |
| Started | Jul 01 04:16:51 PM PDT 24 |
| Finished | Jul 01 04:17:57 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-043f753a-3acf-4777-9141-1be4d774c59e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875475053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1875475053 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1982197108 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8136260000 ps |
| CPU time | 24.71 seconds |
| Started | Jul 01 04:21:12 PM PDT 24 |
| Finished | Jul 01 04:21:58 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-cf441ba6-6ad0-4380-b9da-0571fa1d196c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982197108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1982197108 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2908926364 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8233600000 ps |
| CPU time | 30.53 seconds |
| Started | Jul 01 04:22:09 PM PDT 24 |
| Finished | Jul 01 04:23:12 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-7cee31ca-b1ff-4a84-af90-6179b1b9294e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908926364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2908926364 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3952344998 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11750240000 ps |
| CPU time | 43.82 seconds |
| Started | Jul 01 04:22:11 PM PDT 24 |
| Finished | Jul 01 04:23:42 PM PDT 24 |
| Peak memory | 144020 kb |
| Host | smart-330e38dd-004d-4444-9be7-304f23f196d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952344998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3952344998 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2660822921 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11629340000 ps |
| CPU time | 38.97 seconds |
| Started | Jul 01 04:20:51 PM PDT 24 |
| Finished | Jul 01 04:22:05 PM PDT 24 |
| Peak memory | 144544 kb |
| Host | smart-12f526b8-e3ee-4cb9-aae5-dd1cf7e5e1fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660822921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2660822921 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1485501642 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3391400000 ps |
| CPU time | 11.99 seconds |
| Started | Jul 01 04:20:51 PM PDT 24 |
| Finished | Jul 01 04:21:14 PM PDT 24 |
| Peak memory | 144340 kb |
| Host | smart-b6f62434-f179-4d17-a320-ea33f2f1eed5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1485501642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1485501642 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2653347117 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9049520000 ps |
| CPU time | 29.39 seconds |
| Started | Jul 01 04:21:28 PM PDT 24 |
| Finished | Jul 01 04:22:24 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-ceba1dae-c58b-4077-9b43-fd4e400637fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653347117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2653347117 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3012916672 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4108740000 ps |
| CPU time | 13.92 seconds |
| Started | Jul 01 04:16:54 PM PDT 24 |
| Finished | Jul 01 04:17:21 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-b1accf5d-bf59-4678-9db8-1e1dc8f4bfe4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012916672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3012916672 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2998315361 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6263860000 ps |
| CPU time | 21.86 seconds |
| Started | Jul 01 04:21:46 PM PDT 24 |
| Finished | Jul 01 04:22:29 PM PDT 24 |
| Peak memory | 144852 kb |
| Host | smart-7cd07829-c97d-4f24-b4de-c981d4ac9735 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998315361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2998315361 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3706597099 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4733080000 ps |
| CPU time | 16.05 seconds |
| Started | Jul 01 04:21:27 PM PDT 24 |
| Finished | Jul 01 04:21:59 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-17c6e3b6-1a4c-4d5f-80ce-2e9f302da660 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3706597099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3706597099 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2752730642 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 9456860000 ps |
| CPU time | 30.6 seconds |
| Started | Jul 01 04:21:27 PM PDT 24 |
| Finished | Jul 01 04:22:25 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-1bc57d08-b1a4-4a0b-b292-991ae354028a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752730642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2752730642 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1846428590 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10778080000 ps |
| CPU time | 38.87 seconds |
| Started | Jul 01 04:18:38 PM PDT 24 |
| Finished | Jul 01 04:19:52 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-f8a60a56-4e72-44a9-8691-fa01f0d4dfa2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846428590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1846428590 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3346543021 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5197460000 ps |
| CPU time | 17.88 seconds |
| Started | Jul 01 04:21:30 PM PDT 24 |
| Finished | Jul 01 04:22:05 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-35f3ba76-bd55-45d0-b92e-95ff4288abdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346543021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3346543021 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.851118566 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9703620000 ps |
| CPU time | 32.52 seconds |
| Started | Jul 01 04:21:30 PM PDT 24 |
| Finished | Jul 01 04:22:32 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-a54a675e-c788-45a5-bfdf-c6f94ad2ec4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851118566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.851118566 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3873109321 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3915920000 ps |
| CPU time | 13.59 seconds |
| Started | Jul 01 04:16:45 PM PDT 24 |
| Finished | Jul 01 04:17:11 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-a8636494-80ec-4e34-abf6-d13ae70a56a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873109321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3873109321 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3144321175 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7591900000 ps |
| CPU time | 25.45 seconds |
| Started | Jul 01 04:21:21 PM PDT 24 |
| Finished | Jul 01 04:22:09 PM PDT 24 |
| Peak memory | 143992 kb |
| Host | smart-a6d373f5-035c-4231-b668-545bd6acc2ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3144321175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3144321175 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2902132654 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5845360000 ps |
| CPU time | 21.52 seconds |
| Started | Jul 01 04:21:53 PM PDT 24 |
| Finished | Jul 01 04:22:37 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-5efdc3d6-57c0-41cc-adc0-318c4e611490 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902132654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2902132654 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1004275501 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7934140000 ps |
| CPU time | 28.63 seconds |
| Started | Jul 01 04:17:42 PM PDT 24 |
| Finished | Jul 01 04:18:36 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-1f15925d-092e-412a-a042-24ce7badf4b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004275501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1004275501 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.235188751 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3294060000 ps |
| CPU time | 11.46 seconds |
| Started | Jul 01 04:21:30 PM PDT 24 |
| Finished | Jul 01 04:21:53 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-8a9e2b73-ed2d-447b-95ee-72053529f228 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235188751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.235188751 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3592706076 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13767720000 ps |
| CPU time | 45.09 seconds |
| Started | Jul 01 04:21:31 PM PDT 24 |
| Finished | Jul 01 04:22:56 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-3973bf57-4437-44f8-aa89-9e89dd5ffd37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592706076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3592706076 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2642993201 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9696180000 ps |
| CPU time | 31.57 seconds |
| Started | Jul 01 04:21:49 PM PDT 24 |
| Finished | Jul 01 04:22:49 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-d1127fa7-6a94-4b5c-b28f-c0320e703e58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642993201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2642993201 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.328496171 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13618300000 ps |
| CPU time | 48.37 seconds |
| Started | Jul 01 04:19:05 PM PDT 24 |
| Finished | Jul 01 04:20:37 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-3134873b-6ecf-4f56-8e10-a15dba905667 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328496171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.328496171 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.670245364 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11086840000 ps |
| CPU time | 41.08 seconds |
| Started | Jul 01 04:17:34 PM PDT 24 |
| Finished | Jul 01 04:18:52 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-1aacd32d-fdbb-4da0-bd5b-42ee03c956dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670245364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.670245364 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3355877405 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5045560000 ps |
| CPU time | 15.76 seconds |
| Started | Jul 01 04:21:04 PM PDT 24 |
| Finished | Jul 01 04:21:35 PM PDT 24 |
| Peak memory | 143608 kb |
| Host | smart-894801de-157b-4e7d-a193-f07a60b1bde4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355877405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3355877405 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2165389346 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9922480000 ps |
| CPU time | 36.32 seconds |
| Started | Jul 01 04:21:30 PM PDT 24 |
| Finished | Jul 01 04:22:41 PM PDT 24 |
| Peak memory | 143700 kb |
| Host | smart-e4131f5e-8b6c-44af-bef3-ff797040a9eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165389346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2165389346 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.4006345664 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10316180000 ps |
| CPU time | 37.79 seconds |
| Started | Jul 01 04:18:20 PM PDT 24 |
| Finished | Jul 01 04:19:31 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-82f95c84-f769-42be-8b55-56c75c1f7c09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006345664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.4006345664 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3849016676 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5622160000 ps |
| CPU time | 16.96 seconds |
| Started | Jul 01 04:21:18 PM PDT 24 |
| Finished | Jul 01 04:21:50 PM PDT 24 |
| Peak memory | 144512 kb |
| Host | smart-51c7fa6c-7c5e-441d-9a45-312bb6f960ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849016676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3849016676 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2200624239 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14690280000 ps |
| CPU time | 55.63 seconds |
| Started | Jul 01 04:20:16 PM PDT 24 |
| Finished | Jul 01 04:22:03 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-5a68c5a6-a97d-40a2-8196-b49b3bb24a43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2200624239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2200624239 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.749442938 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13992780000 ps |
| CPU time | 51.73 seconds |
| Started | Jul 01 04:16:51 PM PDT 24 |
| Finished | Jul 01 04:18:29 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-ec37b083-db28-4095-9f17-dbb4c515c62f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749442938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.749442938 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.949369617 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7994280000 ps |
| CPU time | 25.32 seconds |
| Started | Jul 01 04:21:03 PM PDT 24 |
| Finished | Jul 01 04:21:50 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-3eda20ee-e82d-4af8-9edf-798c8fed9bff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949369617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.949369617 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |