| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2073196783 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.998828308 |
| /workspace/coverage/default/10.prim_present_test.3737611309 |
| /workspace/coverage/default/11.prim_present_test.4107637839 |
| /workspace/coverage/default/12.prim_present_test.264817943 |
| /workspace/coverage/default/13.prim_present_test.1193887771 |
| /workspace/coverage/default/14.prim_present_test.1993657365 |
| /workspace/coverage/default/15.prim_present_test.3579934160 |
| /workspace/coverage/default/16.prim_present_test.1172867119 |
| /workspace/coverage/default/17.prim_present_test.121940935 |
| /workspace/coverage/default/18.prim_present_test.3091569705 |
| /workspace/coverage/default/19.prim_present_test.2590069449 |
| /workspace/coverage/default/2.prim_present_test.126451505 |
| /workspace/coverage/default/20.prim_present_test.869123187 |
| /workspace/coverage/default/21.prim_present_test.973937637 |
| /workspace/coverage/default/22.prim_present_test.3815169743 |
| /workspace/coverage/default/23.prim_present_test.2256026786 |
| /workspace/coverage/default/24.prim_present_test.3533222414 |
| /workspace/coverage/default/25.prim_present_test.3363273476 |
| /workspace/coverage/default/26.prim_present_test.3091846939 |
| /workspace/coverage/default/27.prim_present_test.520798519 |
| /workspace/coverage/default/28.prim_present_test.44894086 |
| /workspace/coverage/default/29.prim_present_test.515817641 |
| /workspace/coverage/default/3.prim_present_test.3943818655 |
| /workspace/coverage/default/30.prim_present_test.1904575687 |
| /workspace/coverage/default/31.prim_present_test.381208611 |
| /workspace/coverage/default/32.prim_present_test.3714856903 |
| /workspace/coverage/default/33.prim_present_test.37150591 |
| /workspace/coverage/default/34.prim_present_test.1949758829 |
| /workspace/coverage/default/35.prim_present_test.3971585864 |
| /workspace/coverage/default/36.prim_present_test.1470091972 |
| /workspace/coverage/default/37.prim_present_test.753833841 |
| /workspace/coverage/default/38.prim_present_test.806998868 |
| /workspace/coverage/default/39.prim_present_test.525379047 |
| /workspace/coverage/default/4.prim_present_test.3362925850 |
| /workspace/coverage/default/40.prim_present_test.299101386 |
| /workspace/coverage/default/41.prim_present_test.2744174950 |
| /workspace/coverage/default/42.prim_present_test.2961048937 |
| /workspace/coverage/default/43.prim_present_test.3241445711 |
| /workspace/coverage/default/44.prim_present_test.3288656831 |
| /workspace/coverage/default/45.prim_present_test.3242690991 |
| /workspace/coverage/default/46.prim_present_test.529528085 |
| /workspace/coverage/default/47.prim_present_test.3282648562 |
| /workspace/coverage/default/48.prim_present_test.3399950861 |
| /workspace/coverage/default/49.prim_present_test.3825763743 |
| /workspace/coverage/default/5.prim_present_test.4044618741 |
| /workspace/coverage/default/6.prim_present_test.2481756241 |
| /workspace/coverage/default/7.prim_present_test.3605207632 |
| /workspace/coverage/default/8.prim_present_test.1409808590 |
| /workspace/coverage/default/9.prim_present_test.1180577614 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_present_test.1180577614 | Jul 02 09:13:03 AM PDT 24 | Jul 02 09:14:38 AM PDT 24 | 12652960000 ps | ||
| T2 | /workspace/coverage/default/16.prim_present_test.1172867119 | Jul 02 09:13:13 AM PDT 24 | Jul 02 09:14:17 AM PDT 24 | 9099120000 ps | ||
| T3 | /workspace/coverage/default/1.prim_present_test.998828308 | Jul 02 09:13:07 AM PDT 24 | Jul 02 09:14:46 AM PDT 24 | 15147840000 ps | ||
| T4 | /workspace/coverage/default/0.prim_present_test.2073196783 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:15:00 AM PDT 24 | 15004000000 ps | ||
| T5 | /workspace/coverage/default/31.prim_present_test.381208611 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:14:24 AM PDT 24 | 9860480000 ps | ||
| T6 | /workspace/coverage/default/4.prim_present_test.3362925850 | Jul 02 09:13:09 AM PDT 24 | Jul 02 09:14:42 AM PDT 24 | 11208360000 ps | ||
| T7 | /workspace/coverage/default/10.prim_present_test.3737611309 | Jul 02 09:13:13 AM PDT 24 | Jul 02 09:14:05 AM PDT 24 | 5971220000 ps | ||
| T8 | /workspace/coverage/default/7.prim_present_test.3605207632 | Jul 02 09:13:09 AM PDT 24 | Jul 02 09:14:07 AM PDT 24 | 7766740000 ps | ||
| T9 | /workspace/coverage/default/26.prim_present_test.3091846939 | Jul 02 09:13:13 AM PDT 24 | Jul 02 09:14:12 AM PDT 24 | 7794020000 ps | ||
| T10 | /workspace/coverage/default/34.prim_present_test.1949758829 | Jul 02 09:13:13 AM PDT 24 | Jul 02 09:14:17 AM PDT 24 | 11921360000 ps | ||
| T11 | /workspace/coverage/default/44.prim_present_test.3288656831 | Jul 02 09:13:15 AM PDT 24 | Jul 02 09:14:57 AM PDT 24 | 13409360000 ps | ||
| T12 | /workspace/coverage/default/11.prim_present_test.4107637839 | Jul 02 09:13:15 AM PDT 24 | Jul 02 09:14:08 AM PDT 24 | 6551540000 ps | ||
| T13 | /workspace/coverage/default/22.prim_present_test.3815169743 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:13:54 AM PDT 24 | 4433620000 ps | ||
| T14 | /workspace/coverage/default/6.prim_present_test.2481756241 | Jul 02 09:13:09 AM PDT 24 | Jul 02 09:14:44 AM PDT 24 | 13482520000 ps | ||
| T15 | /workspace/coverage/default/19.prim_present_test.2590069449 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:14:07 AM PDT 24 | 7289340000 ps | ||
| T16 | /workspace/coverage/default/43.prim_present_test.3241445711 | Jul 02 09:13:10 AM PDT 24 | Jul 02 09:13:59 AM PDT 24 | 5850320000 ps | ||
| T17 | /workspace/coverage/default/13.prim_present_test.1193887771 | Jul 02 09:13:13 AM PDT 24 | Jul 02 09:14:19 AM PDT 24 | 12408680000 ps | ||
| T18 | /workspace/coverage/default/33.prim_present_test.37150591 | Jul 02 09:13:11 AM PDT 24 | Jul 02 09:14:45 AM PDT 24 | 12076360000 ps | ||
| T19 | /workspace/coverage/default/27.prim_present_test.520798519 | Jul 02 09:13:06 AM PDT 24 | Jul 02 09:14:20 AM PDT 24 | 11982740000 ps | ||
| T20 | /workspace/coverage/default/46.prim_present_test.529528085 | Jul 02 09:13:17 AM PDT 24 | Jul 02 09:13:56 AM PDT 24 | 4935200000 ps | ||
| T21 | /workspace/coverage/default/30.prim_present_test.1904575687 | Jul 02 09:13:11 AM PDT 24 | Jul 02 09:14:45 AM PDT 24 | 12189200000 ps | ||
| T22 | /workspace/coverage/default/45.prim_present_test.3242690991 | Jul 02 09:13:16 AM PDT 24 | Jul 02 09:14:22 AM PDT 24 | 9551100000 ps | ||
| T23 | /workspace/coverage/default/25.prim_present_test.3363273476 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:14:27 AM PDT 24 | 8914360000 ps | ||
| T24 | /workspace/coverage/default/20.prim_present_test.869123187 | Jul 02 09:13:14 AM PDT 24 | Jul 02 09:14:44 AM PDT 24 | 12277240000 ps | ||
| T25 | /workspace/coverage/default/36.prim_present_test.1470091972 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:14:21 AM PDT 24 | 9344020000 ps | ||
| T26 | /workspace/coverage/default/38.prim_present_test.806998868 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:14:57 AM PDT 24 | 13508560000 ps | ||
| T27 | /workspace/coverage/default/5.prim_present_test.4044618741 | Jul 02 09:13:11 AM PDT 24 | Jul 02 09:14:28 AM PDT 24 | 10637340000 ps | ||
| T28 | /workspace/coverage/default/29.prim_present_test.515817641 | Jul 02 09:13:11 AM PDT 24 | Jul 02 09:14:10 AM PDT 24 | 7646460000 ps | ||
| T29 | /workspace/coverage/default/8.prim_present_test.1409808590 | Jul 02 09:13:09 AM PDT 24 | Jul 02 09:14:00 AM PDT 24 | 6975620000 ps | ||
| T30 | /workspace/coverage/default/18.prim_present_test.3091569705 | Jul 02 09:13:10 AM PDT 24 | Jul 02 09:13:42 AM PDT 24 | 4113080000 ps | ||
| T31 | /workspace/coverage/default/39.prim_present_test.525379047 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:13:47 AM PDT 24 | 3527800000 ps | ||
| T32 | /workspace/coverage/default/37.prim_present_test.753833841 | Jul 02 09:13:06 AM PDT 24 | Jul 02 09:13:57 AM PDT 24 | 6107000000 ps | ||
| T33 | /workspace/coverage/default/3.prim_present_test.3943818655 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:14:14 AM PDT 24 | 8546080000 ps | ||
| T34 | /workspace/coverage/default/2.prim_present_test.126451505 | Jul 02 09:13:09 AM PDT 24 | Jul 02 09:14:56 AM PDT 24 | 13829720000 ps | ||
| T35 | /workspace/coverage/default/40.prim_present_test.299101386 | Jul 02 09:13:08 AM PDT 24 | Jul 02 09:14:35 AM PDT 24 | 11509060000 ps | ||
| T36 | /workspace/coverage/default/49.prim_present_test.3825763743 | Jul 02 09:13:13 AM PDT 24 | Jul 02 09:14:21 AM PDT 24 | 9125160000 ps | ||
| T37 | /workspace/coverage/default/48.prim_present_test.3399950861 | Jul 02 09:13:15 AM PDT 24 | Jul 02 09:14:02 AM PDT 24 | 6825580000 ps | ||
| T38 | /workspace/coverage/default/41.prim_present_test.2744174950 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:13:56 AM PDT 24 | 5442360000 ps | ||
| T39 | /workspace/coverage/default/21.prim_present_test.973937637 | Jul 02 09:13:09 AM PDT 24 | Jul 02 09:14:50 AM PDT 24 | 12612040000 ps | ||
| T40 | /workspace/coverage/default/28.prim_present_test.44894086 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:14:27 AM PDT 24 | 10104760000 ps | ||
| T41 | /workspace/coverage/default/12.prim_present_test.264817943 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:14:12 AM PDT 24 | 9798480000 ps | ||
| T42 | /workspace/coverage/default/35.prim_present_test.3971585864 | Jul 02 09:13:20 AM PDT 24 | Jul 02 09:14:09 AM PDT 24 | 6214880000 ps | ||
| T43 | /workspace/coverage/default/23.prim_present_test.2256026786 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:14:51 AM PDT 24 | 12515940000 ps | ||
| T44 | /workspace/coverage/default/47.prim_present_test.3282648562 | Jul 02 09:13:13 AM PDT 24 | Jul 02 09:14:49 AM PDT 24 | 13713160000 ps | ||
| T45 | /workspace/coverage/default/42.prim_present_test.2961048937 | Jul 02 09:13:13 AM PDT 24 | Jul 02 09:14:41 AM PDT 24 | 12103640000 ps | ||
| T46 | /workspace/coverage/default/24.prim_present_test.3533222414 | Jul 02 09:13:08 AM PDT 24 | Jul 02 09:14:21 AM PDT 24 | 10748940000 ps | ||
| T47 | /workspace/coverage/default/32.prim_present_test.3714856903 | Jul 02 09:13:17 AM PDT 24 | Jul 02 09:14:20 AM PDT 24 | 8070540000 ps | ||
| T48 | /workspace/coverage/default/14.prim_present_test.1993657365 | Jul 02 09:13:07 AM PDT 24 | Jul 02 09:14:20 AM PDT 24 | 10128940000 ps | ||
| T49 | /workspace/coverage/default/15.prim_present_test.3579934160 | Jul 02 09:13:11 AM PDT 24 | Jul 02 09:14:17 AM PDT 24 | 8835620000 ps | ||
| T50 | /workspace/coverage/default/17.prim_present_test.121940935 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:14:34 AM PDT 24 | 10832020000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2073196783 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15004000000 ps |
| CPU time | 54.85 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:15:00 AM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-f1251e19-1777-4bcc-87a5-7e39e94f6349 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073196783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2073196783 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.998828308 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 15147840000 ps |
| CPU time | 50.73 seconds |
| Started | Jul 02 09:13:07 AM PDT 24 |
| Finished | Jul 02 09:14:46 AM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-578b991c-d6fc-4b28-b245-01a6b927631f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998828308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.998828308 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3737611309 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5971220000 ps |
| CPU time | 24.18 seconds |
| Started | Jul 02 09:13:13 AM PDT 24 |
| Finished | Jul 02 09:14:05 AM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-55321d27-3727-4323-8e43-ce2580920e04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737611309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3737611309 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4107637839 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6551540000 ps |
| CPU time | 25.58 seconds |
| Started | Jul 02 09:13:15 AM PDT 24 |
| Finished | Jul 02 09:14:08 AM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-c30520f1-52d5-43b1-a4df-d0575b58edd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4107637839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4107637839 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.264817943 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9798480000 ps |
| CPU time | 29.46 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:14:12 AM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-2abbc8c7-9aac-4b48-a7e8-d1e37206bece |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264817943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.264817943 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1193887771 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12408680000 ps |
| CPU time | 33.07 seconds |
| Started | Jul 02 09:13:13 AM PDT 24 |
| Finished | Jul 02 09:14:19 AM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-4c3c7a52-22b4-4c0a-bb7b-e5e376d31240 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1193887771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1193887771 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1993657365 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10128940000 ps |
| CPU time | 37.11 seconds |
| Started | Jul 02 09:13:07 AM PDT 24 |
| Finished | Jul 02 09:14:20 AM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-21d5fce6-c1e5-41f0-8867-008d8540e602 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993657365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1993657365 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3579934160 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8835620000 ps |
| CPU time | 32.03 seconds |
| Started | Jul 02 09:13:11 AM PDT 24 |
| Finished | Jul 02 09:14:17 AM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-df132433-445a-4645-aa0f-9d1eecc139ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579934160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3579934160 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1172867119 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9099120000 ps |
| CPU time | 31.7 seconds |
| Started | Jul 02 09:13:13 AM PDT 24 |
| Finished | Jul 02 09:14:17 AM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-eab74a16-a4e9-4ef1-851c-bd4b6059277b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1172867119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1172867119 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.121940935 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10832020000 ps |
| CPU time | 39.86 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:14:34 AM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-9504acd4-bc21-497a-93dd-8ef9d9756f73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121940935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.121940935 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3091569705 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4113080000 ps |
| CPU time | 14.61 seconds |
| Started | Jul 02 09:13:10 AM PDT 24 |
| Finished | Jul 02 09:13:42 AM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-a1888723-f0f8-472c-9cd5-67119ffb2985 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091569705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3091569705 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2590069449 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7289340000 ps |
| CPU time | 26.53 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:14:07 AM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-74f2faef-3c84-4e4c-b227-a74dd9b9cccf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590069449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2590069449 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.126451505 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13829720000 ps |
| CPU time | 53.06 seconds |
| Started | Jul 02 09:13:09 AM PDT 24 |
| Finished | Jul 02 09:14:56 AM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-7daf708b-e1e5-4a8e-b34c-50e03e0de5c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126451505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.126451505 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.869123187 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12277240000 ps |
| CPU time | 44.59 seconds |
| Started | Jul 02 09:13:14 AM PDT 24 |
| Finished | Jul 02 09:14:44 AM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-f67a5222-e32a-4f29-a27f-ff4d4a7bccbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869123187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.869123187 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.973937637 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12612040000 ps |
| CPU time | 49.67 seconds |
| Started | Jul 02 09:13:09 AM PDT 24 |
| Finished | Jul 02 09:14:50 AM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-8a10e2a3-033f-4023-ac0e-2f080328fccf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973937637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.973937637 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3815169743 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4433620000 ps |
| CPU time | 19.08 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:13:54 AM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-187ef1c3-13aa-4a39-90aa-e1e60ca544f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815169743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3815169743 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2256026786 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12515940000 ps |
| CPU time | 46.82 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:14:51 AM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-9063a728-c859-4bc2-a4a6-ac702d990db7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256026786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2256026786 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3533222414 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10748940000 ps |
| CPU time | 37.07 seconds |
| Started | Jul 02 09:13:08 AM PDT 24 |
| Finished | Jul 02 09:14:21 AM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-386cfa03-6d60-489f-9e56-58fa25bfd190 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533222414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3533222414 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3363273476 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8914360000 ps |
| CPU time | 34.75 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:14:27 AM PDT 24 |
| Peak memory | 144796 kb |
| Host | smart-6e48fc14-61a5-4a06-a35f-6b4c7abb060d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363273476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3363273476 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3091846939 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7794020000 ps |
| CPU time | 28.39 seconds |
| Started | Jul 02 09:13:13 AM PDT 24 |
| Finished | Jul 02 09:14:12 AM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-dfa89877-2b54-42be-adb0-f3644debb62a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091846939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3091846939 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.520798519 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11982740000 ps |
| CPU time | 38.87 seconds |
| Started | Jul 02 09:13:06 AM PDT 24 |
| Finished | Jul 02 09:14:20 AM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-23e4c795-beb8-4381-94ae-7f15c6fcba60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520798519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.520798519 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.44894086 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10104760000 ps |
| CPU time | 36.62 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:14:27 AM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-94713f57-1eca-4e55-9d5a-aaa783e762f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44894086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.44894086 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.515817641 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7646460000 ps |
| CPU time | 28.03 seconds |
| Started | Jul 02 09:13:11 AM PDT 24 |
| Finished | Jul 02 09:14:10 AM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-bbf2387f-80ab-4a4d-adbf-d6242d29bb64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515817641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.515817641 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3943818655 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8546080000 ps |
| CPU time | 29.29 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:14:14 AM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-5ec5f1a0-c081-4ad6-920b-c6ab01f581b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943818655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3943818655 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1904575687 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12189200000 ps |
| CPU time | 46.59 seconds |
| Started | Jul 02 09:13:11 AM PDT 24 |
| Finished | Jul 02 09:14:45 AM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-88d23302-7d59-4be3-b62c-9e2853437cab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904575687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1904575687 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.381208611 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9860480000 ps |
| CPU time | 35.66 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:14:24 AM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-ca9afc1e-fa70-49ba-923f-4e63595ce32a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381208611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.381208611 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3714856903 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8070540000 ps |
| CPU time | 30.85 seconds |
| Started | Jul 02 09:13:17 AM PDT 24 |
| Finished | Jul 02 09:14:20 AM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-46783fbf-f5bd-445d-8507-a55cfc3b7a6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714856903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3714856903 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.37150591 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12076360000 ps |
| CPU time | 45.69 seconds |
| Started | Jul 02 09:13:11 AM PDT 24 |
| Finished | Jul 02 09:14:45 AM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-06613532-c10e-4f49-94db-68c3e98a8a79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37150591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.37150591 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1949758829 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11921360000 ps |
| CPU time | 31.53 seconds |
| Started | Jul 02 09:13:13 AM PDT 24 |
| Finished | Jul 02 09:14:17 AM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-f64febbf-4d8e-4c00-89f8-4ecffe58ba77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949758829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1949758829 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3971585864 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6214880000 ps |
| CPU time | 25.09 seconds |
| Started | Jul 02 09:13:20 AM PDT 24 |
| Finished | Jul 02 09:14:09 AM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-4cea3dcf-1f85-43e5-b6d2-a0216d1e17a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3971585864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3971585864 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1470091972 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9344020000 ps |
| CPU time | 33.66 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:14:21 AM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-46a3b93d-a5d6-4883-bfe6-fbfaf6b29e96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470091972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1470091972 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.753833841 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6107000000 ps |
| CPU time | 25.29 seconds |
| Started | Jul 02 09:13:06 AM PDT 24 |
| Finished | Jul 02 09:13:57 AM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-15daa24f-fa1e-4a99-9890-f7fcb5ed23f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753833841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.753833841 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.806998868 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13508560000 ps |
| CPU time | 50.45 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:14:57 AM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-3b6f7ba9-8c4a-40c6-8c24-7138eafe18d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806998868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.806998868 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.525379047 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3527800000 ps |
| CPU time | 13.52 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:13:47 AM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-2ad85e19-7ef9-42a6-8942-bf1adea0e05b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525379047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.525379047 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3362925850 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11208360000 ps |
| CPU time | 45.09 seconds |
| Started | Jul 02 09:13:09 AM PDT 24 |
| Finished | Jul 02 09:14:42 AM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-cdcf726f-0973-475a-a152-3684695f81aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362925850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3362925850 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.299101386 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11509060000 ps |
| CPU time | 43.65 seconds |
| Started | Jul 02 09:13:08 AM PDT 24 |
| Finished | Jul 02 09:14:35 AM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-54ba2f9f-fa7c-486c-b1b4-5e44a1fd52df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=299101386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.299101386 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2744174950 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5442360000 ps |
| CPU time | 20.5 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:13:56 AM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-65d5b70c-b0d5-46a3-bccf-d2ac52a8d1bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744174950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2744174950 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2961048937 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12103640000 ps |
| CPU time | 44.02 seconds |
| Started | Jul 02 09:13:13 AM PDT 24 |
| Finished | Jul 02 09:14:41 AM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-3790d61d-ab2f-4311-83b0-110117632217 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961048937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2961048937 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3241445711 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5850320000 ps |
| CPU time | 23.1 seconds |
| Started | Jul 02 09:13:10 AM PDT 24 |
| Finished | Jul 02 09:13:59 AM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-3c0e0e1d-9248-40d0-92e1-688432064005 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241445711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3241445711 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3288656831 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13409360000 ps |
| CPU time | 51.28 seconds |
| Started | Jul 02 09:13:15 AM PDT 24 |
| Finished | Jul 02 09:14:57 AM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-27ad5db7-650e-47a7-b750-60f2fc190d59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288656831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3288656831 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3242690991 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9551100000 ps |
| CPU time | 32.94 seconds |
| Started | Jul 02 09:13:16 AM PDT 24 |
| Finished | Jul 02 09:14:22 AM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-af0f7f9d-f626-488b-a192-60243657d970 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3242690991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3242690991 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.529528085 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4935200000 ps |
| CPU time | 19.17 seconds |
| Started | Jul 02 09:13:17 AM PDT 24 |
| Finished | Jul 02 09:13:56 AM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-d5e063f5-6c99-4617-b000-2a5fd02133ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=529528085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.529528085 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3282648562 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13713160000 ps |
| CPU time | 48.06 seconds |
| Started | Jul 02 09:13:13 AM PDT 24 |
| Finished | Jul 02 09:14:49 AM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-d0d9f074-b936-47ed-8357-241eb35ee6f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282648562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3282648562 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3399950861 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6825580000 ps |
| CPU time | 22.41 seconds |
| Started | Jul 02 09:13:15 AM PDT 24 |
| Finished | Jul 02 09:14:02 AM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-a9dffe54-162b-4406-8f58-10f1e0afddc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399950861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3399950861 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3825763743 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9125160000 ps |
| CPU time | 32.87 seconds |
| Started | Jul 02 09:13:13 AM PDT 24 |
| Finished | Jul 02 09:14:21 AM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-b91c2f66-93e0-48c2-8cae-b1f1ace613c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825763743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3825763743 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.4044618741 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10637340000 ps |
| CPU time | 37.19 seconds |
| Started | Jul 02 09:13:11 AM PDT 24 |
| Finished | Jul 02 09:14:28 AM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-053ee2c0-ede5-4273-99ac-14f3f8bc08d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044618741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.4044618741 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2481756241 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13482520000 ps |
| CPU time | 47.46 seconds |
| Started | Jul 02 09:13:09 AM PDT 24 |
| Finished | Jul 02 09:14:44 AM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-46021db3-e016-47ea-9a12-906825dc810e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481756241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2481756241 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3605207632 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7766740000 ps |
| CPU time | 27.74 seconds |
| Started | Jul 02 09:13:09 AM PDT 24 |
| Finished | Jul 02 09:14:07 AM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-924909b9-1cf9-437a-8b53-9dde99bfb5cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605207632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3605207632 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1409808590 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6975620000 ps |
| CPU time | 24.63 seconds |
| Started | Jul 02 09:13:09 AM PDT 24 |
| Finished | Jul 02 09:14:00 AM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-4e4ad8dc-5a08-4d79-a834-9bd1af3673c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409808590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1409808590 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1180577614 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12652960000 ps |
| CPU time | 48.7 seconds |
| Started | Jul 02 09:13:03 AM PDT 24 |
| Finished | Jul 02 09:14:38 AM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-e94b13cb-e9b1-4624-a86d-6318f25ba052 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180577614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1180577614 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |