| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/13.prim_present_test.4169853694 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2864173846 |
| /workspace/coverage/default/1.prim_present_test.3222992274 |
| /workspace/coverage/default/10.prim_present_test.1205801641 |
| /workspace/coverage/default/11.prim_present_test.566953103 |
| /workspace/coverage/default/12.prim_present_test.3167269861 |
| /workspace/coverage/default/14.prim_present_test.3409215949 |
| /workspace/coverage/default/15.prim_present_test.844892178 |
| /workspace/coverage/default/16.prim_present_test.2265504285 |
| /workspace/coverage/default/17.prim_present_test.252372338 |
| /workspace/coverage/default/18.prim_present_test.1253572091 |
| /workspace/coverage/default/19.prim_present_test.4047526355 |
| /workspace/coverage/default/2.prim_present_test.3243404859 |
| /workspace/coverage/default/20.prim_present_test.1672699976 |
| /workspace/coverage/default/21.prim_present_test.1398490485 |
| /workspace/coverage/default/22.prim_present_test.2940624266 |
| /workspace/coverage/default/23.prim_present_test.3191890452 |
| /workspace/coverage/default/24.prim_present_test.2314418282 |
| /workspace/coverage/default/25.prim_present_test.968572017 |
| /workspace/coverage/default/26.prim_present_test.712940859 |
| /workspace/coverage/default/27.prim_present_test.3809162398 |
| /workspace/coverage/default/28.prim_present_test.3620981306 |
| /workspace/coverage/default/29.prim_present_test.125379867 |
| /workspace/coverage/default/3.prim_present_test.2880341685 |
| /workspace/coverage/default/30.prim_present_test.2286026642 |
| /workspace/coverage/default/31.prim_present_test.933866328 |
| /workspace/coverage/default/32.prim_present_test.3675063568 |
| /workspace/coverage/default/33.prim_present_test.113258708 |
| /workspace/coverage/default/34.prim_present_test.2263171103 |
| /workspace/coverage/default/35.prim_present_test.1939805648 |
| /workspace/coverage/default/36.prim_present_test.463912142 |
| /workspace/coverage/default/37.prim_present_test.805365704 |
| /workspace/coverage/default/38.prim_present_test.585604538 |
| /workspace/coverage/default/39.prim_present_test.945785533 |
| /workspace/coverage/default/4.prim_present_test.4292351804 |
| /workspace/coverage/default/40.prim_present_test.4241930524 |
| /workspace/coverage/default/41.prim_present_test.3424809484 |
| /workspace/coverage/default/42.prim_present_test.522357479 |
| /workspace/coverage/default/43.prim_present_test.1181132208 |
| /workspace/coverage/default/44.prim_present_test.3891693966 |
| /workspace/coverage/default/45.prim_present_test.4170812881 |
| /workspace/coverage/default/46.prim_present_test.1765621943 |
| /workspace/coverage/default/47.prim_present_test.1271134616 |
| /workspace/coverage/default/48.prim_present_test.3608371780 |
| /workspace/coverage/default/49.prim_present_test.1202937936 |
| /workspace/coverage/default/5.prim_present_test.1740381347 |
| /workspace/coverage/default/6.prim_present_test.3311254510 |
| /workspace/coverage/default/7.prim_present_test.800263877 |
| /workspace/coverage/default/8.prim_present_test.2435540009 |
| /workspace/coverage/default/9.prim_present_test.975386833 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/42.prim_present_test.522357479 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:00:59 PM PDT 24 | 4922800000 ps | ||
| T2 | /workspace/coverage/default/6.prim_present_test.3311254510 | Jul 03 05:00:22 PM PDT 24 | Jul 03 05:01:23 PM PDT 24 | 8787260000 ps | ||
| T3 | /workspace/coverage/default/8.prim_present_test.2435540009 | Jul 03 05:00:19 PM PDT 24 | Jul 03 05:01:28 PM PDT 24 | 10722280000 ps | ||
| T4 | /workspace/coverage/default/21.prim_present_test.1398490485 | Jul 03 05:00:17 PM PDT 24 | Jul 03 05:00:42 PM PDT 24 | 3254380000 ps | ||
| T5 | /workspace/coverage/default/7.prim_present_test.800263877 | Jul 03 05:00:19 PM PDT 24 | Jul 03 05:01:13 PM PDT 24 | 8453700000 ps | ||
| T6 | /workspace/coverage/default/13.prim_present_test.4169853694 | Jul 03 05:00:18 PM PDT 24 | Jul 03 05:02:09 PM PDT 24 | 14617740000 ps | ||
| T7 | /workspace/coverage/default/15.prim_present_test.844892178 | Jul 03 05:00:20 PM PDT 24 | Jul 03 05:01:04 PM PDT 24 | 7381100000 ps | ||
| T8 | /workspace/coverage/default/47.prim_present_test.1271134616 | Jul 03 05:00:25 PM PDT 24 | Jul 03 05:01:04 PM PDT 24 | 5649440000 ps | ||
| T9 | /workspace/coverage/default/4.prim_present_test.4292351804 | Jul 03 05:00:22 PM PDT 24 | Jul 03 05:01:31 PM PDT 24 | 8807100000 ps | ||
| T10 | /workspace/coverage/default/25.prim_present_test.968572017 | Jul 03 05:00:25 PM PDT 24 | Jul 03 05:01:57 PM PDT 24 | 14607200000 ps | ||
| T11 | /workspace/coverage/default/29.prim_present_test.125379867 | Jul 03 05:00:25 PM PDT 24 | Jul 03 05:02:01 PM PDT 24 | 15253860000 ps | ||
| T12 | /workspace/coverage/default/45.prim_present_test.4170812881 | Jul 03 05:00:25 PM PDT 24 | Jul 03 05:01:58 PM PDT 24 | 13188020000 ps | ||
| T13 | /workspace/coverage/default/3.prim_present_test.2880341685 | Jul 03 05:00:18 PM PDT 24 | Jul 03 05:01:42 PM PDT 24 | 11943060000 ps | ||
| T14 | /workspace/coverage/default/39.prim_present_test.945785533 | Jul 03 05:00:25 PM PDT 24 | Jul 03 05:01:23 PM PDT 24 | 7025220000 ps | ||
| T15 | /workspace/coverage/default/11.prim_present_test.566953103 | Jul 03 05:00:19 PM PDT 24 | Jul 03 05:01:44 PM PDT 24 | 13452140000 ps | ||
| T16 | /workspace/coverage/default/34.prim_present_test.2263171103 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:01:16 PM PDT 24 | 7320340000 ps | ||
| T17 | /workspace/coverage/default/18.prim_present_test.1253572091 | Jul 03 05:00:19 PM PDT 24 | Jul 03 05:01:45 PM PDT 24 | 14353000000 ps | ||
| T18 | /workspace/coverage/default/26.prim_present_test.712940859 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:01:12 PM PDT 24 | 6492020000 ps | ||
| T19 | /workspace/coverage/default/10.prim_present_test.1205801641 | Jul 03 05:00:21 PM PDT 24 | Jul 03 05:00:56 PM PDT 24 | 5221640000 ps | ||
| T20 | /workspace/coverage/default/23.prim_present_test.3191890452 | Jul 03 05:00:20 PM PDT 24 | Jul 03 05:01:15 PM PDT 24 | 6813800000 ps | ||
| T21 | /workspace/coverage/default/49.prim_present_test.1202937936 | Jul 03 05:00:22 PM PDT 24 | Jul 03 05:01:19 PM PDT 24 | 9193360000 ps | ||
| T22 | /workspace/coverage/default/12.prim_present_test.3167269861 | Jul 03 05:00:20 PM PDT 24 | Jul 03 05:01:14 PM PDT 24 | 6575720000 ps | ||
| T23 | /workspace/coverage/default/46.prim_present_test.1765621943 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:00:58 PM PDT 24 | 4464000000 ps | ||
| T24 | /workspace/coverage/default/19.prim_present_test.4047526355 | Jul 03 05:00:21 PM PDT 24 | Jul 03 05:00:51 PM PDT 24 | 4826080000 ps | ||
| T25 | /workspace/coverage/default/33.prim_present_test.113258708 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:01:56 PM PDT 24 | 13499880000 ps | ||
| T26 | /workspace/coverage/default/22.prim_present_test.2940624266 | Jul 03 05:00:20 PM PDT 24 | Jul 03 05:01:11 PM PDT 24 | 8638460000 ps | ||
| T27 | /workspace/coverage/default/20.prim_present_test.1672699976 | Jul 03 05:00:20 PM PDT 24 | Jul 03 05:00:57 PM PDT 24 | 5360520000 ps | ||
| T28 | /workspace/coverage/default/17.prim_present_test.252372338 | Jul 03 05:00:21 PM PDT 24 | Jul 03 05:01:48 PM PDT 24 | 12967300000 ps | ||
| T29 | /workspace/coverage/default/32.prim_present_test.3675063568 | Jul 03 05:00:20 PM PDT 24 | Jul 03 05:01:18 PM PDT 24 | 9437640000 ps | ||
| T30 | /workspace/coverage/default/35.prim_present_test.1939805648 | Jul 03 05:00:19 PM PDT 24 | Jul 03 05:01:03 PM PDT 24 | 6587500000 ps | ||
| T31 | /workspace/coverage/default/30.prim_present_test.2286026642 | Jul 03 05:00:21 PM PDT 24 | Jul 03 05:01:43 PM PDT 24 | 13888000000 ps | ||
| T32 | /workspace/coverage/default/48.prim_present_test.3608371780 | Jul 03 05:00:25 PM PDT 24 | Jul 03 05:01:40 PM PDT 24 | 11398700000 ps | ||
| T33 | /workspace/coverage/default/9.prim_present_test.975386833 | Jul 03 05:00:18 PM PDT 24 | Jul 03 05:01:24 PM PDT 24 | 11084360000 ps | ||
| T34 | /workspace/coverage/default/0.prim_present_test.2864173846 | Jul 03 05:00:19 PM PDT 24 | Jul 03 05:01:29 PM PDT 24 | 8738900000 ps | ||
| T35 | /workspace/coverage/default/38.prim_present_test.585604538 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:01:01 PM PDT 24 | 4888700000 ps | ||
| T36 | /workspace/coverage/default/31.prim_present_test.933866328 | Jul 03 05:00:22 PM PDT 24 | Jul 03 05:01:14 PM PDT 24 | 8374340000 ps | ||
| T37 | /workspace/coverage/default/1.prim_present_test.3222992274 | Jul 03 05:00:15 PM PDT 24 | Jul 03 05:00:50 PM PDT 24 | 5245200000 ps | ||
| T38 | /workspace/coverage/default/27.prim_present_test.3809162398 | Jul 03 05:00:25 PM PDT 24 | Jul 03 05:01:11 PM PDT 24 | 6630280000 ps | ||
| T39 | /workspace/coverage/default/24.prim_present_test.2314418282 | Jul 03 05:00:18 PM PDT 24 | Jul 03 05:00:56 PM PDT 24 | 5059820000 ps | ||
| T40 | /workspace/coverage/default/2.prim_present_test.3243404859 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:01:48 PM PDT 24 | 13157020000 ps | ||
| T41 | /workspace/coverage/default/5.prim_present_test.1740381347 | Jul 03 05:00:19 PM PDT 24 | Jul 03 05:01:08 PM PDT 24 | 7138060000 ps | ||
| T42 | /workspace/coverage/default/36.prim_present_test.463912142 | Jul 03 05:00:20 PM PDT 24 | Jul 03 05:01:05 PM PDT 24 | 6070420000 ps | ||
| T43 | /workspace/coverage/default/41.prim_present_test.3424809484 | Jul 03 05:00:22 PM PDT 24 | Jul 03 05:01:26 PM PDT 24 | 8232360000 ps | ||
| T44 | /workspace/coverage/default/16.prim_present_test.2265504285 | Jul 03 05:00:16 PM PDT 24 | Jul 03 05:01:06 PM PDT 24 | 7391020000 ps | ||
| T45 | /workspace/coverage/default/43.prim_present_test.1181132208 | Jul 03 05:00:24 PM PDT 24 | Jul 03 05:01:05 PM PDT 24 | 6392820000 ps | ||
| T46 | /workspace/coverage/default/37.prim_present_test.805365704 | Jul 03 05:00:21 PM PDT 24 | Jul 03 05:00:49 PM PDT 24 | 3543920000 ps | ||
| T47 | /workspace/coverage/default/14.prim_present_test.3409215949 | Jul 03 05:00:21 PM PDT 24 | Jul 03 05:00:47 PM PDT 24 | 3897940000 ps | ||
| T48 | /workspace/coverage/default/40.prim_present_test.4241930524 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:01:42 PM PDT 24 | 10101040000 ps | ||
| T49 | /workspace/coverage/default/28.prim_present_test.3620981306 | Jul 03 05:00:22 PM PDT 24 | Jul 03 05:01:37 PM PDT 24 | 9549240000 ps | ||
| T50 | /workspace/coverage/default/44.prim_present_test.3891693966 | Jul 03 05:00:23 PM PDT 24 | Jul 03 05:01:46 PM PDT 24 | 12323120000 ps |
| Test location | /workspace/coverage/default/13.prim_present_test.4169853694 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14617740000 ps |
| CPU time | 57.02 seconds |
| Started | Jul 03 05:00:18 PM PDT 24 |
| Finished | Jul 03 05:02:09 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-df10fe2b-e92f-47ae-a616-3bba2d173886 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169853694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4169853694 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2864173846 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8738900000 ps |
| CPU time | 35.24 seconds |
| Started | Jul 03 05:00:19 PM PDT 24 |
| Finished | Jul 03 05:01:29 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-29bb68c2-fbf7-4cee-860d-5e9f83226c8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2864173846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2864173846 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3222992274 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5245200000 ps |
| CPU time | 18.43 seconds |
| Started | Jul 03 05:00:15 PM PDT 24 |
| Finished | Jul 03 05:00:50 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-1de8d21c-d88f-49b2-bf8d-404acd198273 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222992274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3222992274 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1205801641 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5221640000 ps |
| CPU time | 18.55 seconds |
| Started | Jul 03 05:00:21 PM PDT 24 |
| Finished | Jul 03 05:00:56 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-736e2df6-f0f5-4bea-8df5-2eae4b846eb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205801641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1205801641 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.566953103 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13452140000 ps |
| CPU time | 45.18 seconds |
| Started | Jul 03 05:00:19 PM PDT 24 |
| Finished | Jul 03 05:01:44 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-f7d8f066-44b5-4938-a746-264af4f3970b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566953103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.566953103 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3167269861 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6575720000 ps |
| CPU time | 27.37 seconds |
| Started | Jul 03 05:00:20 PM PDT 24 |
| Finished | Jul 03 05:01:14 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-fbdff61d-db44-44dc-b9d3-d524de13cf9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3167269861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3167269861 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3409215949 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3897940000 ps |
| CPU time | 14.04 seconds |
| Started | Jul 03 05:00:21 PM PDT 24 |
| Finished | Jul 03 05:00:47 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-0ab765b1-353c-4fac-b195-3b83647ea63a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409215949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3409215949 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.844892178 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7381100000 ps |
| CPU time | 23.46 seconds |
| Started | Jul 03 05:00:20 PM PDT 24 |
| Finished | Jul 03 05:01:04 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-646c7fe0-e1a0-428c-8561-c0433a9fa485 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844892178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.844892178 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2265504285 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7391020000 ps |
| CPU time | 26.04 seconds |
| Started | Jul 03 05:00:16 PM PDT 24 |
| Finished | Jul 03 05:01:06 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-506824a7-9466-4731-a0b7-ffd07b799201 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265504285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2265504285 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.252372338 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12967300000 ps |
| CPU time | 45.95 seconds |
| Started | Jul 03 05:00:21 PM PDT 24 |
| Finished | Jul 03 05:01:48 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-c2a67bb7-9f86-46fd-9166-eb2010fc0552 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252372338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.252372338 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1253572091 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14353000000 ps |
| CPU time | 45.92 seconds |
| Started | Jul 03 05:00:19 PM PDT 24 |
| Finished | Jul 03 05:01:45 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-25fb54ab-bee7-4158-8619-82b67cb9d33c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253572091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1253572091 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.4047526355 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4826080000 ps |
| CPU time | 15.92 seconds |
| Started | Jul 03 05:00:21 PM PDT 24 |
| Finished | Jul 03 05:00:51 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-a5df221d-d91d-4256-b8ee-742a42e26292 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047526355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.4047526355 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3243404859 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13157020000 ps |
| CPU time | 44.75 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:01:48 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-06891baf-e511-4c28-b742-7f8f3bdceeb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243404859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3243404859 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1672699976 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5360520000 ps |
| CPU time | 19.4 seconds |
| Started | Jul 03 05:00:20 PM PDT 24 |
| Finished | Jul 03 05:00:57 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-c28020de-66d8-493d-b53d-07d360be4c05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672699976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1672699976 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1398490485 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3254380000 ps |
| CPU time | 12.72 seconds |
| Started | Jul 03 05:00:17 PM PDT 24 |
| Finished | Jul 03 05:00:42 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-03c8f21e-49b5-4630-8789-a8cfc4d06a96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398490485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1398490485 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2940624266 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8638460000 ps |
| CPU time | 27.28 seconds |
| Started | Jul 03 05:00:20 PM PDT 24 |
| Finished | Jul 03 05:01:11 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-91016c54-2e40-4f9a-b7af-7fb9fd739e90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940624266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2940624266 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3191890452 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6813800000 ps |
| CPU time | 27.71 seconds |
| Started | Jul 03 05:00:20 PM PDT 24 |
| Finished | Jul 03 05:01:15 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-fd5df973-2869-4f58-bf8a-0dee07416ad5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191890452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3191890452 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2314418282 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5059820000 ps |
| CPU time | 19.42 seconds |
| Started | Jul 03 05:00:18 PM PDT 24 |
| Finished | Jul 03 05:00:56 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-6af546a0-6be9-45eb-9135-18c3eb81a9a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314418282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2314418282 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.968572017 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 14607200000 ps |
| CPU time | 48.86 seconds |
| Started | Jul 03 05:00:25 PM PDT 24 |
| Finished | Jul 03 05:01:57 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-01b2a0ab-f594-42b5-ae8a-cac1a2505e5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968572017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.968572017 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.712940859 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6492020000 ps |
| CPU time | 25.67 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:01:12 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-ea43bae8-f697-4f08-8be5-b71a0e508380 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712940859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.712940859 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3809162398 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6630280000 ps |
| CPU time | 24.47 seconds |
| Started | Jul 03 05:00:25 PM PDT 24 |
| Finished | Jul 03 05:01:11 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-c15ec693-7b6a-477d-be6f-1fa7bbe02fe3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809162398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3809162398 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3620981306 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9549240000 ps |
| CPU time | 39.33 seconds |
| Started | Jul 03 05:00:22 PM PDT 24 |
| Finished | Jul 03 05:01:37 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-5516b56b-e2aa-4011-bfac-4fe0b1c5420d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620981306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3620981306 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.125379867 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 15253860000 ps |
| CPU time | 50.9 seconds |
| Started | Jul 03 05:00:25 PM PDT 24 |
| Finished | Jul 03 05:02:01 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-eb6e2a6c-de6f-408b-abc9-e556df9543f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125379867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.125379867 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2880341685 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11943060000 ps |
| CPU time | 43.93 seconds |
| Started | Jul 03 05:00:18 PM PDT 24 |
| Finished | Jul 03 05:01:42 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-62197e1e-307d-4999-a2b2-f4c7ee2b8f51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880341685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2880341685 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2286026642 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13888000000 ps |
| CPU time | 43.21 seconds |
| Started | Jul 03 05:00:21 PM PDT 24 |
| Finished | Jul 03 05:01:43 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-8213e029-388b-42d4-a494-35f2c9c931f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286026642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2286026642 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.933866328 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8374340000 ps |
| CPU time | 27.52 seconds |
| Started | Jul 03 05:00:22 PM PDT 24 |
| Finished | Jul 03 05:01:14 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-13bc2655-ffc7-454c-9b33-abadf169b102 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933866328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.933866328 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3675063568 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9437640000 ps |
| CPU time | 30.87 seconds |
| Started | Jul 03 05:00:20 PM PDT 24 |
| Finished | Jul 03 05:01:18 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-1fdb377a-a400-406a-948d-5f948f52722c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3675063568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3675063568 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.113258708 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13499880000 ps |
| CPU time | 48.58 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:01:56 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-b9e523d0-06e4-4dfa-8194-d8d17e71348f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113258708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.113258708 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2263171103 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7320340000 ps |
| CPU time | 27.65 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:01:16 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-b0a61ede-e87b-4d13-bc89-9c039d6d97b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263171103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2263171103 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1939805648 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6587500000 ps |
| CPU time | 22.76 seconds |
| Started | Jul 03 05:00:19 PM PDT 24 |
| Finished | Jul 03 05:01:03 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-d57db053-6250-4fdc-89fe-68c188f5a858 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939805648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1939805648 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.463912142 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6070420000 ps |
| CPU time | 23.22 seconds |
| Started | Jul 03 05:00:20 PM PDT 24 |
| Finished | Jul 03 05:01:05 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-a706e5a2-0991-46c1-9276-c568265a3bf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=463912142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.463912142 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.805365704 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3543920000 ps |
| CPU time | 14.24 seconds |
| Started | Jul 03 05:00:21 PM PDT 24 |
| Finished | Jul 03 05:00:49 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-8dabeba7-45cb-4e02-865d-78b78640d437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805365704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.805365704 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.585604538 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4888700000 ps |
| CPU time | 20.16 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:01:01 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-082b4398-4021-4c94-b4c6-daa2815fd1db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585604538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.585604538 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.945785533 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7025220000 ps |
| CPU time | 29.51 seconds |
| Started | Jul 03 05:00:25 PM PDT 24 |
| Finished | Jul 03 05:01:23 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-4e01fb6d-e623-460a-af32-1aa10b4684b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945785533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.945785533 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4292351804 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8807100000 ps |
| CPU time | 35.09 seconds |
| Started | Jul 03 05:00:22 PM PDT 24 |
| Finished | Jul 03 05:01:31 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-ba563479-9e24-4aaf-b3f6-e4b02dd5b908 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292351804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4292351804 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4241930524 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10101040000 ps |
| CPU time | 40.51 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:01:42 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-0a2375fe-9d1c-4c84-9ea5-c26f995cd3d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241930524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4241930524 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3424809484 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8232360000 ps |
| CPU time | 33.26 seconds |
| Started | Jul 03 05:00:22 PM PDT 24 |
| Finished | Jul 03 05:01:26 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-1bde4ff9-e013-41cb-bb5f-c0777d18dae8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424809484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3424809484 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.522357479 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4922800000 ps |
| CPU time | 18.87 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:00:59 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-ea238ef6-3048-4510-a167-20fdd2cb7c9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=522357479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.522357479 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1181132208 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6392820000 ps |
| CPU time | 21.64 seconds |
| Started | Jul 03 05:00:24 PM PDT 24 |
| Finished | Jul 03 05:01:05 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-f109d5c5-5803-433b-b105-722c8d323cbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181132208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1181132208 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3891693966 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12323120000 ps |
| CPU time | 43.71 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:01:46 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ab1397ba-36ba-44d2-9be0-4211d00a6ca0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891693966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3891693966 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4170812881 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13188020000 ps |
| CPU time | 48.63 seconds |
| Started | Jul 03 05:00:25 PM PDT 24 |
| Finished | Jul 03 05:01:58 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-84ca522c-1622-490f-8e59-5259a431ce19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170812881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4170812881 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1765621943 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4464000000 ps |
| CPU time | 17.55 seconds |
| Started | Jul 03 05:00:23 PM PDT 24 |
| Finished | Jul 03 05:00:58 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-b12e4721-99f6-488c-8c2d-062b984674fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765621943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1765621943 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1271134616 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5649440000 ps |
| CPU time | 20.79 seconds |
| Started | Jul 03 05:00:25 PM PDT 24 |
| Finished | Jul 03 05:01:04 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-021acf76-855b-4c65-994e-fde3a0b49061 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271134616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1271134616 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3608371780 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 11398700000 ps |
| CPU time | 40.05 seconds |
| Started | Jul 03 05:00:25 PM PDT 24 |
| Finished | Jul 03 05:01:40 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-4f5d3ae0-08a6-4f3b-8b98-e749d5a0cd17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608371780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3608371780 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1202937936 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9193360000 ps |
| CPU time | 30.54 seconds |
| Started | Jul 03 05:00:22 PM PDT 24 |
| Finished | Jul 03 05:01:19 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-9096328e-3cf4-4411-981f-6adfc637f853 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202937936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1202937936 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1740381347 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 7138060000 ps |
| CPU time | 25.54 seconds |
| Started | Jul 03 05:00:19 PM PDT 24 |
| Finished | Jul 03 05:01:08 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-001387b3-4b0e-4d1c-8df1-5bf62fbea33d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740381347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1740381347 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3311254510 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8787260000 ps |
| CPU time | 31.84 seconds |
| Started | Jul 03 05:00:22 PM PDT 24 |
| Finished | Jul 03 05:01:23 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-f46213a1-f597-492a-aae2-0ea2401de926 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311254510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3311254510 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.800263877 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8453700000 ps |
| CPU time | 28.14 seconds |
| Started | Jul 03 05:00:19 PM PDT 24 |
| Finished | Jul 03 05:01:13 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-0cab3bd7-8288-4881-afee-618693e1a067 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800263877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.800263877 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2435540009 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10722280000 ps |
| CPU time | 36.29 seconds |
| Started | Jul 03 05:00:19 PM PDT 24 |
| Finished | Jul 03 05:01:28 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-acbce456-99aa-488d-8cb3-406de26f158c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435540009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2435540009 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.975386833 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11084360000 ps |
| CPU time | 35.11 seconds |
| Started | Jul 03 05:00:18 PM PDT 24 |
| Finished | Jul 03 05:01:24 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-3164f9f5-e32f-43de-af53-48b99dfff33f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975386833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.975386833 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |