| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/12.prim_present_test.107463891 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2712056616 |
| /workspace/coverage/default/1.prim_present_test.1948729981 |
| /workspace/coverage/default/10.prim_present_test.2263690689 |
| /workspace/coverage/default/11.prim_present_test.548775285 |
| /workspace/coverage/default/13.prim_present_test.1248773332 |
| /workspace/coverage/default/14.prim_present_test.3393494638 |
| /workspace/coverage/default/15.prim_present_test.2771482104 |
| /workspace/coverage/default/16.prim_present_test.281220600 |
| /workspace/coverage/default/17.prim_present_test.2235584129 |
| /workspace/coverage/default/18.prim_present_test.2628448769 |
| /workspace/coverage/default/19.prim_present_test.2796405769 |
| /workspace/coverage/default/2.prim_present_test.3975905235 |
| /workspace/coverage/default/20.prim_present_test.1943955007 |
| /workspace/coverage/default/21.prim_present_test.2154821298 |
| /workspace/coverage/default/22.prim_present_test.568471680 |
| /workspace/coverage/default/23.prim_present_test.2314156768 |
| /workspace/coverage/default/24.prim_present_test.496054970 |
| /workspace/coverage/default/25.prim_present_test.2351218624 |
| /workspace/coverage/default/26.prim_present_test.2528692611 |
| /workspace/coverage/default/27.prim_present_test.3718998113 |
| /workspace/coverage/default/28.prim_present_test.2644208543 |
| /workspace/coverage/default/29.prim_present_test.683376520 |
| /workspace/coverage/default/3.prim_present_test.2346547047 |
| /workspace/coverage/default/30.prim_present_test.3014438287 |
| /workspace/coverage/default/31.prim_present_test.1775141959 |
| /workspace/coverage/default/32.prim_present_test.3271395917 |
| /workspace/coverage/default/33.prim_present_test.34795700 |
| /workspace/coverage/default/34.prim_present_test.3184781242 |
| /workspace/coverage/default/35.prim_present_test.2264347484 |
| /workspace/coverage/default/36.prim_present_test.4114914009 |
| /workspace/coverage/default/37.prim_present_test.2477920835 |
| /workspace/coverage/default/38.prim_present_test.197291156 |
| /workspace/coverage/default/39.prim_present_test.2390581982 |
| /workspace/coverage/default/4.prim_present_test.2266523729 |
| /workspace/coverage/default/40.prim_present_test.1184658283 |
| /workspace/coverage/default/41.prim_present_test.1043410233 |
| /workspace/coverage/default/42.prim_present_test.601934140 |
| /workspace/coverage/default/43.prim_present_test.2505409640 |
| /workspace/coverage/default/44.prim_present_test.2910044498 |
| /workspace/coverage/default/45.prim_present_test.1885804187 |
| /workspace/coverage/default/46.prim_present_test.2772795424 |
| /workspace/coverage/default/47.prim_present_test.1105316473 |
| /workspace/coverage/default/48.prim_present_test.3987599845 |
| /workspace/coverage/default/49.prim_present_test.1873519868 |
| /workspace/coverage/default/5.prim_present_test.418907484 |
| /workspace/coverage/default/6.prim_present_test.3652886976 |
| /workspace/coverage/default/7.prim_present_test.1576215577 |
| /workspace/coverage/default/8.prim_present_test.1240587897 |
| /workspace/coverage/default/9.prim_present_test.1092788156 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_present_test.107463891 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:19:41 PM PDT 24 | 7260200000 ps | ||
| T2 | /workspace/coverage/default/15.prim_present_test.2771482104 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:19:55 PM PDT 24 | 10933080000 ps | ||
| T3 | /workspace/coverage/default/3.prim_present_test.2346547047 | Jul 04 04:18:35 PM PDT 24 | Jul 04 04:19:09 PM PDT 24 | 5775300000 ps | ||
| T4 | /workspace/coverage/default/22.prim_present_test.568471680 | Jul 04 04:18:48 PM PDT 24 | Jul 04 04:20:08 PM PDT 24 | 10893400000 ps | ||
| T5 | /workspace/coverage/default/27.prim_present_test.3718998113 | Jul 04 04:18:36 PM PDT 24 | Jul 04 04:19:48 PM PDT 24 | 11903380000 ps | ||
| T6 | /workspace/coverage/default/2.prim_present_test.3975905235 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:20:26 PM PDT 24 | 14024400000 ps | ||
| T7 | /workspace/coverage/default/47.prim_present_test.1105316473 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:20:00 PM PDT 24 | 11403040000 ps | ||
| T8 | /workspace/coverage/default/17.prim_present_test.2235584129 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:19:25 PM PDT 24 | 5315880000 ps | ||
| T9 | /workspace/coverage/default/4.prim_present_test.2266523729 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:19:13 PM PDT 24 | 4513600000 ps | ||
| T10 | /workspace/coverage/default/49.prim_present_test.1873519868 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:19:46 PM PDT 24 | 9311160000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.2390581982 | Jul 04 04:18:36 PM PDT 24 | Jul 04 04:19:53 PM PDT 24 | 12700700000 ps | ||
| T12 | /workspace/coverage/default/8.prim_present_test.1240587897 | Jul 04 04:18:33 PM PDT 24 | Jul 04 04:19:12 PM PDT 24 | 6416380000 ps | ||
| T13 | /workspace/coverage/default/10.prim_present_test.2263690689 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:19:55 PM PDT 24 | 9455620000 ps | ||
| T14 | /workspace/coverage/default/23.prim_present_test.2314156768 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:19:14 PM PDT 24 | 3840280000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.3652886976 | Jul 04 04:19:18 PM PDT 24 | Jul 04 04:20:53 PM PDT 24 | 13663560000 ps | ||
| T16 | /workspace/coverage/default/34.prim_present_test.3184781242 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:20:27 PM PDT 24 | 13419900000 ps | ||
| T17 | /workspace/coverage/default/14.prim_present_test.3393494638 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:19:50 PM PDT 24 | 8451220000 ps | ||
| T18 | /workspace/coverage/default/19.prim_present_test.2796405769 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:19:20 PM PDT 24 | 4576220000 ps | ||
| T19 | /workspace/coverage/default/24.prim_present_test.496054970 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:20:30 PM PDT 24 | 14728720000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.2477920835 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:19:51 PM PDT 24 | 9006120000 ps | ||
| T21 | /workspace/coverage/default/20.prim_present_test.1943955007 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:19:59 PM PDT 24 | 9629840000 ps | ||
| T22 | /workspace/coverage/default/7.prim_present_test.1576215577 | Jul 04 04:18:36 PM PDT 24 | Jul 04 04:19:59 PM PDT 24 | 13927060000 ps | ||
| T23 | /workspace/coverage/default/29.prim_present_test.683376520 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:19:24 PM PDT 24 | 5206140000 ps | ||
| T24 | /workspace/coverage/default/26.prim_present_test.2528692611 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:20:17 PM PDT 24 | 12431620000 ps | ||
| T25 | /workspace/coverage/default/36.prim_present_test.4114914009 | Jul 04 04:18:36 PM PDT 24 | Jul 04 04:19:24 PM PDT 24 | 7559040000 ps | ||
| T26 | /workspace/coverage/default/0.prim_present_test.2712056616 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:19:32 PM PDT 24 | 6279980000 ps | ||
| T27 | /workspace/coverage/default/35.prim_present_test.2264347484 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:20:14 PM PDT 24 | 11754580000 ps | ||
| T28 | /workspace/coverage/default/32.prim_present_test.3271395917 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:20:20 PM PDT 24 | 13786940000 ps | ||
| T29 | /workspace/coverage/default/33.prim_present_test.34795700 | Jul 04 04:18:35 PM PDT 24 | Jul 04 04:19:04 PM PDT 24 | 4860180000 ps | ||
| T30 | /workspace/coverage/default/44.prim_present_test.2910044498 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:19:15 PM PDT 24 | 4020700000 ps | ||
| T31 | /workspace/coverage/default/5.prim_present_test.418907484 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:20:34 PM PDT 24 | 14335640000 ps | ||
| T32 | /workspace/coverage/default/30.prim_present_test.3014438287 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:19:53 PM PDT 24 | 9401060000 ps | ||
| T33 | /workspace/coverage/default/16.prim_present_test.281220600 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:19:52 PM PDT 24 | 8942880000 ps | ||
| T34 | /workspace/coverage/default/41.prim_present_test.1043410233 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:19:57 PM PDT 24 | 9998120000 ps | ||
| T35 | /workspace/coverage/default/25.prim_present_test.2351218624 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:20:22 PM PDT 24 | 13526540000 ps | ||
| T36 | /workspace/coverage/default/18.prim_present_test.2628448769 | Jul 04 04:19:16 PM PDT 24 | Jul 04 04:20:46 PM PDT 24 | 13197940000 ps | ||
| T37 | /workspace/coverage/default/31.prim_present_test.1775141959 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:19:33 PM PDT 24 | 6433120000 ps | ||
| T38 | /workspace/coverage/default/42.prim_present_test.601934140 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:20:05 PM PDT 24 | 11295160000 ps | ||
| T39 | /workspace/coverage/default/45.prim_present_test.1885804187 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:20:23 PM PDT 24 | 13631320000 ps | ||
| T40 | /workspace/coverage/default/1.prim_present_test.1948729981 | Jul 04 04:18:48 PM PDT 24 | Jul 04 04:20:05 PM PDT 24 | 10330440000 ps | ||
| T41 | /workspace/coverage/default/46.prim_present_test.2772795424 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:20:33 PM PDT 24 | 14662380000 ps | ||
| T42 | /workspace/coverage/default/38.prim_present_test.197291156 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:20:11 PM PDT 24 | 11999480000 ps | ||
| T43 | /workspace/coverage/default/40.prim_present_test.1184658283 | Jul 04 04:18:47 PM PDT 24 | Jul 04 04:19:33 PM PDT 24 | 6937800000 ps | ||
| T44 | /workspace/coverage/default/11.prim_present_test.548775285 | Jul 04 04:18:45 PM PDT 24 | Jul 04 04:19:21 PM PDT 24 | 4532200000 ps | ||
| T45 | /workspace/coverage/default/48.prim_present_test.3987599845 | Jul 04 04:19:17 PM PDT 24 | Jul 04 04:20:03 PM PDT 24 | 6680500000 ps | ||
| T46 | /workspace/coverage/default/13.prim_present_test.1248773332 | Jul 04 04:18:35 PM PDT 24 | Jul 04 04:19:37 PM PDT 24 | 10798540000 ps | ||
| T47 | /workspace/coverage/default/43.prim_present_test.2505409640 | Jul 04 04:18:48 PM PDT 24 | Jul 04 04:19:43 PM PDT 24 | 7399080000 ps | ||
| T48 | /workspace/coverage/default/9.prim_present_test.1092788156 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:19:28 PM PDT 24 | 5455380000 ps | ||
| T49 | /workspace/coverage/default/21.prim_present_test.2154821298 | Jul 04 04:18:46 PM PDT 24 | Jul 04 04:20:15 PM PDT 24 | 11697540000 ps | ||
| T50 | /workspace/coverage/default/28.prim_present_test.2644208543 | Jul 04 04:18:35 PM PDT 24 | Jul 04 04:19:49 PM PDT 24 | 12223300000 ps |
| Test location | /workspace/coverage/default/12.prim_present_test.107463891 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7260200000 ps |
| CPU time | 28.7 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:19:41 PM PDT 24 |
| Peak memory | 144624 kb |
| Host | smart-4339ef1c-8c5f-4f5b-80db-29714dd08808 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107463891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.107463891 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2712056616 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6279980000 ps |
| CPU time | 24.51 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:19:32 PM PDT 24 |
| Peak memory | 143352 kb |
| Host | smart-b2670281-7461-4d3d-9e34-3ad64bc77715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712056616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2712056616 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1948729981 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10330440000 ps |
| CPU time | 39.89 seconds |
| Started | Jul 04 04:18:48 PM PDT 24 |
| Finished | Jul 04 04:20:05 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-8b7b938c-3253-4fee-b908-d36ee1b309b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948729981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1948729981 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2263690689 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9455620000 ps |
| CPU time | 36.38 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:19:55 PM PDT 24 |
| Peak memory | 143452 kb |
| Host | smart-294853af-1ece-4e1e-bc0c-d10775eb91cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263690689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2263690689 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.548775285 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4532200000 ps |
| CPU time | 18.65 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:19:21 PM PDT 24 |
| Peak memory | 144436 kb |
| Host | smart-f40f5973-86a1-4914-b38e-ab0c11f99f64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548775285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.548775285 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1248773332 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10798540000 ps |
| CPU time | 33.25 seconds |
| Started | Jul 04 04:18:35 PM PDT 24 |
| Finished | Jul 04 04:19:37 PM PDT 24 |
| Peak memory | 145356 kb |
| Host | smart-8c4b5704-e595-49fe-8275-e8ac1c39c4da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248773332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1248773332 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3393494638 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8451220000 ps |
| CPU time | 32.58 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:19:50 PM PDT 24 |
| Peak memory | 143008 kb |
| Host | smart-4fe71652-2f21-4b80-984d-7fd8146eeb0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393494638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3393494638 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2771482104 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10933080000 ps |
| CPU time | 35.82 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:19:55 PM PDT 24 |
| Peak memory | 143752 kb |
| Host | smart-af5d3d73-c4b0-4417-9beb-73cf270f4a56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2771482104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2771482104 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.281220600 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8942880000 ps |
| CPU time | 35.1 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:19:52 PM PDT 24 |
| Peak memory | 143388 kb |
| Host | smart-bb6710fa-eaf2-414c-a17f-3288aef6e9d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281220600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.281220600 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2235584129 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5315880000 ps |
| CPU time | 20.68 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:19:25 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-5f6b1e0f-ae77-445d-bf5e-f5b5cf1bef16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235584129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2235584129 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2628448769 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13197940000 ps |
| CPU time | 47.89 seconds |
| Started | Jul 04 04:19:16 PM PDT 24 |
| Finished | Jul 04 04:20:46 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-3cce8574-d82b-4ee7-af79-e9101aa8c08c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628448769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2628448769 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2796405769 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4576220000 ps |
| CPU time | 18.41 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:19:20 PM PDT 24 |
| Peak memory | 143552 kb |
| Host | smart-ab5b0728-35be-4828-9e8c-da97e3db0cdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796405769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2796405769 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3975905235 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14024400000 ps |
| CPU time | 52.92 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:20:26 PM PDT 24 |
| Peak memory | 144460 kb |
| Host | smart-cd84c1a7-42cd-4c09-bf83-ce1635776f41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975905235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3975905235 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1943955007 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9629840000 ps |
| CPU time | 37.41 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:19:59 PM PDT 24 |
| Peak memory | 144500 kb |
| Host | smart-d0014728-3b6e-4f76-8ffa-14ab6ba10ea7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943955007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1943955007 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2154821298 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11697540000 ps |
| CPU time | 45.95 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:20:15 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-4d9e751b-5572-495e-a3f1-b6e42ddae6e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154821298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2154821298 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.568471680 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10893400000 ps |
| CPU time | 41.27 seconds |
| Started | Jul 04 04:18:48 PM PDT 24 |
| Finished | Jul 04 04:20:08 PM PDT 24 |
| Peak memory | 144800 kb |
| Host | smart-2e9f2c9e-5ff3-424c-acfb-2eea0922efb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568471680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.568471680 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2314156768 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3840280000 ps |
| CPU time | 14.89 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:19:14 PM PDT 24 |
| Peak memory | 144836 kb |
| Host | smart-e2452969-d660-41d5-8c2c-468da75b9610 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314156768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2314156768 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.496054970 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14728720000 ps |
| CPU time | 55.38 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:20:30 PM PDT 24 |
| Peak memory | 144456 kb |
| Host | smart-501fcdac-0e92-47e7-9b2f-225eb39e2374 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496054970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.496054970 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2351218624 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13526540000 ps |
| CPU time | 51.05 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:20:22 PM PDT 24 |
| Peak memory | 143764 kb |
| Host | smart-8a296e39-4de4-4e61-a771-40ea7bd38476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351218624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2351218624 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2528692611 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12431620000 ps |
| CPU time | 47.58 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:20:17 PM PDT 24 |
| Peak memory | 144392 kb |
| Host | smart-24233ff1-2c61-4b6a-a6af-a44481aef518 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528692611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2528692611 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3718998113 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11903380000 ps |
| CPU time | 38.64 seconds |
| Started | Jul 04 04:18:36 PM PDT 24 |
| Finished | Jul 04 04:19:48 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-7a8fa445-c503-4338-84e6-b2682533a743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718998113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3718998113 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2644208543 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12223300000 ps |
| CPU time | 39.6 seconds |
| Started | Jul 04 04:18:35 PM PDT 24 |
| Finished | Jul 04 04:19:49 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-38fd527f-cad3-414d-b0c2-12d31b433ffa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644208543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2644208543 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.683376520 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5206140000 ps |
| CPU time | 19.88 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:19:24 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-e304d52a-deef-4d3d-81e4-af3da9107340 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683376520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.683376520 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2346547047 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5775300000 ps |
| CPU time | 18.27 seconds |
| Started | Jul 04 04:18:35 PM PDT 24 |
| Finished | Jul 04 04:19:09 PM PDT 24 |
| Peak memory | 145356 kb |
| Host | smart-35524a7d-2475-463f-b0c7-0daf9b022386 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346547047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2346547047 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3014438287 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9401060000 ps |
| CPU time | 34.8 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:19:53 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-33c9524b-5a29-4efa-b105-f4df540fc88e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014438287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3014438287 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1775141959 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6433120000 ps |
| CPU time | 24.6 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:19:33 PM PDT 24 |
| Peak memory | 144624 kb |
| Host | smart-cfc03b9f-8537-402a-b1a7-4ccf4b579ec8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775141959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1775141959 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3271395917 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13786940000 ps |
| CPU time | 49.92 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:20:20 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-da1d7fe1-cb28-418a-beaf-74bba6c6591a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271395917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3271395917 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.34795700 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4860180000 ps |
| CPU time | 15.72 seconds |
| Started | Jul 04 04:18:35 PM PDT 24 |
| Finished | Jul 04 04:19:04 PM PDT 24 |
| Peak memory | 145372 kb |
| Host | smart-d079c998-568e-4222-a51d-0401c985a66e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34795700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.34795700 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3184781242 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13419900000 ps |
| CPU time | 51.97 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:20:27 PM PDT 24 |
| Peak memory | 143124 kb |
| Host | smart-146e6173-0181-45a1-86d4-1812044a1ddb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3184781242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3184781242 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2264347484 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11754580000 ps |
| CPU time | 45.91 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:20:14 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-755b0636-df49-42db-9a43-07894465db99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264347484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2264347484 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4114914009 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7559040000 ps |
| CPU time | 25.01 seconds |
| Started | Jul 04 04:18:36 PM PDT 24 |
| Finished | Jul 04 04:19:24 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-1998e264-ec3c-4ace-bfc6-89c900e2aec5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114914009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4114914009 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2477920835 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9006120000 ps |
| CPU time | 34.7 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:19:51 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-2983a6a3-efcc-4e6a-a2a6-69a7371b455a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2477920835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2477920835 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.197291156 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11999480000 ps |
| CPU time | 45.11 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:20:11 PM PDT 24 |
| Peak memory | 144484 kb |
| Host | smart-b9d114b6-94f6-4e66-8f9b-8e22012c6418 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=197291156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.197291156 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2390581982 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12700700000 ps |
| CPU time | 41.26 seconds |
| Started | Jul 04 04:18:36 PM PDT 24 |
| Finished | Jul 04 04:19:53 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-51cd0197-94cc-4d91-9602-645f8323b31f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390581982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2390581982 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2266523729 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4513600000 ps |
| CPU time | 14.3 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:19:13 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-80dd0395-2eba-41ca-98f8-cb21648d8943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266523729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2266523729 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1184658283 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6937800000 ps |
| CPU time | 24.12 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:19:33 PM PDT 24 |
| Peak memory | 143340 kb |
| Host | smart-62ab1c2a-b06f-4a11-8ddf-1d9b12e90713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184658283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1184658283 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1043410233 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9998120000 ps |
| CPU time | 37.12 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:19:57 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-1a167a33-fcd1-4e8a-ac6b-85e49aee724b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1043410233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1043410233 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.601934140 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11295160000 ps |
| CPU time | 42.29 seconds |
| Started | Jul 04 04:18:45 PM PDT 24 |
| Finished | Jul 04 04:20:05 PM PDT 24 |
| Peak memory | 143404 kb |
| Host | smart-6d832f84-5b9e-4361-b7db-762836b73397 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601934140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.601934140 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2505409640 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7399080000 ps |
| CPU time | 28.57 seconds |
| Started | Jul 04 04:18:48 PM PDT 24 |
| Finished | Jul 04 04:19:43 PM PDT 24 |
| Peak memory | 144764 kb |
| Host | smart-6b714ae7-5e8b-4936-ab1b-8edf9220e920 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505409640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2505409640 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2910044498 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4020700000 ps |
| CPU time | 15.57 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:19:15 PM PDT 24 |
| Peak memory | 144608 kb |
| Host | smart-9126022a-9e21-4ce5-a58d-3cb8e5acdcf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910044498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2910044498 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1885804187 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13631320000 ps |
| CPU time | 51.13 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:20:23 PM PDT 24 |
| Peak memory | 143456 kb |
| Host | smart-ee66b0c5-782d-470d-8105-51bc195c7e76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885804187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1885804187 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2772795424 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14662380000 ps |
| CPU time | 55.73 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:20:33 PM PDT 24 |
| Peak memory | 143208 kb |
| Host | smart-cc8c57ae-fd24-45ad-8c13-1afcd2b3c191 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772795424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2772795424 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1105316473 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11403040000 ps |
| CPU time | 38.51 seconds |
| Started | Jul 04 04:18:47 PM PDT 24 |
| Finished | Jul 04 04:20:00 PM PDT 24 |
| Peak memory | 143392 kb |
| Host | smart-ddd9a2c6-f0b9-45d9-a79b-d3fa677e568c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1105316473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1105316473 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3987599845 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6680500000 ps |
| CPU time | 24.73 seconds |
| Started | Jul 04 04:19:17 PM PDT 24 |
| Finished | Jul 04 04:20:03 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-835ab0f7-b00f-436a-8dda-19cc2e24a2a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987599845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3987599845 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1873519868 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9311160000 ps |
| CPU time | 32.11 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:19:46 PM PDT 24 |
| Peak memory | 143408 kb |
| Host | smart-788c0817-5307-4d2b-9e1e-24a6856de031 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873519868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1873519868 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.418907484 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14335640000 ps |
| CPU time | 56.36 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:20:34 PM PDT 24 |
| Peak memory | 144500 kb |
| Host | smart-a209870c-83e3-43ca-a1b6-f786481d42b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418907484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.418907484 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3652886976 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13663560000 ps |
| CPU time | 50.45 seconds |
| Started | Jul 04 04:19:18 PM PDT 24 |
| Finished | Jul 04 04:20:53 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-1d0fe463-ba22-4384-89f4-52ad8b0174f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652886976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3652886976 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1576215577 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13927060000 ps |
| CPU time | 44.5 seconds |
| Started | Jul 04 04:18:36 PM PDT 24 |
| Finished | Jul 04 04:19:59 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-ad94ebf4-a0d7-4ebe-9bfb-813382d953b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576215577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1576215577 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1240587897 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6416380000 ps |
| CPU time | 20.49 seconds |
| Started | Jul 04 04:18:33 PM PDT 24 |
| Finished | Jul 04 04:19:12 PM PDT 24 |
| Peak memory | 145368 kb |
| Host | smart-31162711-07e0-44db-8f85-2c51c19b559a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240587897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1240587897 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1092788156 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5455380000 ps |
| CPU time | 21.88 seconds |
| Started | Jul 04 04:18:46 PM PDT 24 |
| Finished | Jul 04 04:19:28 PM PDT 24 |
| Peak memory | 144336 kb |
| Host | smart-4c4d9606-98bc-437b-a94d-57e4db9f182c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092788156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1092788156 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |