| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3707485015 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.653217494 |
| /workspace/coverage/default/10.prim_present_test.2173003167 |
| /workspace/coverage/default/11.prim_present_test.3974389217 |
| /workspace/coverage/default/12.prim_present_test.3738850320 |
| /workspace/coverage/default/13.prim_present_test.2480327301 |
| /workspace/coverage/default/14.prim_present_test.2599681310 |
| /workspace/coverage/default/15.prim_present_test.2636912027 |
| /workspace/coverage/default/16.prim_present_test.2958919678 |
| /workspace/coverage/default/17.prim_present_test.2940525176 |
| /workspace/coverage/default/18.prim_present_test.2195147608 |
| /workspace/coverage/default/19.prim_present_test.3313432515 |
| /workspace/coverage/default/2.prim_present_test.1756788043 |
| /workspace/coverage/default/20.prim_present_test.1680890178 |
| /workspace/coverage/default/21.prim_present_test.1409962265 |
| /workspace/coverage/default/22.prim_present_test.2870662985 |
| /workspace/coverage/default/23.prim_present_test.2814416939 |
| /workspace/coverage/default/24.prim_present_test.1261169506 |
| /workspace/coverage/default/25.prim_present_test.1367294653 |
| /workspace/coverage/default/26.prim_present_test.1539196561 |
| /workspace/coverage/default/27.prim_present_test.522330829 |
| /workspace/coverage/default/28.prim_present_test.772236020 |
| /workspace/coverage/default/29.prim_present_test.3206209870 |
| /workspace/coverage/default/3.prim_present_test.83559923 |
| /workspace/coverage/default/30.prim_present_test.201295780 |
| /workspace/coverage/default/31.prim_present_test.3009319130 |
| /workspace/coverage/default/32.prim_present_test.707532145 |
| /workspace/coverage/default/33.prim_present_test.2768487928 |
| /workspace/coverage/default/34.prim_present_test.889154420 |
| /workspace/coverage/default/35.prim_present_test.2126128028 |
| /workspace/coverage/default/36.prim_present_test.98948565 |
| /workspace/coverage/default/37.prim_present_test.2475983998 |
| /workspace/coverage/default/38.prim_present_test.1322293068 |
| /workspace/coverage/default/39.prim_present_test.4110719625 |
| /workspace/coverage/default/4.prim_present_test.3191515255 |
| /workspace/coverage/default/40.prim_present_test.879026303 |
| /workspace/coverage/default/41.prim_present_test.2585188652 |
| /workspace/coverage/default/42.prim_present_test.4231613967 |
| /workspace/coverage/default/43.prim_present_test.3326144739 |
| /workspace/coverage/default/44.prim_present_test.2942692125 |
| /workspace/coverage/default/45.prim_present_test.2047045360 |
| /workspace/coverage/default/46.prim_present_test.3847552899 |
| /workspace/coverage/default/47.prim_present_test.2000245189 |
| /workspace/coverage/default/48.prim_present_test.2755304789 |
| /workspace/coverage/default/49.prim_present_test.3909937455 |
| /workspace/coverage/default/5.prim_present_test.462093924 |
| /workspace/coverage/default/6.prim_present_test.452879254 |
| /workspace/coverage/default/7.prim_present_test.1772488800 |
| /workspace/coverage/default/8.prim_present_test.68217536 |
| /workspace/coverage/default/9.prim_present_test.1785747961 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/14.prim_present_test.2599681310 | Jul 05 04:34:28 PM PDT 24 | Jul 05 04:35:37 PM PDT 24 | 11174260000 ps | ||
| T2 | /workspace/coverage/default/42.prim_present_test.4231613967 | Jul 05 04:34:37 PM PDT 24 | Jul 05 04:35:43 PM PDT 24 | 8251580000 ps | ||
| T3 | /workspace/coverage/default/37.prim_present_test.2475983998 | Jul 05 04:34:33 PM PDT 24 | Jul 05 04:35:49 PM PDT 24 | 9058820000 ps | ||
| T4 | /workspace/coverage/default/6.prim_present_test.452879254 | Jul 05 04:34:13 PM PDT 24 | Jul 05 04:36:14 PM PDT 24 | 14866980000 ps | ||
| T5 | /workspace/coverage/default/46.prim_present_test.3847552899 | Jul 05 04:34:34 PM PDT 24 | Jul 05 04:35:01 PM PDT 24 | 3787580000 ps | ||
| T6 | /workspace/coverage/default/31.prim_present_test.3009319130 | Jul 05 04:34:34 PM PDT 24 | Jul 05 04:35:22 PM PDT 24 | 7838040000 ps | ||
| T7 | /workspace/coverage/default/7.prim_present_test.1772488800 | Jul 05 04:34:32 PM PDT 24 | Jul 05 04:35:02 PM PDT 24 | 3753480000 ps | ||
| T8 | /workspace/coverage/default/34.prim_present_test.889154420 | Jul 05 04:34:28 PM PDT 24 | Jul 05 04:35:49 PM PDT 24 | 10612540000 ps | ||
| T9 | /workspace/coverage/default/3.prim_present_test.83559923 | Jul 05 04:34:33 PM PDT 24 | Jul 05 04:34:59 PM PDT 24 | 4082080000 ps | ||
| T10 | /workspace/coverage/default/0.prim_present_test.3707485015 | Jul 05 04:34:27 PM PDT 24 | Jul 05 04:35:15 PM PDT 24 | 7082260000 ps | ||
| T11 | /workspace/coverage/default/35.prim_present_test.2126128028 | Jul 05 04:34:32 PM PDT 24 | Jul 05 04:36:07 PM PDT 24 | 12547560000 ps | ||
| T12 | /workspace/coverage/default/33.prim_present_test.2768487928 | Jul 05 04:34:16 PM PDT 24 | Jul 05 04:35:12 PM PDT 24 | 6878280000 ps | ||
| T13 | /workspace/coverage/default/47.prim_present_test.2000245189 | Jul 05 04:34:38 PM PDT 24 | Jul 05 04:35:21 PM PDT 24 | 5620920000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.2585188652 | Jul 05 04:34:14 PM PDT 24 | Jul 05 04:34:48 PM PDT 24 | 4032480000 ps | ||
| T15 | /workspace/coverage/default/36.prim_present_test.98948565 | Jul 05 04:34:26 PM PDT 24 | Jul 05 04:35:41 PM PDT 24 | 11478060000 ps | ||
| T16 | /workspace/coverage/default/21.prim_present_test.1409962265 | Jul 05 04:34:23 PM PDT 24 | Jul 05 04:36:06 PM PDT 24 | 13401920000 ps | ||
| T17 | /workspace/coverage/default/23.prim_present_test.2814416939 | Jul 05 04:34:32 PM PDT 24 | Jul 05 04:35:45 PM PDT 24 | 12122860000 ps | ||
| T18 | /workspace/coverage/default/5.prim_present_test.462093924 | Jul 05 04:34:13 PM PDT 24 | Jul 05 04:35:35 PM PDT 24 | 13615820000 ps | ||
| T19 | /workspace/coverage/default/17.prim_present_test.2940525176 | Jul 05 04:34:15 PM PDT 24 | Jul 05 04:35:49 PM PDT 24 | 12351020000 ps | ||
| T20 | /workspace/coverage/default/8.prim_present_test.68217536 | Jul 05 04:34:38 PM PDT 24 | Jul 05 04:36:01 PM PDT 24 | 12427280000 ps | ||
| T21 | /workspace/coverage/default/22.prim_present_test.2870662985 | Jul 05 04:34:14 PM PDT 24 | Jul 05 04:35:16 PM PDT 24 | 7500760000 ps | ||
| T22 | /workspace/coverage/default/25.prim_present_test.1367294653 | Jul 05 04:34:18 PM PDT 24 | Jul 05 04:35:25 PM PDT 24 | 8345200000 ps | ||
| T23 | /workspace/coverage/default/32.prim_present_test.707532145 | Jul 05 04:34:13 PM PDT 24 | Jul 05 04:35:49 PM PDT 24 | 11173020000 ps | ||
| T24 | /workspace/coverage/default/44.prim_present_test.2942692125 | Jul 05 04:34:40 PM PDT 24 | Jul 05 04:35:21 PM PDT 24 | 5912320000 ps | ||
| T25 | /workspace/coverage/default/10.prim_present_test.2173003167 | Jul 05 04:34:34 PM PDT 24 | Jul 05 04:35:05 PM PDT 24 | 3931420000 ps | ||
| T26 | /workspace/coverage/default/29.prim_present_test.3206209870 | Jul 05 04:34:13 PM PDT 24 | Jul 05 04:35:08 PM PDT 24 | 7641500000 ps | ||
| T27 | /workspace/coverage/default/43.prim_present_test.3326144739 | Jul 05 04:34:12 PM PDT 24 | Jul 05 04:35:43 PM PDT 24 | 10840080000 ps | ||
| T28 | /workspace/coverage/default/45.prim_present_test.2047045360 | Jul 05 04:34:31 PM PDT 24 | Jul 05 04:35:44 PM PDT 24 | 12556240000 ps | ||
| T29 | /workspace/coverage/default/20.prim_present_test.1680890178 | Jul 05 04:34:30 PM PDT 24 | Jul 05 04:36:04 PM PDT 24 | 13575520000 ps | ||
| T30 | /workspace/coverage/default/27.prim_present_test.522330829 | Jul 05 04:34:28 PM PDT 24 | Jul 05 04:36:12 PM PDT 24 | 13733000000 ps | ||
| T31 | /workspace/coverage/default/38.prim_present_test.1322293068 | Jul 05 04:34:14 PM PDT 24 | Jul 05 04:35:56 PM PDT 24 | 13427960000 ps | ||
| T32 | /workspace/coverage/default/30.prim_present_test.201295780 | Jul 05 04:34:18 PM PDT 24 | Jul 05 04:36:05 PM PDT 24 | 13116100000 ps | ||
| T33 | /workspace/coverage/default/1.prim_present_test.653217494 | Jul 05 04:34:34 PM PDT 24 | Jul 05 04:35:57 PM PDT 24 | 10981440000 ps | ||
| T34 | /workspace/coverage/default/18.prim_present_test.2195147608 | Jul 05 04:34:37 PM PDT 24 | Jul 05 04:35:35 PM PDT 24 | 6971280000 ps | ||
| T35 | /workspace/coverage/default/4.prim_present_test.3191515255 | Jul 05 04:34:14 PM PDT 24 | Jul 05 04:34:58 PM PDT 24 | 6421340000 ps | ||
| T36 | /workspace/coverage/default/15.prim_present_test.2636912027 | Jul 05 04:34:35 PM PDT 24 | Jul 05 04:35:38 PM PDT 24 | 8356360000 ps | ||
| T37 | /workspace/coverage/default/19.prim_present_test.3313432515 | Jul 05 04:34:12 PM PDT 24 | Jul 05 04:35:50 PM PDT 24 | 14031220000 ps | ||
| T38 | /workspace/coverage/default/16.prim_present_test.2958919678 | Jul 05 04:34:37 PM PDT 24 | Jul 05 04:36:00 PM PDT 24 | 10502800000 ps | ||
| T39 | /workspace/coverage/default/24.prim_present_test.1261169506 | Jul 05 04:34:32 PM PDT 24 | Jul 05 04:35:37 PM PDT 24 | 7934760000 ps | ||
| T40 | /workspace/coverage/default/49.prim_present_test.3909937455 | Jul 05 04:34:28 PM PDT 24 | Jul 05 04:35:23 PM PDT 24 | 6999800000 ps | ||
| T41 | /workspace/coverage/default/12.prim_present_test.3738850320 | Jul 05 04:34:33 PM PDT 24 | Jul 05 04:36:23 PM PDT 24 | 14727480000 ps | ||
| T42 | /workspace/coverage/default/11.prim_present_test.3974389217 | Jul 05 04:34:26 PM PDT 24 | Jul 05 04:35:08 PM PDT 24 | 5281160000 ps | ||
| T43 | /workspace/coverage/default/13.prim_present_test.2480327301 | Jul 05 04:34:12 PM PDT 24 | Jul 05 04:35:04 PM PDT 24 | 7231680000 ps | ||
| T44 | /workspace/coverage/default/2.prim_present_test.1756788043 | Jul 05 04:34:15 PM PDT 24 | Jul 05 04:36:15 PM PDT 24 | 15035620000 ps | ||
| T45 | /workspace/coverage/default/39.prim_present_test.4110719625 | Jul 05 04:34:27 PM PDT 24 | Jul 05 04:35:47 PM PDT 24 | 11628100000 ps | ||
| T46 | /workspace/coverage/default/40.prim_present_test.879026303 | Jul 05 04:34:34 PM PDT 24 | Jul 05 04:35:55 PM PDT 24 | 11977160000 ps | ||
| T47 | /workspace/coverage/default/26.prim_present_test.1539196561 | Jul 05 04:34:24 PM PDT 24 | Jul 05 04:35:01 PM PDT 24 | 4643800000 ps | ||
| T48 | /workspace/coverage/default/9.prim_present_test.1785747961 | Jul 05 04:34:33 PM PDT 24 | Jul 05 04:35:28 PM PDT 24 | 7604920000 ps | ||
| T49 | /workspace/coverage/default/48.prim_present_test.2755304789 | Jul 05 04:34:33 PM PDT 24 | Jul 05 04:35:51 PM PDT 24 | 11937480000 ps | ||
| T50 | /workspace/coverage/default/28.prim_present_test.772236020 | Jul 05 04:34:35 PM PDT 24 | Jul 05 04:35:07 PM PDT 24 | 5597980000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3707485015 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7082260000 ps |
| CPU time | 25.05 seconds |
| Started | Jul 05 04:34:27 PM PDT 24 |
| Finished | Jul 05 04:35:15 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-3371bd92-2faf-415b-8362-16271e4f1f91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707485015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3707485015 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.653217494 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10981440000 ps |
| CPU time | 43.06 seconds |
| Started | Jul 05 04:34:34 PM PDT 24 |
| Finished | Jul 05 04:35:57 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-fcb7dc51-c664-48d9-a73b-8d259e1473d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653217494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.653217494 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2173003167 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3931420000 ps |
| CPU time | 16.01 seconds |
| Started | Jul 05 04:34:34 PM PDT 24 |
| Finished | Jul 05 04:35:05 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-50e736d6-491a-4677-9c8a-94eabbf96b8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173003167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2173003167 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3974389217 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5281160000 ps |
| CPU time | 21.44 seconds |
| Started | Jul 05 04:34:26 PM PDT 24 |
| Finished | Jul 05 04:35:08 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-87a56964-6a23-4b29-b4fb-19a15bb0636f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974389217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3974389217 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3738850320 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14727480000 ps |
| CPU time | 56.11 seconds |
| Started | Jul 05 04:34:33 PM PDT 24 |
| Finished | Jul 05 04:36:23 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-2be810c4-9759-456e-8f74-08b71b91f191 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738850320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3738850320 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2480327301 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7231680000 ps |
| CPU time | 24.7 seconds |
| Started | Jul 05 04:34:12 PM PDT 24 |
| Finished | Jul 05 04:35:04 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-aed22886-4963-47b6-9873-044814e6087f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480327301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2480327301 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2599681310 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11174260000 ps |
| CPU time | 36.33 seconds |
| Started | Jul 05 04:34:28 PM PDT 24 |
| Finished | Jul 05 04:35:37 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-812da246-2941-47e9-afae-f0271049bc78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599681310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2599681310 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2636912027 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8356360000 ps |
| CPU time | 32.72 seconds |
| Started | Jul 05 04:34:35 PM PDT 24 |
| Finished | Jul 05 04:35:38 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-46338f82-b7c0-4494-b1fb-20070a3550c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636912027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2636912027 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2958919678 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10502800000 ps |
| CPU time | 41.64 seconds |
| Started | Jul 05 04:34:37 PM PDT 24 |
| Finished | Jul 05 04:36:00 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-64e2fe6e-ed42-4b36-a0d6-313098b0e31c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958919678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2958919678 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2940525176 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12351020000 ps |
| CPU time | 46.55 seconds |
| Started | Jul 05 04:34:15 PM PDT 24 |
| Finished | Jul 05 04:35:49 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c1cc9ce6-45bb-4643-b375-f9f46902d693 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940525176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2940525176 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2195147608 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6971280000 ps |
| CPU time | 29.15 seconds |
| Started | Jul 05 04:34:37 PM PDT 24 |
| Finished | Jul 05 04:35:35 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-6c9b037a-3f6b-409b-a68e-e91ce7f784fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195147608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2195147608 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3313432515 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 14031220000 ps |
| CPU time | 48.51 seconds |
| Started | Jul 05 04:34:12 PM PDT 24 |
| Finished | Jul 05 04:35:50 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-f2097c8e-876b-4066-ae96-50c01a297787 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313432515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3313432515 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1756788043 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15035620000 ps |
| CPU time | 57.61 seconds |
| Started | Jul 05 04:34:15 PM PDT 24 |
| Finished | Jul 05 04:36:15 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-3e86ac78-4488-4090-a36b-34eb5f38dc4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756788043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1756788043 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1680890178 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13575520000 ps |
| CPU time | 48.99 seconds |
| Started | Jul 05 04:34:30 PM PDT 24 |
| Finished | Jul 05 04:36:04 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-b888beae-f786-4746-87d1-dd7a025039f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680890178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1680890178 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1409962265 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13401920000 ps |
| CPU time | 52.8 seconds |
| Started | Jul 05 04:34:23 PM PDT 24 |
| Finished | Jul 05 04:36:06 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-f595dee3-3961-49ef-9a51-39b3ac83773c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409962265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1409962265 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2870662985 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7500760000 ps |
| CPU time | 29.74 seconds |
| Started | Jul 05 04:34:14 PM PDT 24 |
| Finished | Jul 05 04:35:16 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-d3460aa8-eeda-4701-92bd-ef5cdc111ef1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870662985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2870662985 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2814416939 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12122860000 ps |
| CPU time | 39.45 seconds |
| Started | Jul 05 04:34:32 PM PDT 24 |
| Finished | Jul 05 04:35:45 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-b26c190e-485c-4e96-b608-a4f28bfc2866 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814416939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2814416939 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1261169506 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7934760000 ps |
| CPU time | 32.68 seconds |
| Started | Jul 05 04:34:32 PM PDT 24 |
| Finished | Jul 05 04:35:37 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-9d76d5ab-9ada-4803-ab03-1d868da8189f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261169506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1261169506 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1367294653 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8345200000 ps |
| CPU time | 32.31 seconds |
| Started | Jul 05 04:34:18 PM PDT 24 |
| Finished | Jul 05 04:35:25 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-04e149f4-6032-4d44-bf93-216dbe668a21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367294653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1367294653 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1539196561 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4643800000 ps |
| CPU time | 18.37 seconds |
| Started | Jul 05 04:34:24 PM PDT 24 |
| Finished | Jul 05 04:35:01 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-6bdd0516-07ef-4b68-85c0-28e32ed45a45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539196561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1539196561 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.522330829 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13733000000 ps |
| CPU time | 52.84 seconds |
| Started | Jul 05 04:34:28 PM PDT 24 |
| Finished | Jul 05 04:36:12 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-626356d5-085a-4d9a-8e86-11dde24afb4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=522330829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.522330829 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.772236020 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5597980000 ps |
| CPU time | 17.15 seconds |
| Started | Jul 05 04:34:35 PM PDT 24 |
| Finished | Jul 05 04:35:07 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-e025ef6e-4a05-4567-9020-739e9db02b3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772236020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.772236020 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3206209870 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7641500000 ps |
| CPU time | 26.53 seconds |
| Started | Jul 05 04:34:13 PM PDT 24 |
| Finished | Jul 05 04:35:08 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-97f5b025-7a56-4889-92f3-3df12bb70514 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206209870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3206209870 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.83559923 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4082080000 ps |
| CPU time | 13.83 seconds |
| Started | Jul 05 04:34:33 PM PDT 24 |
| Finished | Jul 05 04:34:59 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-8efa9d92-7618-40c0-9c84-77a658339d09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83559923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.83559923 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.201295780 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13116100000 ps |
| CPU time | 53.08 seconds |
| Started | Jul 05 04:34:18 PM PDT 24 |
| Finished | Jul 05 04:36:05 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-db8af0df-2282-430f-9e42-3f713f92fde0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201295780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.201295780 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3009319130 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7838040000 ps |
| CPU time | 25.16 seconds |
| Started | Jul 05 04:34:34 PM PDT 24 |
| Finished | Jul 05 04:35:22 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-a5a26183-80d1-40e4-9d9c-69284341f94c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009319130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3009319130 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.707532145 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11173020000 ps |
| CPU time | 45.63 seconds |
| Started | Jul 05 04:34:13 PM PDT 24 |
| Finished | Jul 05 04:35:49 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-2fe1714f-a2dd-4272-9e61-3e0cea157c30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707532145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.707532145 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2768487928 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6878280000 ps |
| CPU time | 26.79 seconds |
| Started | Jul 05 04:34:16 PM PDT 24 |
| Finished | Jul 05 04:35:12 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-eb9a3093-e331-46b4-a8ad-fbf12d1c0d53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768487928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2768487928 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.889154420 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10612540000 ps |
| CPU time | 41.06 seconds |
| Started | Jul 05 04:34:28 PM PDT 24 |
| Finished | Jul 05 04:35:49 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-32da8ede-e8e1-47c1-ba9e-e43c05f98ce6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889154420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.889154420 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2126128028 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12547560000 ps |
| CPU time | 49.12 seconds |
| Started | Jul 05 04:34:32 PM PDT 24 |
| Finished | Jul 05 04:36:07 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-7808bdcb-ea57-4b7a-92cd-6d7c5a89aafd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126128028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2126128028 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.98948565 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11478060000 ps |
| CPU time | 38.84 seconds |
| Started | Jul 05 04:34:26 PM PDT 24 |
| Finished | Jul 05 04:35:41 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-487c4904-0d52-4b3a-8116-c8a0d51106cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98948565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.98948565 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2475983998 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9058820000 ps |
| CPU time | 34.53 seconds |
| Started | Jul 05 04:34:33 PM PDT 24 |
| Finished | Jul 05 04:35:49 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-8f4711e1-4ba2-466c-a171-5fbc573c52c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475983998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2475983998 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1322293068 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13427960000 ps |
| CPU time | 49.91 seconds |
| Started | Jul 05 04:34:14 PM PDT 24 |
| Finished | Jul 05 04:35:56 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-43d51157-7931-4ed6-8394-97a9ca0f3018 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322293068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1322293068 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.4110719625 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11628100000 ps |
| CPU time | 42.06 seconds |
| Started | Jul 05 04:34:27 PM PDT 24 |
| Finished | Jul 05 04:35:47 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-ed769368-35e0-4d9b-a5ac-b02287535e1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110719625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4110719625 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3191515255 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6421340000 ps |
| CPU time | 20.71 seconds |
| Started | Jul 05 04:34:14 PM PDT 24 |
| Finished | Jul 05 04:34:58 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-3815d057-e11f-4bf9-af74-10d207b7c445 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191515255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3191515255 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.879026303 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11977160000 ps |
| CPU time | 43.24 seconds |
| Started | Jul 05 04:34:34 PM PDT 24 |
| Finished | Jul 05 04:35:55 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-a37de2b9-2cb3-4e88-b809-24a6ea92ea9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879026303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.879026303 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2585188652 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4032480000 ps |
| CPU time | 14.9 seconds |
| Started | Jul 05 04:34:14 PM PDT 24 |
| Finished | Jul 05 04:34:48 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-b979063e-046f-4f09-9744-02ea029d392f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585188652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2585188652 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4231613967 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8251580000 ps |
| CPU time | 33.18 seconds |
| Started | Jul 05 04:34:37 PM PDT 24 |
| Finished | Jul 05 04:35:43 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-ed5be43e-cffe-46c3-85db-7d18ec75865c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231613967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4231613967 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3326144739 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10840080000 ps |
| CPU time | 42.39 seconds |
| Started | Jul 05 04:34:12 PM PDT 24 |
| Finished | Jul 05 04:35:43 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-600123b4-7da9-44a0-bc43-26c266f61d41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326144739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3326144739 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2942692125 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5912320000 ps |
| CPU time | 21.33 seconds |
| Started | Jul 05 04:34:40 PM PDT 24 |
| Finished | Jul 05 04:35:21 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-00a0827c-6300-4ad9-a489-784b0f711656 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942692125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2942692125 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2047045360 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12556240000 ps |
| CPU time | 39.27 seconds |
| Started | Jul 05 04:34:31 PM PDT 24 |
| Finished | Jul 05 04:35:44 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-841bc718-3845-4f4e-bcf0-f9e6822923f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047045360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2047045360 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3847552899 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3787580000 ps |
| CPU time | 13.74 seconds |
| Started | Jul 05 04:34:34 PM PDT 24 |
| Finished | Jul 05 04:35:01 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-65cb99b5-986d-495e-a52a-d7a2087b6105 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3847552899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3847552899 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2000245189 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5620920000 ps |
| CPU time | 22.45 seconds |
| Started | Jul 05 04:34:38 PM PDT 24 |
| Finished | Jul 05 04:35:21 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-6027df06-e37a-4f26-a5b0-629a30cb2526 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000245189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2000245189 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2755304789 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11937480000 ps |
| CPU time | 41.31 seconds |
| Started | Jul 05 04:34:33 PM PDT 24 |
| Finished | Jul 05 04:35:51 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-a820bd62-029c-41f3-aea4-1af275fadb33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755304789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2755304789 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3909937455 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6999800000 ps |
| CPU time | 27.61 seconds |
| Started | Jul 05 04:34:28 PM PDT 24 |
| Finished | Jul 05 04:35:23 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-835ada73-364f-4163-8d58-d5649664ea61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909937455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3909937455 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.462093924 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13615820000 ps |
| CPU time | 40.78 seconds |
| Started | Jul 05 04:34:13 PM PDT 24 |
| Finished | Jul 05 04:35:35 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-3a4c580e-1af7-4c3f-a050-9a8ae49b3f8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462093924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.462093924 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.452879254 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14866980000 ps |
| CPU time | 58.68 seconds |
| Started | Jul 05 04:34:13 PM PDT 24 |
| Finished | Jul 05 04:36:14 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-98756104-5845-42f8-b825-31569b0efe37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452879254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.452879254 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1772488800 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3753480000 ps |
| CPU time | 15.49 seconds |
| Started | Jul 05 04:34:32 PM PDT 24 |
| Finished | Jul 05 04:35:02 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-9d90df37-0073-4f79-8d4e-c71ac85d21f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772488800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1772488800 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.68217536 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12427280000 ps |
| CPU time | 44.55 seconds |
| Started | Jul 05 04:34:38 PM PDT 24 |
| Finished | Jul 05 04:36:01 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-c6db7f02-fd68-4720-bca9-0d180b66b7fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68217536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.68217536 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1785747961 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7604920000 ps |
| CPU time | 26.47 seconds |
| Started | Jul 05 04:34:33 PM PDT 24 |
| Finished | Jul 05 04:35:28 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-0499fc5a-eba1-4454-a39a-e5b532a8e9c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785747961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1785747961 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |