| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/14.prim_present_test.3347210538 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1405338921 |
| /workspace/coverage/default/1.prim_present_test.2001231681 |
| /workspace/coverage/default/10.prim_present_test.819469157 |
| /workspace/coverage/default/11.prim_present_test.3664689935 |
| /workspace/coverage/default/12.prim_present_test.3944216006 |
| /workspace/coverage/default/13.prim_present_test.2186237015 |
| /workspace/coverage/default/15.prim_present_test.1889512184 |
| /workspace/coverage/default/16.prim_present_test.3176303228 |
| /workspace/coverage/default/17.prim_present_test.2136632990 |
| /workspace/coverage/default/18.prim_present_test.4029839882 |
| /workspace/coverage/default/19.prim_present_test.3137164581 |
| /workspace/coverage/default/2.prim_present_test.1703767306 |
| /workspace/coverage/default/20.prim_present_test.1299006092 |
| /workspace/coverage/default/21.prim_present_test.2692041466 |
| /workspace/coverage/default/22.prim_present_test.2824921484 |
| /workspace/coverage/default/23.prim_present_test.1211025954 |
| /workspace/coverage/default/24.prim_present_test.3791625598 |
| /workspace/coverage/default/25.prim_present_test.437262709 |
| /workspace/coverage/default/26.prim_present_test.681907159 |
| /workspace/coverage/default/27.prim_present_test.797320643 |
| /workspace/coverage/default/28.prim_present_test.411654706 |
| /workspace/coverage/default/29.prim_present_test.2633279547 |
| /workspace/coverage/default/3.prim_present_test.2933647259 |
| /workspace/coverage/default/30.prim_present_test.888972513 |
| /workspace/coverage/default/31.prim_present_test.1493509168 |
| /workspace/coverage/default/32.prim_present_test.1305491563 |
| /workspace/coverage/default/33.prim_present_test.3664750819 |
| /workspace/coverage/default/34.prim_present_test.3285235627 |
| /workspace/coverage/default/35.prim_present_test.3710672000 |
| /workspace/coverage/default/36.prim_present_test.2334226558 |
| /workspace/coverage/default/37.prim_present_test.2981998259 |
| /workspace/coverage/default/38.prim_present_test.3923881657 |
| /workspace/coverage/default/39.prim_present_test.1262361322 |
| /workspace/coverage/default/4.prim_present_test.622862901 |
| /workspace/coverage/default/40.prim_present_test.3920866603 |
| /workspace/coverage/default/41.prim_present_test.1627763042 |
| /workspace/coverage/default/42.prim_present_test.1352572797 |
| /workspace/coverage/default/43.prim_present_test.1451453020 |
| /workspace/coverage/default/44.prim_present_test.4277602818 |
| /workspace/coverage/default/45.prim_present_test.2892885456 |
| /workspace/coverage/default/46.prim_present_test.663517802 |
| /workspace/coverage/default/47.prim_present_test.1765413684 |
| /workspace/coverage/default/48.prim_present_test.273706418 |
| /workspace/coverage/default/49.prim_present_test.279523611 |
| /workspace/coverage/default/5.prim_present_test.2918079218 |
| /workspace/coverage/default/6.prim_present_test.62146217 |
| /workspace/coverage/default/7.prim_present_test.3526898762 |
| /workspace/coverage/default/8.prim_present_test.587799969 |
| /workspace/coverage/default/9.prim_present_test.2831977325 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/14.prim_present_test.3347210538 | Jul 06 05:10:43 PM PDT 24 | Jul 06 05:11:34 PM PDT 24 | 7787820000 ps | ||
| T2 | /workspace/coverage/default/9.prim_present_test.2831977325 | Jul 06 05:10:47 PM PDT 24 | Jul 06 05:12:24 PM PDT 24 | 15349340000 ps | ||
| T3 | /workspace/coverage/default/7.prim_present_test.3526898762 | Jul 06 05:10:58 PM PDT 24 | Jul 06 05:12:05 PM PDT 24 | 8416500000 ps | ||
| T4 | /workspace/coverage/default/49.prim_present_test.279523611 | Jul 06 05:10:53 PM PDT 24 | Jul 06 05:11:47 PM PDT 24 | 8519420000 ps | ||
| T5 | /workspace/coverage/default/15.prim_present_test.1889512184 | Jul 06 05:10:43 PM PDT 24 | Jul 06 05:11:34 PM PDT 24 | 7916160000 ps | ||
| T6 | /workspace/coverage/default/20.prim_present_test.1299006092 | Jul 06 05:10:50 PM PDT 24 | Jul 06 05:11:25 PM PDT 24 | 5542800000 ps | ||
| T7 | /workspace/coverage/default/33.prim_present_test.3664750819 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:11:28 PM PDT 24 | 5355560000 ps | ||
| T8 | /workspace/coverage/default/25.prim_present_test.437262709 | Jul 06 05:10:51 PM PDT 24 | Jul 06 05:12:08 PM PDT 24 | 10616880000 ps | ||
| T9 | /workspace/coverage/default/18.prim_present_test.4029839882 | Jul 06 05:10:59 PM PDT 24 | Jul 06 05:12:30 PM PDT 24 | 11202780000 ps | ||
| T10 | /workspace/coverage/default/6.prim_present_test.62146217 | Jul 06 05:10:57 PM PDT 24 | Jul 06 05:12:21 PM PDT 24 | 10572860000 ps | ||
| T11 | /workspace/coverage/default/17.prim_present_test.2136632990 | Jul 06 05:10:59 PM PDT 24 | Jul 06 05:12:45 PM PDT 24 | 14065940000 ps | ||
| T12 | /workspace/coverage/default/26.prim_present_test.681907159 | Jul 06 05:10:51 PM PDT 24 | Jul 06 05:11:33 PM PDT 24 | 5695320000 ps | ||
| T13 | /workspace/coverage/default/48.prim_present_test.273706418 | Jul 06 05:10:53 PM PDT 24 | Jul 06 05:11:43 PM PDT 24 | 7639020000 ps | ||
| T14 | /workspace/coverage/default/12.prim_present_test.3944216006 | Jul 06 05:10:58 PM PDT 24 | Jul 06 05:11:32 PM PDT 24 | 4020080000 ps | ||
| T15 | /workspace/coverage/default/34.prim_present_test.3285235627 | Jul 06 05:10:48 PM PDT 24 | Jul 06 05:11:14 PM PDT 24 | 4905440000 ps | ||
| T16 | /workspace/coverage/default/8.prim_present_test.587799969 | Jul 06 05:10:45 PM PDT 24 | Jul 06 05:11:45 PM PDT 24 | 9967740000 ps | ||
| T17 | /workspace/coverage/default/2.prim_present_test.1703767306 | Jul 06 05:10:46 PM PDT 24 | Jul 06 05:11:40 PM PDT 24 | 7757440000 ps | ||
| T18 | /workspace/coverage/default/47.prim_present_test.1765413684 | Jul 06 05:10:54 PM PDT 24 | Jul 06 05:11:55 PM PDT 24 | 8376820000 ps | ||
| T19 | /workspace/coverage/default/31.prim_present_test.1493509168 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:12:05 PM PDT 24 | 11539440000 ps | ||
| T20 | /workspace/coverage/default/24.prim_present_test.3791625598 | Jul 06 05:10:50 PM PDT 24 | Jul 06 05:11:56 PM PDT 24 | 8577080000 ps | ||
| T21 | /workspace/coverage/default/21.prim_present_test.2692041466 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:12:23 PM PDT 24 | 14658660000 ps | ||
| T22 | /workspace/coverage/default/45.prim_present_test.2892885456 | Jul 06 05:10:56 PM PDT 24 | Jul 06 05:11:36 PM PDT 24 | 8020940000 ps | ||
| T23 | /workspace/coverage/default/35.prim_present_test.3710672000 | Jul 06 05:10:51 PM PDT 24 | Jul 06 05:12:14 PM PDT 24 | 11428460000 ps | ||
| T24 | /workspace/coverage/default/4.prim_present_test.622862901 | Jul 06 05:10:46 PM PDT 24 | Jul 06 05:11:37 PM PDT 24 | 7645840000 ps | ||
| T25 | /workspace/coverage/default/44.prim_present_test.4277602818 | Jul 06 05:10:54 PM PDT 24 | Jul 06 05:11:24 PM PDT 24 | 4310860000 ps | ||
| T26 | /workspace/coverage/default/32.prim_present_test.1305491563 | Jul 06 05:10:51 PM PDT 24 | Jul 06 05:12:47 PM PDT 24 | 14767160000 ps | ||
| T27 | /workspace/coverage/default/28.prim_present_test.411654706 | Jul 06 05:10:48 PM PDT 24 | Jul 06 05:11:13 PM PDT 24 | 3282280000 ps | ||
| T28 | /workspace/coverage/default/42.prim_present_test.1352572797 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:11:24 PM PDT 24 | 4998440000 ps | ||
| T29 | /workspace/coverage/default/37.prim_present_test.2981998259 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:11:35 PM PDT 24 | 6843560000 ps | ||
| T30 | /workspace/coverage/default/29.prim_present_test.2633279547 | Jul 06 05:10:59 PM PDT 24 | Jul 06 05:11:34 PM PDT 24 | 4255680000 ps | ||
| T31 | /workspace/coverage/default/3.prim_present_test.2933647259 | Jul 06 05:10:44 PM PDT 24 | Jul 06 05:11:17 PM PDT 24 | 5464680000 ps | ||
| T32 | /workspace/coverage/default/40.prim_present_test.3920866603 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:11:37 PM PDT 24 | 7534860000 ps | ||
| T33 | /workspace/coverage/default/41.prim_present_test.1627763042 | Jul 06 05:10:51 PM PDT 24 | Jul 06 05:11:25 PM PDT 24 | 3837180000 ps | ||
| T34 | /workspace/coverage/default/13.prim_present_test.2186237015 | Jul 06 05:10:58 PM PDT 24 | Jul 06 05:12:31 PM PDT 24 | 11705600000 ps | ||
| T35 | /workspace/coverage/default/38.prim_present_test.3923881657 | Jul 06 05:10:50 PM PDT 24 | Jul 06 05:12:24 PM PDT 24 | 13836540000 ps | ||
| T36 | /workspace/coverage/default/43.prim_present_test.1451453020 | Jul 06 05:10:50 PM PDT 24 | Jul 06 05:11:13 PM PDT 24 | 3548260000 ps | ||
| T37 | /workspace/coverage/default/27.prim_present_test.797320643 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:11:10 PM PDT 24 | 3656760000 ps | ||
| T38 | /workspace/coverage/default/16.prim_present_test.3176303228 | Jul 06 05:10:59 PM PDT 24 | Jul 06 05:12:45 PM PDT 24 | 14118640000 ps | ||
| T39 | /workspace/coverage/default/5.prim_present_test.2918079218 | Jul 06 05:10:58 PM PDT 24 | Jul 06 05:12:00 PM PDT 24 | 7508200000 ps | ||
| T40 | /workspace/coverage/default/23.prim_present_test.1211025954 | Jul 06 05:10:47 PM PDT 24 | Jul 06 05:12:20 PM PDT 24 | 13399440000 ps | ||
| T41 | /workspace/coverage/default/11.prim_present_test.3664689935 | Jul 06 05:10:47 PM PDT 24 | Jul 06 05:11:18 PM PDT 24 | 4574980000 ps | ||
| T42 | /workspace/coverage/default/1.prim_present_test.2001231681 | Jul 06 05:10:45 PM PDT 24 | Jul 06 05:11:10 PM PDT 24 | 3293440000 ps | ||
| T43 | /workspace/coverage/default/36.prim_present_test.2334226558 | Jul 06 05:10:53 PM PDT 24 | Jul 06 05:12:26 PM PDT 24 | 14844040000 ps | ||
| T44 | /workspace/coverage/default/30.prim_present_test.888972513 | Jul 06 05:10:48 PM PDT 24 | Jul 06 05:11:34 PM PDT 24 | 7329020000 ps | ||
| T45 | /workspace/coverage/default/0.prim_present_test.1405338921 | Jul 06 05:10:57 PM PDT 24 | Jul 06 05:12:29 PM PDT 24 | 11458840000 ps | ||
| T46 | /workspace/coverage/default/39.prim_present_test.1262361322 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:12:18 PM PDT 24 | 15061660000 ps | ||
| T47 | /workspace/coverage/default/22.prim_present_test.2824921484 | Jul 06 05:10:51 PM PDT 24 | Jul 06 05:12:07 PM PDT 24 | 10419720000 ps | ||
| T48 | /workspace/coverage/default/19.prim_present_test.3137164581 | Jul 06 05:10:49 PM PDT 24 | Jul 06 05:11:55 PM PDT 24 | 9944800000 ps | ||
| T49 | /workspace/coverage/default/10.prim_present_test.819469157 | Jul 06 05:10:43 PM PDT 24 | Jul 06 05:11:14 PM PDT 24 | 4194920000 ps | ||
| T50 | /workspace/coverage/default/46.prim_present_test.663517802 | Jul 06 05:10:54 PM PDT 24 | Jul 06 05:11:42 PM PDT 24 | 7281900000 ps |
| Test location | /workspace/coverage/default/14.prim_present_test.3347210538 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7787820000 ps |
| CPU time | 26.98 seconds |
| Started | Jul 06 05:10:43 PM PDT 24 |
| Finished | Jul 06 05:11:34 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-506cd8d7-b128-4ba9-99c9-90e670484a1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347210538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3347210538 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1405338921 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11458840000 ps |
| CPU time | 46.57 seconds |
| Started | Jul 06 05:10:57 PM PDT 24 |
| Finished | Jul 06 05:12:29 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-fd0f8af1-f5c4-476c-9f53-576c026d7b16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405338921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1405338921 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2001231681 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3293440000 ps |
| CPU time | 12.55 seconds |
| Started | Jul 06 05:10:45 PM PDT 24 |
| Finished | Jul 06 05:11:10 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-fd62719a-b0a3-4a41-a427-078f6ded251d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001231681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2001231681 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.819469157 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4194920000 ps |
| CPU time | 16.01 seconds |
| Started | Jul 06 05:10:43 PM PDT 24 |
| Finished | Jul 06 05:11:14 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-e3b27fe8-2909-46ee-8f78-88c5b196a65e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819469157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.819469157 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3664689935 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4574980000 ps |
| CPU time | 16.58 seconds |
| Started | Jul 06 05:10:47 PM PDT 24 |
| Finished | Jul 06 05:11:18 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-501ded0c-1dfe-4bb1-a578-8232f36ee49a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664689935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3664689935 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3944216006 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4020080000 ps |
| CPU time | 16.79 seconds |
| Started | Jul 06 05:10:58 PM PDT 24 |
| Finished | Jul 06 05:11:32 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-90fd669a-dc82-42b5-b532-e4f5a6a081ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944216006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3944216006 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2186237015 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11705600000 ps |
| CPU time | 47.69 seconds |
| Started | Jul 06 05:10:58 PM PDT 24 |
| Finished | Jul 06 05:12:31 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-0bcd7c1e-b9be-44e3-aaa8-dda784fd0c88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186237015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2186237015 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1889512184 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7916160000 ps |
| CPU time | 26.33 seconds |
| Started | Jul 06 05:10:43 PM PDT 24 |
| Finished | Jul 06 05:11:34 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-a073d456-3374-4f4b-83c6-ee4a1323ca81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889512184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1889512184 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3176303228 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14118640000 ps |
| CPU time | 54.69 seconds |
| Started | Jul 06 05:10:59 PM PDT 24 |
| Finished | Jul 06 05:12:45 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-179bf6b1-c606-4148-afc2-03f99bef166e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176303228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3176303228 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2136632990 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14065940000 ps |
| CPU time | 53.68 seconds |
| Started | Jul 06 05:10:59 PM PDT 24 |
| Finished | Jul 06 05:12:45 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-bf081d57-c964-4100-ab4e-c7cc86b40452 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136632990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2136632990 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.4029839882 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11202780000 ps |
| CPU time | 45.48 seconds |
| Started | Jul 06 05:10:59 PM PDT 24 |
| Finished | Jul 06 05:12:30 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-6e4e8ec2-b0ab-4e1b-bcd4-33d9c2df4b42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029839882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4029839882 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3137164581 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9944800000 ps |
| CPU time | 34.25 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:11:55 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-44fbb2da-7883-4bc6-99fc-b27084387567 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137164581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3137164581 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1703767306 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7757440000 ps |
| CPU time | 27.87 seconds |
| Started | Jul 06 05:10:46 PM PDT 24 |
| Finished | Jul 06 05:11:40 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-95ed1bca-32cb-4536-b29a-c1e2d7d4606f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703767306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1703767306 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1299006092 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5542800000 ps |
| CPU time | 19.19 seconds |
| Started | Jul 06 05:10:50 PM PDT 24 |
| Finished | Jul 06 05:11:25 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-614b0bde-7feb-4989-9965-751a250bd73c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299006092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1299006092 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2692041466 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14658660000 ps |
| CPU time | 50.24 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:12:23 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-9c00dd2d-b400-4ac0-8e73-4d90da59726a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692041466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2692041466 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2824921484 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10419720000 ps |
| CPU time | 39.85 seconds |
| Started | Jul 06 05:10:51 PM PDT 24 |
| Finished | Jul 06 05:12:07 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-16a27070-e5d3-4b2a-9f8a-d9c72647b5ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824921484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2824921484 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1211025954 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13399440000 ps |
| CPU time | 49.34 seconds |
| Started | Jul 06 05:10:47 PM PDT 24 |
| Finished | Jul 06 05:12:20 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-7701be4e-4bed-4f6a-b1d5-e3a8529b2d7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1211025954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1211025954 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3791625598 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8577080000 ps |
| CPU time | 34.2 seconds |
| Started | Jul 06 05:10:50 PM PDT 24 |
| Finished | Jul 06 05:11:56 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-fd43d9f5-dafa-4f80-9cdc-6d7ce70446ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791625598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3791625598 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.437262709 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10616880000 ps |
| CPU time | 40.13 seconds |
| Started | Jul 06 05:10:51 PM PDT 24 |
| Finished | Jul 06 05:12:08 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-27092a42-d785-4089-ae15-f187f09ae2a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437262709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.437262709 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.681907159 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5695320000 ps |
| CPU time | 21.58 seconds |
| Started | Jul 06 05:10:51 PM PDT 24 |
| Finished | Jul 06 05:11:33 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-8934226d-4f37-4d0d-9523-572552a89c0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681907159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.681907159 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.797320643 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3656760000 ps |
| CPU time | 10.99 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:11:10 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-4c4145a6-37b8-4c7e-b270-2f988b7d8405 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797320643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.797320643 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.411654706 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3282280000 ps |
| CPU time | 12.34 seconds |
| Started | Jul 06 05:10:48 PM PDT 24 |
| Finished | Jul 06 05:11:13 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-8a0f8ae3-e111-4613-88d8-1334ff482a16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411654706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.411654706 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2633279547 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4255680000 ps |
| CPU time | 17.87 seconds |
| Started | Jul 06 05:10:59 PM PDT 24 |
| Finished | Jul 06 05:11:34 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-75a6910a-73a9-4cc6-966c-6b7370e49517 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2633279547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2633279547 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2933647259 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5464680000 ps |
| CPU time | 17.88 seconds |
| Started | Jul 06 05:10:44 PM PDT 24 |
| Finished | Jul 06 05:11:17 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-48fd7487-f85e-4bd8-9f10-0f5939f19345 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933647259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2933647259 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.888972513 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7329020000 ps |
| CPU time | 24.51 seconds |
| Started | Jul 06 05:10:48 PM PDT 24 |
| Finished | Jul 06 05:11:34 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-79a725ee-2770-491a-af40-501ef0facae3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888972513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.888972513 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1493509168 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11539440000 ps |
| CPU time | 39.88 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:12:05 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-0b57467f-7963-46d9-b9b0-3c63a7534a7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493509168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1493509168 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1305491563 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14767160000 ps |
| CPU time | 59.5 seconds |
| Started | Jul 06 05:10:51 PM PDT 24 |
| Finished | Jul 06 05:12:47 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a0a98be0-baad-4914-92ee-7fffa828fb6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1305491563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1305491563 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3664750819 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5355560000 ps |
| CPU time | 20.17 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:11:28 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-59b62d94-d978-49d9-a6e5-41ec699695f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664750819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3664750819 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3285235627 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4905440000 ps |
| CPU time | 13.83 seconds |
| Started | Jul 06 05:10:48 PM PDT 24 |
| Finished | Jul 06 05:11:14 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-53db3db7-cfc1-4a8b-a3f4-fcd345bd5602 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285235627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3285235627 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3710672000 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11428460000 ps |
| CPU time | 43.47 seconds |
| Started | Jul 06 05:10:51 PM PDT 24 |
| Finished | Jul 06 05:12:14 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-8c4738c6-9c3c-4826-9367-06a07bc1aec3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710672000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3710672000 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2334226558 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14844040000 ps |
| CPU time | 49.61 seconds |
| Started | Jul 06 05:10:53 PM PDT 24 |
| Finished | Jul 06 05:12:26 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c34ca79c-60b1-424e-a458-a63436ace619 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334226558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2334226558 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2981998259 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6843560000 ps |
| CPU time | 23.99 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:11:35 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-a2cfb8e6-dfea-4107-9d07-96e6ade4dfbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981998259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2981998259 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3923881657 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13836540000 ps |
| CPU time | 49.82 seconds |
| Started | Jul 06 05:10:50 PM PDT 24 |
| Finished | Jul 06 05:12:24 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-42041bfc-ff94-4162-bceb-33308d74b8d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3923881657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3923881657 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1262361322 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15061660000 ps |
| CPU time | 47.81 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:12:18 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-16ebdf55-4f41-4592-a9c7-8f99a2a52602 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262361322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1262361322 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.622862901 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7645840000 ps |
| CPU time | 27.04 seconds |
| Started | Jul 06 05:10:46 PM PDT 24 |
| Finished | Jul 06 05:11:37 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-26ea8aef-740c-4798-9f38-cefa4efee58b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622862901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.622862901 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3920866603 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7534860000 ps |
| CPU time | 25.44 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:11:37 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-ac5eba17-4686-4a94-9384-d3c22333cf69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920866603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3920866603 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1627763042 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3837180000 ps |
| CPU time | 17.56 seconds |
| Started | Jul 06 05:10:51 PM PDT 24 |
| Finished | Jul 06 05:11:25 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-98982f65-9ace-4b16-b602-eca51aa45aaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627763042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1627763042 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1352572797 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4998440000 ps |
| CPU time | 18.39 seconds |
| Started | Jul 06 05:10:49 PM PDT 24 |
| Finished | Jul 06 05:11:24 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-429bf2e8-eec9-45fd-95c9-1ac293b0f9e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352572797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1352572797 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1451453020 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3548260000 ps |
| CPU time | 12.4 seconds |
| Started | Jul 06 05:10:50 PM PDT 24 |
| Finished | Jul 06 05:11:13 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-558e9847-6e90-4f8b-9d8e-e4e325e93645 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451453020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1451453020 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.4277602818 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4310860000 ps |
| CPU time | 15.51 seconds |
| Started | Jul 06 05:10:54 PM PDT 24 |
| Finished | Jul 06 05:11:24 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-53f413e1-0b8d-40cd-b803-3060beb6f520 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277602818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.4277602818 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2892885456 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8020940000 ps |
| CPU time | 21.45 seconds |
| Started | Jul 06 05:10:56 PM PDT 24 |
| Finished | Jul 06 05:11:36 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-9741eca5-0d9d-499b-a0c4-bf16e72b9475 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892885456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2892885456 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.663517802 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7281900000 ps |
| CPU time | 25.37 seconds |
| Started | Jul 06 05:10:54 PM PDT 24 |
| Finished | Jul 06 05:11:42 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-5f3e0ae4-ccde-400a-b708-62ef96fc4536 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663517802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.663517802 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1765413684 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8376820000 ps |
| CPU time | 31.33 seconds |
| Started | Jul 06 05:10:54 PM PDT 24 |
| Finished | Jul 06 05:11:55 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-0304e3f1-922f-441f-abbd-5f11563a7827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765413684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1765413684 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.273706418 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7639020000 ps |
| CPU time | 26.36 seconds |
| Started | Jul 06 05:10:53 PM PDT 24 |
| Finished | Jul 06 05:11:43 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-215d25c6-39cd-44e3-a010-fa3aee1d325f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273706418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.273706418 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.279523611 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8519420000 ps |
| CPU time | 28.51 seconds |
| Started | Jul 06 05:10:53 PM PDT 24 |
| Finished | Jul 06 05:11:47 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-02a79911-8eec-457e-8e41-bce0e20af6be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279523611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.279523611 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2918079218 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7508200000 ps |
| CPU time | 31.53 seconds |
| Started | Jul 06 05:10:58 PM PDT 24 |
| Finished | Jul 06 05:12:00 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-4a2bbb32-61b5-492c-9966-528bfffccfbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918079218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2918079218 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.62146217 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10572860000 ps |
| CPU time | 42.8 seconds |
| Started | Jul 06 05:10:57 PM PDT 24 |
| Finished | Jul 06 05:12:21 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-5e8562fd-2e69-4914-9feb-a6ff5839670b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62146217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.62146217 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3526898762 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8416500000 ps |
| CPU time | 34.17 seconds |
| Started | Jul 06 05:10:58 PM PDT 24 |
| Finished | Jul 06 05:12:05 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-446c50d7-136b-4649-92e9-52e3637beb53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526898762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3526898762 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.587799969 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9967740000 ps |
| CPU time | 31.98 seconds |
| Started | Jul 06 05:10:45 PM PDT 24 |
| Finished | Jul 06 05:11:45 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-9d8e30eb-f971-4018-bc54-f5f087be1824 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587799969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.587799969 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2831977325 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15349340000 ps |
| CPU time | 51.82 seconds |
| Started | Jul 06 05:10:47 PM PDT 24 |
| Finished | Jul 06 05:12:24 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-2bc7208e-dfcc-4512-bb70-3e99c7f6bf1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831977325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2831977325 |
| Directory | /workspace/9.prim_present_test/latest |
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