| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.284035743 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3221025756 |
| /workspace/coverage/default/10.prim_present_test.3984280646 |
| /workspace/coverage/default/11.prim_present_test.1639005627 |
| /workspace/coverage/default/12.prim_present_test.4237478589 |
| /workspace/coverage/default/13.prim_present_test.3909833959 |
| /workspace/coverage/default/14.prim_present_test.1368532564 |
| /workspace/coverage/default/15.prim_present_test.3915459471 |
| /workspace/coverage/default/16.prim_present_test.3231169267 |
| /workspace/coverage/default/17.prim_present_test.3013958831 |
| /workspace/coverage/default/18.prim_present_test.2193175636 |
| /workspace/coverage/default/19.prim_present_test.4183970956 |
| /workspace/coverage/default/2.prim_present_test.3667722713 |
| /workspace/coverage/default/20.prim_present_test.4089679510 |
| /workspace/coverage/default/21.prim_present_test.1667035948 |
| /workspace/coverage/default/22.prim_present_test.1155813810 |
| /workspace/coverage/default/23.prim_present_test.1885620417 |
| /workspace/coverage/default/24.prim_present_test.166807913 |
| /workspace/coverage/default/25.prim_present_test.4013568712 |
| /workspace/coverage/default/26.prim_present_test.2480424034 |
| /workspace/coverage/default/27.prim_present_test.3488521180 |
| /workspace/coverage/default/28.prim_present_test.1965875358 |
| /workspace/coverage/default/29.prim_present_test.1757768004 |
| /workspace/coverage/default/3.prim_present_test.35097475 |
| /workspace/coverage/default/30.prim_present_test.3120672370 |
| /workspace/coverage/default/31.prim_present_test.464911570 |
| /workspace/coverage/default/32.prim_present_test.1489799162 |
| /workspace/coverage/default/33.prim_present_test.4202789965 |
| /workspace/coverage/default/34.prim_present_test.1235920756 |
| /workspace/coverage/default/35.prim_present_test.3426380766 |
| /workspace/coverage/default/36.prim_present_test.2225460906 |
| /workspace/coverage/default/37.prim_present_test.1149762463 |
| /workspace/coverage/default/38.prim_present_test.2380121517 |
| /workspace/coverage/default/39.prim_present_test.1325601613 |
| /workspace/coverage/default/4.prim_present_test.259580518 |
| /workspace/coverage/default/40.prim_present_test.4244756021 |
| /workspace/coverage/default/41.prim_present_test.2705431438 |
| /workspace/coverage/default/42.prim_present_test.1530302955 |
| /workspace/coverage/default/43.prim_present_test.364785828 |
| /workspace/coverage/default/44.prim_present_test.305547174 |
| /workspace/coverage/default/45.prim_present_test.4157887052 |
| /workspace/coverage/default/46.prim_present_test.1165666270 |
| /workspace/coverage/default/47.prim_present_test.1514514797 |
| /workspace/coverage/default/48.prim_present_test.224370954 |
| /workspace/coverage/default/49.prim_present_test.2885103659 |
| /workspace/coverage/default/5.prim_present_test.1431264096 |
| /workspace/coverage/default/6.prim_present_test.2773798248 |
| /workspace/coverage/default/7.prim_present_test.95253817 |
| /workspace/coverage/default/8.prim_present_test.2892819763 |
| /workspace/coverage/default/9.prim_present_test.1120282190 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/15.prim_present_test.3915459471 | Jul 07 04:17:32 PM PDT 24 | Jul 07 04:18:17 PM PDT 24 | 6188220000 ps | ||
| T2 | /workspace/coverage/default/25.prim_present_test.4013568712 | Jul 07 04:21:12 PM PDT 24 | Jul 07 04:22:33 PM PDT 24 | 12706900000 ps | ||
| T3 | /workspace/coverage/default/21.prim_present_test.1667035948 | Jul 07 04:17:32 PM PDT 24 | Jul 07 04:18:51 PM PDT 24 | 11181700000 ps | ||
| T4 | /workspace/coverage/default/1.prim_present_test.284035743 | Jul 07 04:21:09 PM PDT 24 | Jul 07 04:22:02 PM PDT 24 | 7561520000 ps | ||
| T5 | /workspace/coverage/default/44.prim_present_test.305547174 | Jul 07 04:21:15 PM PDT 24 | Jul 07 04:21:44 PM PDT 24 | 5146000000 ps | ||
| T6 | /workspace/coverage/default/9.prim_present_test.1120282190 | Jul 07 04:21:09 PM PDT 24 | Jul 07 04:22:40 PM PDT 24 | 13986580000 ps | ||
| T7 | /workspace/coverage/default/8.prim_present_test.2892819763 | Jul 07 04:19:57 PM PDT 24 | Jul 07 04:20:54 PM PDT 24 | 9077420000 ps | ||
| T8 | /workspace/coverage/default/27.prim_present_test.3488521180 | Jul 07 04:17:32 PM PDT 24 | Jul 07 04:18:43 PM PDT 24 | 9912560000 ps | ||
| T9 | /workspace/coverage/default/22.prim_present_test.1155813810 | Jul 07 04:21:12 PM PDT 24 | Jul 07 04:22:38 PM PDT 24 | 13643720000 ps | ||
| T10 | /workspace/coverage/default/29.prim_present_test.1757768004 | Jul 07 04:22:03 PM PDT 24 | Jul 07 04:22:31 PM PDT 24 | 5165840000 ps | ||
| T11 | /workspace/coverage/default/12.prim_present_test.4237478589 | Jul 07 04:21:22 PM PDT 24 | Jul 07 04:22:21 PM PDT 24 | 10929360000 ps | ||
| T12 | /workspace/coverage/default/34.prim_present_test.1235920756 | Jul 07 04:19:25 PM PDT 24 | Jul 07 04:19:59 PM PDT 24 | 5127400000 ps | ||
| T13 | /workspace/coverage/default/36.prim_present_test.2225460906 | Jul 07 04:18:16 PM PDT 24 | Jul 07 04:18:46 PM PDT 24 | 4315200000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.2705431438 | Jul 07 04:22:24 PM PDT 24 | Jul 07 04:23:15 PM PDT 24 | 7125040000 ps | ||
| T15 | /workspace/coverage/default/28.prim_present_test.1965875358 | Jul 07 04:21:38 PM PDT 24 | Jul 07 04:22:32 PM PDT 24 | 8864140000 ps | ||
| T16 | /workspace/coverage/default/47.prim_present_test.1514514797 | Jul 07 04:17:27 PM PDT 24 | Jul 07 04:18:53 PM PDT 24 | 12820360000 ps | ||
| T17 | /workspace/coverage/default/17.prim_present_test.3013958831 | Jul 07 04:21:09 PM PDT 24 | Jul 07 04:22:23 PM PDT 24 | 10210160000 ps | ||
| T18 | /workspace/coverage/default/38.prim_present_test.2380121517 | Jul 07 04:19:15 PM PDT 24 | Jul 07 04:20:29 PM PDT 24 | 11798600000 ps | ||
| T19 | /workspace/coverage/default/19.prim_present_test.4183970956 | Jul 07 04:21:11 PM PDT 24 | Jul 07 04:22:26 PM PDT 24 | 11562380000 ps | ||
| T20 | /workspace/coverage/default/18.prim_present_test.2193175636 | Jul 07 04:21:27 PM PDT 24 | Jul 07 04:22:36 PM PDT 24 | 11945540000 ps | ||
| T21 | /workspace/coverage/default/35.prim_present_test.3426380766 | Jul 07 04:20:01 PM PDT 24 | Jul 07 04:20:30 PM PDT 24 | 4346200000 ps | ||
| T22 | /workspace/coverage/default/11.prim_present_test.1639005627 | Jul 07 04:21:08 PM PDT 24 | Jul 07 04:22:33 PM PDT 24 | 11943680000 ps | ||
| T23 | /workspace/coverage/default/26.prim_present_test.2480424034 | Jul 07 04:21:50 PM PDT 24 | Jul 07 04:22:19 PM PDT 24 | 4405720000 ps | ||
| T24 | /workspace/coverage/default/4.prim_present_test.259580518 | Jul 07 04:21:09 PM PDT 24 | Jul 07 04:22:08 PM PDT 24 | 8090380000 ps | ||
| T25 | /workspace/coverage/default/46.prim_present_test.1165666270 | Jul 07 04:22:05 PM PDT 24 | Jul 07 04:22:28 PM PDT 24 | 4390840000 ps | ||
| T26 | /workspace/coverage/default/24.prim_present_test.166807913 | Jul 07 04:21:55 PM PDT 24 | Jul 07 04:22:18 PM PDT 24 | 4454080000 ps | ||
| T27 | /workspace/coverage/default/30.prim_present_test.3120672370 | Jul 07 04:21:23 PM PDT 24 | Jul 07 04:22:10 PM PDT 24 | 7781620000 ps | ||
| T28 | /workspace/coverage/default/2.prim_present_test.3667722713 | Jul 07 04:21:09 PM PDT 24 | Jul 07 04:22:00 PM PDT 24 | 9551720000 ps | ||
| T29 | /workspace/coverage/default/37.prim_present_test.1149762463 | Jul 07 04:20:04 PM PDT 24 | Jul 07 04:21:01 PM PDT 24 | 9412220000 ps | ||
| T30 | /workspace/coverage/default/3.prim_present_test.35097475 | Jul 07 04:17:31 PM PDT 24 | Jul 07 04:18:20 PM PDT 24 | 7056840000 ps | ||
| T31 | /workspace/coverage/default/45.prim_present_test.4157887052 | Jul 07 04:21:29 PM PDT 24 | Jul 07 04:22:54 PM PDT 24 | 15071580000 ps | ||
| T32 | /workspace/coverage/default/32.prim_present_test.1489799162 | Jul 07 04:17:27 PM PDT 24 | Jul 07 04:18:25 PM PDT 24 | 8652100000 ps | ||
| T33 | /workspace/coverage/default/49.prim_present_test.2885103659 | Jul 07 04:22:09 PM PDT 24 | Jul 07 04:22:57 PM PDT 24 | 7750620000 ps | ||
| T34 | /workspace/coverage/default/20.prim_present_test.4089679510 | Jul 07 04:21:12 PM PDT 24 | Jul 07 04:21:42 PM PDT 24 | 4912880000 ps | ||
| T35 | /workspace/coverage/default/39.prim_present_test.1325601613 | Jul 07 04:17:30 PM PDT 24 | Jul 07 04:18:02 PM PDT 24 | 4619620000 ps | ||
| T36 | /workspace/coverage/default/43.prim_present_test.364785828 | Jul 07 04:23:06 PM PDT 24 | Jul 07 04:24:05 PM PDT 24 | 10768160000 ps | ||
| T37 | /workspace/coverage/default/31.prim_present_test.464911570 | Jul 07 04:21:23 PM PDT 24 | Jul 07 04:22:34 PM PDT 24 | 12362180000 ps | ||
| T38 | /workspace/coverage/default/0.prim_present_test.3221025756 | Jul 07 04:20:08 PM PDT 24 | Jul 07 04:21:26 PM PDT 24 | 11910820000 ps | ||
| T39 | /workspace/coverage/default/23.prim_present_test.1885620417 | Jul 07 04:21:27 PM PDT 24 | Jul 07 04:22:07 PM PDT 24 | 6715840000 ps | ||
| T40 | /workspace/coverage/default/42.prim_present_test.1530302955 | Jul 07 04:21:15 PM PDT 24 | Jul 07 04:22:07 PM PDT 24 | 8950320000 ps | ||
| T41 | /workspace/coverage/default/40.prim_present_test.4244756021 | Jul 07 04:22:24 PM PDT 24 | Jul 07 04:23:44 PM PDT 24 | 13065880000 ps | ||
| T42 | /workspace/coverage/default/14.prim_present_test.1368532564 | Jul 07 04:21:10 PM PDT 24 | Jul 07 04:22:08 PM PDT 24 | 10383760000 ps | ||
| T43 | /workspace/coverage/default/13.prim_present_test.3909833959 | Jul 07 04:18:14 PM PDT 24 | Jul 07 04:18:39 PM PDT 24 | 3806800000 ps | ||
| T44 | /workspace/coverage/default/6.prim_present_test.2773798248 | Jul 07 04:22:29 PM PDT 24 | Jul 07 04:23:28 PM PDT 24 | 11002520000 ps | ||
| T45 | /workspace/coverage/default/5.prim_present_test.1431264096 | Jul 07 04:20:08 PM PDT 24 | Jul 07 04:21:14 PM PDT 24 | 10138860000 ps | ||
| T46 | /workspace/coverage/default/16.prim_present_test.3231169267 | Jul 07 04:19:46 PM PDT 24 | Jul 07 04:21:01 PM PDT 24 | 10306260000 ps | ||
| T47 | /workspace/coverage/default/33.prim_present_test.4202789965 | Jul 07 04:20:02 PM PDT 24 | Jul 07 04:20:34 PM PDT 24 | 4994720000 ps | ||
| T48 | /workspace/coverage/default/7.prim_present_test.95253817 | Jul 07 04:17:59 PM PDT 24 | Jul 07 04:19:13 PM PDT 24 | 10973380000 ps | ||
| T49 | /workspace/coverage/default/48.prim_present_test.224370954 | Jul 07 04:22:04 PM PDT 24 | Jul 07 04:23:29 PM PDT 24 | 14043620000 ps | ||
| T50 | /workspace/coverage/default/10.prim_present_test.3984280646 | Jul 07 04:18:45 PM PDT 24 | Jul 07 04:19:37 PM PDT 24 | 7843620000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.284035743 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7561520000 ps |
| CPU time | 27.75 seconds |
| Started | Jul 07 04:21:09 PM PDT 24 |
| Finished | Jul 07 04:22:02 PM PDT 24 |
| Peak memory | 144600 kb |
| Host | smart-7294de3d-da54-4eda-aef5-63183d46dcad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284035743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.284035743 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3221025756 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11910820000 ps |
| CPU time | 42.2 seconds |
| Started | Jul 07 04:20:08 PM PDT 24 |
| Finished | Jul 07 04:21:26 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-fe21ec8a-ffcf-4802-a7fd-aed95693e9a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221025756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3221025756 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3984280646 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7843620000 ps |
| CPU time | 27.34 seconds |
| Started | Jul 07 04:18:45 PM PDT 24 |
| Finished | Jul 07 04:19:37 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-1147808a-261c-4e55-9f02-c86d7498f88c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984280646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3984280646 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1639005627 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11943680000 ps |
| CPU time | 44.61 seconds |
| Started | Jul 07 04:21:08 PM PDT 24 |
| Finished | Jul 07 04:22:33 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-4e42eced-c068-4a5c-bf38-182a63b6783f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639005627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1639005627 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4237478589 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10929360000 ps |
| CPU time | 32.35 seconds |
| Started | Jul 07 04:21:22 PM PDT 24 |
| Finished | Jul 07 04:22:21 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-1b17ef66-3be8-4634-bc10-7792b1662089 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237478589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4237478589 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3909833959 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3806800000 ps |
| CPU time | 13.59 seconds |
| Started | Jul 07 04:18:14 PM PDT 24 |
| Finished | Jul 07 04:18:39 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-b0576bb0-4091-46db-a71c-8cfe17748768 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909833959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3909833959 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1368532564 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10383760000 ps |
| CPU time | 31.89 seconds |
| Started | Jul 07 04:21:10 PM PDT 24 |
| Finished | Jul 07 04:22:08 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-3745e95f-de6a-4255-844c-eb90597e9a2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1368532564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1368532564 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3915459471 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6188220000 ps |
| CPU time | 23.95 seconds |
| Started | Jul 07 04:17:32 PM PDT 24 |
| Finished | Jul 07 04:18:17 PM PDT 24 |
| Peak memory | 145340 kb |
| Host | smart-65fca3d5-32e0-4787-a277-70d226fed164 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915459471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3915459471 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3231169267 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10306260000 ps |
| CPU time | 39.45 seconds |
| Started | Jul 07 04:19:46 PM PDT 24 |
| Finished | Jul 07 04:21:01 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-410116f9-133f-4d0c-b35c-8c02a097eabd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231169267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3231169267 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3013958831 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10210160000 ps |
| CPU time | 38.93 seconds |
| Started | Jul 07 04:21:09 PM PDT 24 |
| Finished | Jul 07 04:22:23 PM PDT 24 |
| Peak memory | 144548 kb |
| Host | smart-048f5a50-fbc6-49c1-b37d-21cce6e15fe1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013958831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3013958831 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2193175636 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11945540000 ps |
| CPU time | 37.19 seconds |
| Started | Jul 07 04:21:27 PM PDT 24 |
| Finished | Jul 07 04:22:36 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-bcc60df9-94b0-422b-99f6-7cb2212c0db1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193175636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2193175636 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.4183970956 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11562380000 ps |
| CPU time | 39.71 seconds |
| Started | Jul 07 04:21:11 PM PDT 24 |
| Finished | Jul 07 04:22:26 PM PDT 24 |
| Peak memory | 143076 kb |
| Host | smart-001e4008-f88f-473d-98f2-3f739dedb2cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183970956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.4183970956 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3667722713 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9551720000 ps |
| CPU time | 28.14 seconds |
| Started | Jul 07 04:21:09 PM PDT 24 |
| Finished | Jul 07 04:22:00 PM PDT 24 |
| Peak memory | 143828 kb |
| Host | smart-ade500f6-b9bb-43da-af5f-629b6c1d9dd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667722713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3667722713 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.4089679510 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4912880000 ps |
| CPU time | 16.33 seconds |
| Started | Jul 07 04:21:12 PM PDT 24 |
| Finished | Jul 07 04:21:42 PM PDT 24 |
| Peak memory | 143220 kb |
| Host | smart-304c30cc-8cff-4726-b25a-82cc044a02ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089679510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.4089679510 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1667035948 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11181700000 ps |
| CPU time | 41.78 seconds |
| Started | Jul 07 04:17:32 PM PDT 24 |
| Finished | Jul 07 04:18:51 PM PDT 24 |
| Peak memory | 145340 kb |
| Host | smart-7824b54d-e3a5-4b69-aaa1-d927eef45e31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667035948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1667035948 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1155813810 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13643720000 ps |
| CPU time | 45.57 seconds |
| Started | Jul 07 04:21:12 PM PDT 24 |
| Finished | Jul 07 04:22:38 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-bd28632a-cbde-4f48-8795-d5acf5f40310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155813810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1155813810 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1885620417 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6715840000 ps |
| CPU time | 22.27 seconds |
| Started | Jul 07 04:21:27 PM PDT 24 |
| Finished | Jul 07 04:22:07 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-fa31d5f2-9dd5-464f-8933-bc823014a3f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885620417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1885620417 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.166807913 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4454080000 ps |
| CPU time | 12.68 seconds |
| Started | Jul 07 04:21:55 PM PDT 24 |
| Finished | Jul 07 04:22:18 PM PDT 24 |
| Peak memory | 144516 kb |
| Host | smart-e2681607-1bd2-41d8-a4e6-d6c8ae728558 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=166807913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.166807913 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4013568712 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12706900000 ps |
| CPU time | 42.92 seconds |
| Started | Jul 07 04:21:12 PM PDT 24 |
| Finished | Jul 07 04:22:33 PM PDT 24 |
| Peak memory | 144756 kb |
| Host | smart-6141398e-9ca9-4415-abe8-55d0cad2345b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013568712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4013568712 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2480424034 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4405720000 ps |
| CPU time | 14.7 seconds |
| Started | Jul 07 04:21:50 PM PDT 24 |
| Finished | Jul 07 04:22:19 PM PDT 24 |
| Peak memory | 143832 kb |
| Host | smart-15def8c9-a1e0-4e36-82fa-1f577e0ac18c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480424034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2480424034 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3488521180 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9912560000 ps |
| CPU time | 37.76 seconds |
| Started | Jul 07 04:17:32 PM PDT 24 |
| Finished | Jul 07 04:18:43 PM PDT 24 |
| Peak memory | 145340 kb |
| Host | smart-7bfe0ab8-ebb6-4078-8f47-c5c76c1c415d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488521180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3488521180 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1965875358 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8864140000 ps |
| CPU time | 28.32 seconds |
| Started | Jul 07 04:21:38 PM PDT 24 |
| Finished | Jul 07 04:22:32 PM PDT 24 |
| Peak memory | 143904 kb |
| Host | smart-4f2dc5bb-04dc-42bd-8ba1-f8106359156a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965875358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1965875358 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1757768004 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5165840000 ps |
| CPU time | 15.35 seconds |
| Started | Jul 07 04:22:03 PM PDT 24 |
| Finished | Jul 07 04:22:31 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-3e9ff94c-11ab-40a2-9cb3-73f265c8a9a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757768004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1757768004 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.35097475 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7056840000 ps |
| CPU time | 25.6 seconds |
| Started | Jul 07 04:17:31 PM PDT 24 |
| Finished | Jul 07 04:18:20 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-b1b90b1b-99d8-4265-b041-d787cd9613b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35097475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.35097475 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3120672370 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7781620000 ps |
| CPU time | 25.36 seconds |
| Started | Jul 07 04:21:23 PM PDT 24 |
| Finished | Jul 07 04:22:10 PM PDT 24 |
| Peak memory | 144464 kb |
| Host | smart-ce564118-4756-46b8-9fe5-66990d54cbbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120672370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3120672370 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.464911570 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12362180000 ps |
| CPU time | 38.43 seconds |
| Started | Jul 07 04:21:23 PM PDT 24 |
| Finished | Jul 07 04:22:34 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-70e2e0f3-fe16-41ce-ab4d-f3b1b0ac9694 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464911570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.464911570 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1489799162 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8652100000 ps |
| CPU time | 31.3 seconds |
| Started | Jul 07 04:17:27 PM PDT 24 |
| Finished | Jul 07 04:18:25 PM PDT 24 |
| Peak memory | 145356 kb |
| Host | smart-5d697096-59d3-457c-8379-bf4cbfb45042 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489799162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1489799162 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.4202789965 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4994720000 ps |
| CPU time | 17.67 seconds |
| Started | Jul 07 04:20:02 PM PDT 24 |
| Finished | Jul 07 04:20:34 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-b37f276c-872a-49ad-9346-18beb07cb222 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202789965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.4202789965 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1235920756 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5127400000 ps |
| CPU time | 18.26 seconds |
| Started | Jul 07 04:19:25 PM PDT 24 |
| Finished | Jul 07 04:19:59 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-40e48196-ecd2-4167-8785-c84697501a21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235920756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1235920756 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3426380766 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4346200000 ps |
| CPU time | 15.66 seconds |
| Started | Jul 07 04:20:01 PM PDT 24 |
| Finished | Jul 07 04:20:30 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-4547a2cd-64b4-49ec-a361-3c09aa1133ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426380766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3426380766 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2225460906 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4315200000 ps |
| CPU time | 16.06 seconds |
| Started | Jul 07 04:18:16 PM PDT 24 |
| Finished | Jul 07 04:18:46 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-75310d5c-0529-485a-bd9d-f6c04c44ada7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225460906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2225460906 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1149762463 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9412220000 ps |
| CPU time | 30.7 seconds |
| Started | Jul 07 04:20:04 PM PDT 24 |
| Finished | Jul 07 04:21:01 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-9c66885d-72ed-4048-9181-1249350c68aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149762463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1149762463 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2380121517 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11798600000 ps |
| CPU time | 39.87 seconds |
| Started | Jul 07 04:19:15 PM PDT 24 |
| Finished | Jul 07 04:20:29 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-d4a1153c-28aa-4336-a0c6-4d5bdeebc4de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380121517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2380121517 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1325601613 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4619620000 ps |
| CPU time | 16.63 seconds |
| Started | Jul 07 04:17:30 PM PDT 24 |
| Finished | Jul 07 04:18:02 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-bfd5c4c7-b03f-49f6-9b3e-d4672f37004d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325601613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1325601613 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.259580518 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8090380000 ps |
| CPU time | 31.4 seconds |
| Started | Jul 07 04:21:09 PM PDT 24 |
| Finished | Jul 07 04:22:08 PM PDT 24 |
| Peak memory | 144612 kb |
| Host | smart-6f27e2c0-69b1-47c5-a727-a2e41f46c10e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259580518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.259580518 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4244756021 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13065880000 ps |
| CPU time | 42.53 seconds |
| Started | Jul 07 04:22:24 PM PDT 24 |
| Finished | Jul 07 04:23:44 PM PDT 24 |
| Peak memory | 143280 kb |
| Host | smart-22dd99fb-c0b6-4a7e-903e-4e086577a4e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4244756021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4244756021 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2705431438 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7125040000 ps |
| CPU time | 26.93 seconds |
| Started | Jul 07 04:22:24 PM PDT 24 |
| Finished | Jul 07 04:23:15 PM PDT 24 |
| Peak memory | 143488 kb |
| Host | smart-88829292-9397-4ee9-ad4a-14e65bb5daf0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705431438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2705431438 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1530302955 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8950320000 ps |
| CPU time | 27.94 seconds |
| Started | Jul 07 04:21:15 PM PDT 24 |
| Finished | Jul 07 04:22:07 PM PDT 24 |
| Peak memory | 143848 kb |
| Host | smart-cc33bd43-91f2-471d-9007-d874b3e598c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530302955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1530302955 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.364785828 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10768160000 ps |
| CPU time | 31.77 seconds |
| Started | Jul 07 04:23:06 PM PDT 24 |
| Finished | Jul 07 04:24:05 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-1b2d0385-04ba-406f-882d-e4ad27ece8d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=364785828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.364785828 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.305547174 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5146000000 ps |
| CPU time | 16.13 seconds |
| Started | Jul 07 04:21:15 PM PDT 24 |
| Finished | Jul 07 04:21:44 PM PDT 24 |
| Peak memory | 143488 kb |
| Host | smart-d098520f-2595-4dad-9e0a-69a81fbab0e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=305547174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.305547174 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4157887052 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15071580000 ps |
| CPU time | 46.08 seconds |
| Started | Jul 07 04:21:29 PM PDT 24 |
| Finished | Jul 07 04:22:54 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-fa8364cc-421e-4545-8c2b-1cfa4265b0e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157887052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4157887052 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1165666270 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4390840000 ps |
| CPU time | 12.63 seconds |
| Started | Jul 07 04:22:05 PM PDT 24 |
| Finished | Jul 07 04:22:28 PM PDT 24 |
| Peak memory | 143728 kb |
| Host | smart-ee1427c1-6de7-4baa-a378-733ce682733b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165666270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1165666270 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1514514797 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12820360000 ps |
| CPU time | 46.45 seconds |
| Started | Jul 07 04:17:27 PM PDT 24 |
| Finished | Jul 07 04:18:53 PM PDT 24 |
| Peak memory | 145356 kb |
| Host | smart-7c7f99b2-4e4c-4b5f-996f-b4f00cad537a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514514797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1514514797 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.224370954 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14043620000 ps |
| CPU time | 46.26 seconds |
| Started | Jul 07 04:22:04 PM PDT 24 |
| Finished | Jul 07 04:23:29 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-2dc179e4-f5d3-4ece-9bf5-823a6ddcb266 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=224370954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.224370954 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2885103659 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7750620000 ps |
| CPU time | 25.98 seconds |
| Started | Jul 07 04:22:09 PM PDT 24 |
| Finished | Jul 07 04:22:57 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-3a7ace44-07d1-4e00-a6ff-19365611774a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885103659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2885103659 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1431264096 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10138860000 ps |
| CPU time | 35.24 seconds |
| Started | Jul 07 04:20:08 PM PDT 24 |
| Finished | Jul 07 04:21:14 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-fbf4a6e5-45f0-452f-8898-cde148600995 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431264096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1431264096 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2773798248 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11002520000 ps |
| CPU time | 31.95 seconds |
| Started | Jul 07 04:22:29 PM PDT 24 |
| Finished | Jul 07 04:23:28 PM PDT 24 |
| Peak memory | 144512 kb |
| Host | smart-54a96c69-2ddc-445c-8bc5-032ab2747c65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773798248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2773798248 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.95253817 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10973380000 ps |
| CPU time | 39.38 seconds |
| Started | Jul 07 04:17:59 PM PDT 24 |
| Finished | Jul 07 04:19:13 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-08f6592b-8583-487d-8030-2c8ccc92c868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95253817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.95253817 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2892819763 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9077420000 ps |
| CPU time | 30.74 seconds |
| Started | Jul 07 04:19:57 PM PDT 24 |
| Finished | Jul 07 04:20:54 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-a33b03df-e597-4db7-b5af-1a10069ebb72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892819763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2892819763 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1120282190 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13986580000 ps |
| CPU time | 48.93 seconds |
| Started | Jul 07 04:21:09 PM PDT 24 |
| Finished | Jul 07 04:22:40 PM PDT 24 |
| Peak memory | 144676 kb |
| Host | smart-12ffe3b2-9791-4e66-86d5-c0ae62050b26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120282190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1120282190 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |