| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.116553681 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3187128546 |
| /workspace/coverage/default/10.prim_present_test.2054896489 |
| /workspace/coverage/default/11.prim_present_test.1107394656 |
| /workspace/coverage/default/12.prim_present_test.3470135354 |
| /workspace/coverage/default/13.prim_present_test.3833217606 |
| /workspace/coverage/default/14.prim_present_test.2175198309 |
| /workspace/coverage/default/15.prim_present_test.668440488 |
| /workspace/coverage/default/16.prim_present_test.3137457995 |
| /workspace/coverage/default/17.prim_present_test.804753619 |
| /workspace/coverage/default/18.prim_present_test.2645350190 |
| /workspace/coverage/default/19.prim_present_test.791957641 |
| /workspace/coverage/default/2.prim_present_test.1188302366 |
| /workspace/coverage/default/20.prim_present_test.2048970723 |
| /workspace/coverage/default/21.prim_present_test.385730930 |
| /workspace/coverage/default/22.prim_present_test.1925375824 |
| /workspace/coverage/default/23.prim_present_test.1947640001 |
| /workspace/coverage/default/24.prim_present_test.1508222316 |
| /workspace/coverage/default/25.prim_present_test.3362730164 |
| /workspace/coverage/default/26.prim_present_test.1086425873 |
| /workspace/coverage/default/27.prim_present_test.863343269 |
| /workspace/coverage/default/28.prim_present_test.992945598 |
| /workspace/coverage/default/29.prim_present_test.1557524866 |
| /workspace/coverage/default/3.prim_present_test.2499491604 |
| /workspace/coverage/default/30.prim_present_test.347376140 |
| /workspace/coverage/default/31.prim_present_test.403486229 |
| /workspace/coverage/default/32.prim_present_test.2986263450 |
| /workspace/coverage/default/33.prim_present_test.1880019023 |
| /workspace/coverage/default/34.prim_present_test.1559509623 |
| /workspace/coverage/default/35.prim_present_test.1028546553 |
| /workspace/coverage/default/36.prim_present_test.2806088605 |
| /workspace/coverage/default/37.prim_present_test.685519493 |
| /workspace/coverage/default/38.prim_present_test.3371133025 |
| /workspace/coverage/default/39.prim_present_test.3223820623 |
| /workspace/coverage/default/4.prim_present_test.2350642393 |
| /workspace/coverage/default/40.prim_present_test.2197409596 |
| /workspace/coverage/default/41.prim_present_test.3442192948 |
| /workspace/coverage/default/42.prim_present_test.2527519670 |
| /workspace/coverage/default/43.prim_present_test.891369795 |
| /workspace/coverage/default/44.prim_present_test.3844713520 |
| /workspace/coverage/default/45.prim_present_test.1941714832 |
| /workspace/coverage/default/46.prim_present_test.290753125 |
| /workspace/coverage/default/47.prim_present_test.2121208794 |
| /workspace/coverage/default/48.prim_present_test.142706438 |
| /workspace/coverage/default/49.prim_present_test.344795718 |
| /workspace/coverage/default/5.prim_present_test.1938809420 |
| /workspace/coverage/default/6.prim_present_test.2270422829 |
| /workspace/coverage/default/7.prim_present_test.2300177446 |
| /workspace/coverage/default/8.prim_present_test.678498997 |
| /workspace/coverage/default/9.prim_present_test.408337885 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_present_test.2300177446 | Jul 09 05:49:32 PM PDT 24 | Jul 09 05:50:11 PM PDT 24 | 7016540000 ps | ||
| T2 | /workspace/coverage/default/33.prim_present_test.1880019023 | Jul 09 05:49:20 PM PDT 24 | Jul 09 05:50:40 PM PDT 24 | 15452260000 ps | ||
| T3 | /workspace/coverage/default/20.prim_present_test.2048970723 | Jul 09 05:49:17 PM PDT 24 | Jul 09 05:49:56 PM PDT 24 | 5636420000 ps | ||
| T4 | /workspace/coverage/default/2.prim_present_test.1188302366 | Jul 09 05:49:09 PM PDT 24 | Jul 09 05:49:43 PM PDT 24 | 4688440000 ps | ||
| T5 | /workspace/coverage/default/16.prim_present_test.3137457995 | Jul 09 05:49:21 PM PDT 24 | Jul 09 05:49:46 PM PDT 24 | 4240180000 ps | ||
| T6 | /workspace/coverage/default/39.prim_present_test.3223820623 | Jul 09 05:49:25 PM PDT 24 | Jul 09 05:50:05 PM PDT 24 | 6550920000 ps | ||
| T7 | /workspace/coverage/default/25.prim_present_test.3362730164 | Jul 09 05:49:17 PM PDT 24 | Jul 09 05:50:55 PM PDT 24 | 15133580000 ps | ||
| T8 | /workspace/coverage/default/45.prim_present_test.1941714832 | Jul 09 05:49:24 PM PDT 24 | Jul 09 05:50:44 PM PDT 24 | 12845780000 ps | ||
| T9 | /workspace/coverage/default/1.prim_present_test.116553681 | Jul 09 05:49:09 PM PDT 24 | Jul 09 05:50:35 PM PDT 24 | 12996440000 ps | ||
| T10 | /workspace/coverage/default/15.prim_present_test.668440488 | Jul 09 05:49:18 PM PDT 24 | Jul 09 05:49:52 PM PDT 24 | 4743620000 ps | ||
| T11 | /workspace/coverage/default/10.prim_present_test.2054896489 | Jul 09 05:49:08 PM PDT 24 | Jul 09 05:50:06 PM PDT 24 | 8043260000 ps | ||
| T12 | /workspace/coverage/default/46.prim_present_test.290753125 | Jul 09 05:49:28 PM PDT 24 | Jul 09 05:50:28 PM PDT 24 | 8858560000 ps | ||
| T13 | /workspace/coverage/default/42.prim_present_test.2527519670 | Jul 09 05:49:16 PM PDT 24 | Jul 09 05:49:41 PM PDT 24 | 4033720000 ps | ||
| T14 | /workspace/coverage/default/34.prim_present_test.1559509623 | Jul 09 05:49:09 PM PDT 24 | Jul 09 05:50:45 PM PDT 24 | 13256220000 ps | ||
| T15 | /workspace/coverage/default/48.prim_present_test.142706438 | Jul 09 05:49:27 PM PDT 24 | Jul 09 05:50:26 PM PDT 24 | 10150020000 ps | ||
| T16 | /workspace/coverage/default/8.prim_present_test.678498997 | Jul 09 05:49:23 PM PDT 24 | Jul 09 05:49:44 PM PDT 24 | 3519740000 ps | ||
| T17 | /workspace/coverage/default/5.prim_present_test.1938809420 | Jul 09 05:49:14 PM PDT 24 | Jul 09 05:50:23 PM PDT 24 | 12116040000 ps | ||
| T18 | /workspace/coverage/default/14.prim_present_test.2175198309 | Jul 09 05:49:13 PM PDT 24 | Jul 09 05:50:24 PM PDT 24 | 10643540000 ps | ||
| T19 | /workspace/coverage/default/40.prim_present_test.2197409596 | Jul 09 05:49:25 PM PDT 24 | Jul 09 05:50:41 PM PDT 24 | 12754020000 ps | ||
| T20 | /workspace/coverage/default/18.prim_present_test.2645350190 | Jul 09 05:49:28 PM PDT 24 | Jul 09 05:49:48 PM PDT 24 | 3277940000 ps | ||
| T21 | /workspace/coverage/default/37.prim_present_test.685519493 | Jul 09 05:49:28 PM PDT 24 | Jul 09 05:50:52 PM PDT 24 | 13886140000 ps | ||
| T22 | /workspace/coverage/default/3.prim_present_test.2499491604 | Jul 09 05:49:33 PM PDT 24 | Jul 09 05:50:29 PM PDT 24 | 9984480000 ps | ||
| T23 | /workspace/coverage/default/41.prim_present_test.3442192948 | Jul 09 05:49:22 PM PDT 24 | Jul 09 05:50:24 PM PDT 24 | 9752600000 ps | ||
| T24 | /workspace/coverage/default/43.prim_present_test.891369795 | Jul 09 05:49:29 PM PDT 24 | Jul 09 05:50:47 PM PDT 24 | 12479980000 ps | ||
| T25 | /workspace/coverage/default/28.prim_present_test.992945598 | Jul 09 05:49:22 PM PDT 24 | Jul 09 05:50:08 PM PDT 24 | 6109480000 ps | ||
| T26 | /workspace/coverage/default/30.prim_present_test.347376140 | Jul 09 05:49:23 PM PDT 24 | Jul 09 05:49:39 PM PDT 24 | 3114260000 ps | ||
| T27 | /workspace/coverage/default/27.prim_present_test.863343269 | Jul 09 05:49:19 PM PDT 24 | Jul 09 05:50:48 PM PDT 24 | 14534040000 ps | ||
| T28 | /workspace/coverage/default/38.prim_present_test.3371133025 | Jul 09 05:49:18 PM PDT 24 | Jul 09 05:50:51 PM PDT 24 | 12971020000 ps | ||
| T29 | /workspace/coverage/default/21.prim_present_test.385730930 | Jul 09 05:49:14 PM PDT 24 | Jul 09 05:50:24 PM PDT 24 | 10429640000 ps | ||
| T30 | /workspace/coverage/default/31.prim_present_test.403486229 | Jul 09 05:49:12 PM PDT 24 | Jul 09 05:50:46 PM PDT 24 | 14335640000 ps | ||
| T31 | /workspace/coverage/default/23.prim_present_test.1947640001 | Jul 09 05:49:12 PM PDT 24 | Jul 09 05:50:24 PM PDT 24 | 10451340000 ps | ||
| T32 | /workspace/coverage/default/29.prim_present_test.1557524866 | Jul 09 05:49:22 PM PDT 24 | Jul 09 05:50:04 PM PDT 24 | 6275640000 ps | ||
| T33 | /workspace/coverage/default/49.prim_present_test.344795718 | Jul 09 05:49:16 PM PDT 24 | Jul 09 05:49:49 PM PDT 24 | 6550920000 ps | ||
| T34 | /workspace/coverage/default/47.prim_present_test.2121208794 | Jul 09 05:49:24 PM PDT 24 | Jul 09 05:50:22 PM PDT 24 | 9843740000 ps | ||
| T35 | /workspace/coverage/default/17.prim_present_test.804753619 | Jul 09 05:49:05 PM PDT 24 | Jul 09 05:50:40 PM PDT 24 | 14312080000 ps | ||
| T36 | /workspace/coverage/default/11.prim_present_test.1107394656 | Jul 09 05:49:20 PM PDT 24 | Jul 09 05:50:40 PM PDT 24 | 10795440000 ps | ||
| T37 | /workspace/coverage/default/12.prim_present_test.3470135354 | Jul 09 05:49:30 PM PDT 24 | Jul 09 05:50:33 PM PDT 24 | 9752600000 ps | ||
| T38 | /workspace/coverage/default/0.prim_present_test.3187128546 | Jul 09 05:48:53 PM PDT 24 | Jul 09 05:49:24 PM PDT 24 | 4426800000 ps | ||
| T39 | /workspace/coverage/default/9.prim_present_test.408337885 | Jul 09 05:49:20 PM PDT 24 | Jul 09 05:49:48 PM PDT 24 | 5664940000 ps | ||
| T40 | /workspace/coverage/default/13.prim_present_test.3833217606 | Jul 09 05:49:20 PM PDT 24 | Jul 09 05:49:56 PM PDT 24 | 5304720000 ps | ||
| T41 | /workspace/coverage/default/19.prim_present_test.791957641 | Jul 09 05:49:17 PM PDT 24 | Jul 09 05:51:03 PM PDT 24 | 13917760000 ps | ||
| T42 | /workspace/coverage/default/44.prim_present_test.3844713520 | Jul 09 05:49:30 PM PDT 24 | Jul 09 05:49:49 PM PDT 24 | 3186180000 ps | ||
| T43 | /workspace/coverage/default/35.prim_present_test.1028546553 | Jul 09 05:49:29 PM PDT 24 | Jul 09 05:49:57 PM PDT 24 | 4694020000 ps | ||
| T44 | /workspace/coverage/default/36.prim_present_test.2806088605 | Jul 09 05:49:25 PM PDT 24 | Jul 09 05:50:07 PM PDT 24 | 7802080000 ps | ||
| T45 | /workspace/coverage/default/22.prim_present_test.1925375824 | Jul 09 05:49:26 PM PDT 24 | Jul 09 05:49:48 PM PDT 24 | 3455880000 ps | ||
| T46 | /workspace/coverage/default/4.prim_present_test.2350642393 | Jul 09 05:49:08 PM PDT 24 | Jul 09 05:49:53 PM PDT 24 | 7934760000 ps | ||
| T47 | /workspace/coverage/default/32.prim_present_test.2986263450 | Jul 09 05:49:17 PM PDT 24 | Jul 09 05:49:39 PM PDT 24 | 3701400000 ps | ||
| T48 | /workspace/coverage/default/6.prim_present_test.2270422829 | Jul 09 05:49:24 PM PDT 24 | Jul 09 05:49:47 PM PDT 24 | 3786340000 ps | ||
| T49 | /workspace/coverage/default/26.prim_present_test.1086425873 | Jul 09 05:49:11 PM PDT 24 | Jul 09 05:50:11 PM PDT 24 | 8716580000 ps | ||
| T50 | /workspace/coverage/default/24.prim_present_test.1508222316 | Jul 09 05:49:08 PM PDT 24 | Jul 09 05:50:49 PM PDT 24 | 13533360000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.116553681 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12996440000 ps |
| CPU time | 45.77 seconds |
| Started | Jul 09 05:49:09 PM PDT 24 |
| Finished | Jul 09 05:50:35 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-e0c324fa-665a-4c99-b43b-76c8e7d7bde2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=116553681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.116553681 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3187128546 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4426800000 ps |
| CPU time | 14.89 seconds |
| Started | Jul 09 05:48:53 PM PDT 24 |
| Finished | Jul 09 05:49:24 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c7b6c61d-a44b-4e59-9ba0-d03ec534febf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3187128546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3187128546 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2054896489 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8043260000 ps |
| CPU time | 30.38 seconds |
| Started | Jul 09 05:49:08 PM PDT 24 |
| Finished | Jul 09 05:50:06 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-14599882-e6b8-489c-951c-678755e18b0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054896489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2054896489 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1107394656 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10795440000 ps |
| CPU time | 42.27 seconds |
| Started | Jul 09 05:49:20 PM PDT 24 |
| Finished | Jul 09 05:50:40 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-26f3559c-ff79-4178-a3da-54406a867697 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107394656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1107394656 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3470135354 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9752600000 ps |
| CPU time | 33.63 seconds |
| Started | Jul 09 05:49:30 PM PDT 24 |
| Finished | Jul 09 05:50:33 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-d969ea23-ab2c-4a73-9855-68717291f608 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470135354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3470135354 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3833217606 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5304720000 ps |
| CPU time | 18.55 seconds |
| Started | Jul 09 05:49:20 PM PDT 24 |
| Finished | Jul 09 05:49:56 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-3f3a1d69-1008-4f16-94e5-8d40850c326f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833217606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3833217606 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2175198309 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10643540000 ps |
| CPU time | 37.08 seconds |
| Started | Jul 09 05:49:13 PM PDT 24 |
| Finished | Jul 09 05:50:24 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-45559792-ad9a-4a61-9083-9988568f3690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175198309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2175198309 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.668440488 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4743620000 ps |
| CPU time | 18.04 seconds |
| Started | Jul 09 05:49:18 PM PDT 24 |
| Finished | Jul 09 05:49:52 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-833e7704-a88c-40e4-a4d1-457e4db932d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668440488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.668440488 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3137457995 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4240180000 ps |
| CPU time | 13.35 seconds |
| Started | Jul 09 05:49:21 PM PDT 24 |
| Finished | Jul 09 05:49:46 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-74e047d5-8390-4faa-9052-7bc1ee819d22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137457995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3137457995 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.804753619 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14312080000 ps |
| CPU time | 50.27 seconds |
| Started | Jul 09 05:49:05 PM PDT 24 |
| Finished | Jul 09 05:50:40 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-abff633e-5332-41d6-aefe-ed885b626704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804753619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.804753619 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2645350190 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3277940000 ps |
| CPU time | 10.59 seconds |
| Started | Jul 09 05:49:28 PM PDT 24 |
| Finished | Jul 09 05:49:48 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-29e0ec5f-4ce6-4408-945d-d9c9cf0bceee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645350190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2645350190 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.791957641 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13917760000 ps |
| CPU time | 55.52 seconds |
| Started | Jul 09 05:49:17 PM PDT 24 |
| Finished | Jul 09 05:51:03 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-9e807a2d-2695-4eaa-9433-ccddd85c3dd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791957641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.791957641 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1188302366 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4688440000 ps |
| CPU time | 17.38 seconds |
| Started | Jul 09 05:49:09 PM PDT 24 |
| Finished | Jul 09 05:49:43 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-a16f73a4-b719-40de-8f5b-f41421e95a9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188302366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1188302366 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2048970723 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5636420000 ps |
| CPU time | 20.46 seconds |
| Started | Jul 09 05:49:17 PM PDT 24 |
| Finished | Jul 09 05:49:56 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-7ee0f636-62c4-4ad6-aea1-3e7fb7ab1a8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048970723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2048970723 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.385730930 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10429640000 ps |
| CPU time | 36.84 seconds |
| Started | Jul 09 05:49:14 PM PDT 24 |
| Finished | Jul 09 05:50:24 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-fcd1cc50-1c8c-4a3b-bf78-6055cf371196 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385730930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.385730930 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1925375824 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3455880000 ps |
| CPU time | 11.45 seconds |
| Started | Jul 09 05:49:26 PM PDT 24 |
| Finished | Jul 09 05:49:48 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-21746978-a0bd-4cdd-bd44-e7c0185fbeeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925375824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1925375824 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1947640001 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10451340000 ps |
| CPU time | 38.64 seconds |
| Started | Jul 09 05:49:12 PM PDT 24 |
| Finished | Jul 09 05:50:24 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-69172adf-b6af-4f70-b2c7-10ac6103b35b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947640001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1947640001 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1508222316 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13533360000 ps |
| CPU time | 52.51 seconds |
| Started | Jul 09 05:49:08 PM PDT 24 |
| Finished | Jul 09 05:50:49 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-f7845e72-49f3-4fb1-b53d-cb470ae1b194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1508222316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1508222316 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3362730164 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15133580000 ps |
| CPU time | 51.73 seconds |
| Started | Jul 09 05:49:17 PM PDT 24 |
| Finished | Jul 09 05:50:55 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-8f921bd1-81c2-4c64-b31e-f62a7a9d7fe4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362730164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3362730164 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1086425873 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8716580000 ps |
| CPU time | 31.81 seconds |
| Started | Jul 09 05:49:11 PM PDT 24 |
| Finished | Jul 09 05:50:11 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-616cbb0a-85f6-40dc-b1d9-0ae45c67e9da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086425873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1086425873 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.863343269 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14534040000 ps |
| CPU time | 47.27 seconds |
| Started | Jul 09 05:49:19 PM PDT 24 |
| Finished | Jul 09 05:50:48 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-f1891504-b419-4fcb-b430-ac2bd4a310b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863343269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.863343269 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.992945598 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6109480000 ps |
| CPU time | 23.74 seconds |
| Started | Jul 09 05:49:22 PM PDT 24 |
| Finished | Jul 09 05:50:08 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-bce694dd-817e-4924-b1ec-5140ceb400f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992945598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.992945598 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1557524866 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6275640000 ps |
| CPU time | 21.89 seconds |
| Started | Jul 09 05:49:22 PM PDT 24 |
| Finished | Jul 09 05:50:04 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-39057a99-e354-4450-8c9d-fa7349a1b751 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1557524866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1557524866 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2499491604 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9984480000 ps |
| CPU time | 30.2 seconds |
| Started | Jul 09 05:49:33 PM PDT 24 |
| Finished | Jul 09 05:50:29 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-820a649d-cf8d-41df-bc8e-42f29088e292 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499491604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2499491604 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.347376140 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3114260000 ps |
| CPU time | 8.74 seconds |
| Started | Jul 09 05:49:23 PM PDT 24 |
| Finished | Jul 09 05:49:39 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-42b499b2-b723-427e-ae34-ceb6d81f7332 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347376140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.347376140 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.403486229 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14335640000 ps |
| CPU time | 49.63 seconds |
| Started | Jul 09 05:49:12 PM PDT 24 |
| Finished | Jul 09 05:50:46 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-d25a5d76-fea2-4f46-8d8c-4011386d0ab9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403486229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.403486229 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2986263450 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3701400000 ps |
| CPU time | 11.73 seconds |
| Started | Jul 09 05:49:17 PM PDT 24 |
| Finished | Jul 09 05:49:39 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-4b1f3896-dd58-4132-b751-fbdfd0db7a21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986263450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2986263450 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1880019023 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15452260000 ps |
| CPU time | 42.7 seconds |
| Started | Jul 09 05:49:20 PM PDT 24 |
| Finished | Jul 09 05:50:40 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-0ba317d6-9111-4126-ad26-27e00ad28f37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880019023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1880019023 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1559509623 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13256220000 ps |
| CPU time | 50.63 seconds |
| Started | Jul 09 05:49:09 PM PDT 24 |
| Finished | Jul 09 05:50:45 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-bb96d5fa-ba3d-44fe-bbee-1cf186ce72db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1559509623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1559509623 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1028546553 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4694020000 ps |
| CPU time | 14.64 seconds |
| Started | Jul 09 05:49:29 PM PDT 24 |
| Finished | Jul 09 05:49:57 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-4e480fbd-4caf-4cae-9706-01a0616a7130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028546553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1028546553 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2806088605 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7802080000 ps |
| CPU time | 22.38 seconds |
| Started | Jul 09 05:49:25 PM PDT 24 |
| Finished | Jul 09 05:50:07 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-f635d54d-924a-48d7-a232-e5de3b0e35dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806088605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2806088605 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.685519493 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13886140000 ps |
| CPU time | 43.97 seconds |
| Started | Jul 09 05:49:28 PM PDT 24 |
| Finished | Jul 09 05:50:52 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-6fe9d17b-75f7-46ae-b28c-149af4725d3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=685519493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.685519493 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3371133025 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12971020000 ps |
| CPU time | 48.78 seconds |
| Started | Jul 09 05:49:18 PM PDT 24 |
| Finished | Jul 09 05:50:51 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-eba693ea-84a1-45c6-8a3f-caef8504f510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371133025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3371133025 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3223820623 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6550920000 ps |
| CPU time | 21.47 seconds |
| Started | Jul 09 05:49:25 PM PDT 24 |
| Finished | Jul 09 05:50:05 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-526c80b4-41c5-4284-bda6-c20a3595b452 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223820623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3223820623 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2350642393 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7934760000 ps |
| CPU time | 24.05 seconds |
| Started | Jul 09 05:49:08 PM PDT 24 |
| Finished | Jul 09 05:49:53 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-0d8f74c7-cd8e-45b2-98c2-fd9452545391 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350642393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2350642393 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2197409596 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12754020000 ps |
| CPU time | 40.93 seconds |
| Started | Jul 09 05:49:25 PM PDT 24 |
| Finished | Jul 09 05:50:41 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-6710fca7-8db5-43e5-b2f6-f065873c58a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197409596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2197409596 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3442192948 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9752600000 ps |
| CPU time | 33.01 seconds |
| Started | Jul 09 05:49:22 PM PDT 24 |
| Finished | Jul 09 05:50:24 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-2113ff4e-f02f-4f94-952b-090452bb802c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442192948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3442192948 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2527519670 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4033720000 ps |
| CPU time | 13.11 seconds |
| Started | Jul 09 05:49:16 PM PDT 24 |
| Finished | Jul 09 05:49:41 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-d89b59dd-6d96-47aa-b40d-b81744456b73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527519670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2527519670 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.891369795 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12479980000 ps |
| CPU time | 41.06 seconds |
| Started | Jul 09 05:49:29 PM PDT 24 |
| Finished | Jul 09 05:50:47 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-3d3ec700-6b3b-4882-9c90-85fe731f2113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891369795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.891369795 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3844713520 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3186180000 ps |
| CPU time | 10.02 seconds |
| Started | Jul 09 05:49:30 PM PDT 24 |
| Finished | Jul 09 05:49:49 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-87651083-9d67-4c56-8942-e81c40b55e96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844713520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3844713520 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1941714832 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12845780000 ps |
| CPU time | 42.48 seconds |
| Started | Jul 09 05:49:24 PM PDT 24 |
| Finished | Jul 09 05:50:44 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-2e76005f-6560-4acb-a2f2-8f786e425aa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941714832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1941714832 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.290753125 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8858560000 ps |
| CPU time | 30.82 seconds |
| Started | Jul 09 05:49:28 PM PDT 24 |
| Finished | Jul 09 05:50:28 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-8cf64777-c562-4555-b6c7-f23e93d98a80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290753125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.290753125 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2121208794 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9843740000 ps |
| CPU time | 31.13 seconds |
| Started | Jul 09 05:49:24 PM PDT 24 |
| Finished | Jul 09 05:50:22 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-127dd700-ce2f-44f5-917b-32fd8c571196 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121208794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2121208794 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.142706438 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10150020000 ps |
| CPU time | 31.45 seconds |
| Started | Jul 09 05:49:27 PM PDT 24 |
| Finished | Jul 09 05:50:26 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-8daae123-8d0b-4d08-81ef-a0da438e32e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142706438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.142706438 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.344795718 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6550920000 ps |
| CPU time | 17.88 seconds |
| Started | Jul 09 05:49:16 PM PDT 24 |
| Finished | Jul 09 05:49:49 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-6d8bb945-2536-40f2-953c-d1ca59338669 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=344795718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.344795718 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1938809420 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12116040000 ps |
| CPU time | 37.11 seconds |
| Started | Jul 09 05:49:14 PM PDT 24 |
| Finished | Jul 09 05:50:23 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-efe141d8-2df1-4805-ab47-0cfcb32edf5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938809420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1938809420 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2270422829 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3786340000 ps |
| CPU time | 12.55 seconds |
| Started | Jul 09 05:49:24 PM PDT 24 |
| Finished | Jul 09 05:49:47 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-2f67a98f-96a3-42ae-a123-5c0c3d204c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270422829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2270422829 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2300177446 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7016540000 ps |
| CPU time | 20.93 seconds |
| Started | Jul 09 05:49:32 PM PDT 24 |
| Finished | Jul 09 05:50:11 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-a64ea373-d367-4190-96db-f045e42522bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300177446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2300177446 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.678498997 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3519740000 ps |
| CPU time | 11.48 seconds |
| Started | Jul 09 05:49:23 PM PDT 24 |
| Finished | Jul 09 05:49:44 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-0655f267-e9f8-4971-903d-88852fb01f45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=678498997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.678498997 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.408337885 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5664940000 ps |
| CPU time | 15.36 seconds |
| Started | Jul 09 05:49:20 PM PDT 24 |
| Finished | Jul 09 05:49:48 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-96fbb104-ac87-4886-9167-10423d99d438 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408337885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.408337885 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |