| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.3793526028 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3861807416 |
| /workspace/coverage/default/10.prim_present_test.1646472292 |
| /workspace/coverage/default/11.prim_present_test.2472621086 |
| /workspace/coverage/default/12.prim_present_test.2740843281 |
| /workspace/coverage/default/13.prim_present_test.3921456434 |
| /workspace/coverage/default/14.prim_present_test.3744989080 |
| /workspace/coverage/default/15.prim_present_test.2828989613 |
| /workspace/coverage/default/16.prim_present_test.2244307849 |
| /workspace/coverage/default/17.prim_present_test.1926500701 |
| /workspace/coverage/default/18.prim_present_test.572770023 |
| /workspace/coverage/default/19.prim_present_test.1046265209 |
| /workspace/coverage/default/2.prim_present_test.3719764964 |
| /workspace/coverage/default/20.prim_present_test.761585804 |
| /workspace/coverage/default/21.prim_present_test.4220811779 |
| /workspace/coverage/default/22.prim_present_test.1863169024 |
| /workspace/coverage/default/23.prim_present_test.2156254176 |
| /workspace/coverage/default/24.prim_present_test.1507887076 |
| /workspace/coverage/default/25.prim_present_test.1413269105 |
| /workspace/coverage/default/26.prim_present_test.787724078 |
| /workspace/coverage/default/27.prim_present_test.4112405307 |
| /workspace/coverage/default/28.prim_present_test.3047868863 |
| /workspace/coverage/default/29.prim_present_test.3557250377 |
| /workspace/coverage/default/3.prim_present_test.994167797 |
| /workspace/coverage/default/30.prim_present_test.2353937039 |
| /workspace/coverage/default/31.prim_present_test.579135468 |
| /workspace/coverage/default/32.prim_present_test.4092671644 |
| /workspace/coverage/default/33.prim_present_test.1851777124 |
| /workspace/coverage/default/34.prim_present_test.578262415 |
| /workspace/coverage/default/35.prim_present_test.4035471771 |
| /workspace/coverage/default/36.prim_present_test.75367342 |
| /workspace/coverage/default/37.prim_present_test.2453853252 |
| /workspace/coverage/default/38.prim_present_test.1389185196 |
| /workspace/coverage/default/39.prim_present_test.4288643525 |
| /workspace/coverage/default/4.prim_present_test.3071053059 |
| /workspace/coverage/default/40.prim_present_test.174141753 |
| /workspace/coverage/default/41.prim_present_test.3362233723 |
| /workspace/coverage/default/42.prim_present_test.3746224833 |
| /workspace/coverage/default/43.prim_present_test.1516625761 |
| /workspace/coverage/default/44.prim_present_test.3745229736 |
| /workspace/coverage/default/45.prim_present_test.3034647022 |
| /workspace/coverage/default/46.prim_present_test.3081270804 |
| /workspace/coverage/default/47.prim_present_test.3078381495 |
| /workspace/coverage/default/48.prim_present_test.1295389785 |
| /workspace/coverage/default/49.prim_present_test.113046376 |
| /workspace/coverage/default/5.prim_present_test.2840002209 |
| /workspace/coverage/default/6.prim_present_test.1703459328 |
| /workspace/coverage/default/7.prim_present_test.211191948 |
| /workspace/coverage/default/8.prim_present_test.10793054 |
| /workspace/coverage/default/9.prim_present_test.2597995146 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/23.prim_present_test.2156254176 | Jul 10 06:01:21 PM PDT 24 | Jul 10 06:02:33 PM PDT 24 | 10166140000 ps | ||
| T2 | /workspace/coverage/default/41.prim_present_test.3362233723 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:02:36 PM PDT 24 | 10023540000 ps | ||
| T3 | /workspace/coverage/default/1.prim_present_test.3793526028 | Jul 10 06:01:24 PM PDT 24 | Jul 10 06:03:32 PM PDT 24 | 14987260000 ps | ||
| T4 | /workspace/coverage/default/33.prim_present_test.1851777124 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:02:50 PM PDT 24 | 10034700000 ps | ||
| T5 | /workspace/coverage/default/39.prim_present_test.4288643525 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:01:57 PM PDT 24 | 4431140000 ps | ||
| T6 | /workspace/coverage/default/37.prim_present_test.2453853252 | Jul 10 06:01:23 PM PDT 24 | Jul 10 06:02:18 PM PDT 24 | 6793340000 ps | ||
| T7 | /workspace/coverage/default/29.prim_present_test.3557250377 | Jul 10 06:01:25 PM PDT 24 | Jul 10 06:03:10 PM PDT 24 | 15105680000 ps | ||
| T8 | /workspace/coverage/default/4.prim_present_test.3071053059 | Jul 10 06:01:23 PM PDT 24 | Jul 10 06:02:13 PM PDT 24 | 5929060000 ps | ||
| T9 | /workspace/coverage/default/22.prim_present_test.1863169024 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:02:06 PM PDT 24 | 6023300000 ps | ||
| T10 | /workspace/coverage/default/35.prim_present_test.4035471771 | Jul 10 06:01:23 PM PDT 24 | Jul 10 06:02:07 PM PDT 24 | 4666740000 ps | ||
| T11 | /workspace/coverage/default/15.prim_present_test.2828989613 | Jul 10 06:01:23 PM PDT 24 | Jul 10 06:02:06 PM PDT 24 | 6464120000 ps | ||
| T12 | /workspace/coverage/default/49.prim_present_test.113046376 | Jul 10 06:01:28 PM PDT 24 | Jul 10 06:02:36 PM PDT 24 | 8962720000 ps | ||
| T13 | /workspace/coverage/default/44.prim_present_test.3745229736 | Jul 10 06:01:25 PM PDT 24 | Jul 10 06:02:40 PM PDT 24 | 12334900000 ps | ||
| T14 | /workspace/coverage/default/30.prim_present_test.2353937039 | Jul 10 06:01:23 PM PDT 24 | Jul 10 06:01:58 PM PDT 24 | 4972400000 ps | ||
| T15 | /workspace/coverage/default/25.prim_present_test.1413269105 | Jul 10 06:01:26 PM PDT 24 | Jul 10 06:02:38 PM PDT 24 | 9121440000 ps | ||
| T16 | /workspace/coverage/default/8.prim_present_test.10793054 | Jul 10 06:01:24 PM PDT 24 | Jul 10 06:02:20 PM PDT 24 | 5965020000 ps | ||
| T17 | /workspace/coverage/default/10.prim_present_test.1646472292 | Jul 10 06:01:18 PM PDT 24 | Jul 10 06:02:26 PM PDT 24 | 8763700000 ps | ||
| T18 | /workspace/coverage/default/11.prim_present_test.2472621086 | Jul 10 06:01:23 PM PDT 24 | Jul 10 06:03:17 PM PDT 24 | 13095640000 ps | ||
| T19 | /workspace/coverage/default/47.prim_present_test.3078381495 | Jul 10 06:01:27 PM PDT 24 | Jul 10 06:01:58 PM PDT 24 | 4008300000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.2740843281 | Jul 10 06:01:18 PM PDT 24 | Jul 10 06:03:01 PM PDT 24 | 11834560000 ps | ||
| T21 | /workspace/coverage/default/9.prim_present_test.2597995146 | Jul 10 06:01:17 PM PDT 24 | Jul 10 06:02:12 PM PDT 24 | 7524320000 ps | ||
| T22 | /workspace/coverage/default/0.prim_present_test.3861807416 | Jul 10 06:01:18 PM PDT 24 | Jul 10 06:02:10 PM PDT 24 | 6628420000 ps | ||
| T23 | /workspace/coverage/default/16.prim_present_test.2244307849 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:02:06 PM PDT 24 | 5868300000 ps | ||
| T24 | /workspace/coverage/default/5.prim_present_test.2840002209 | Jul 10 06:01:24 PM PDT 24 | Jul 10 06:03:06 PM PDT 24 | 11664680000 ps | ||
| T25 | /workspace/coverage/default/2.prim_present_test.3719764964 | Jul 10 06:01:24 PM PDT 24 | Jul 10 06:02:59 PM PDT 24 | 10643540000 ps | ||
| T26 | /workspace/coverage/default/13.prim_present_test.3921456434 | Jul 10 06:01:28 PM PDT 24 | Jul 10 06:02:41 PM PDT 24 | 9112140000 ps | ||
| T27 | /workspace/coverage/default/34.prim_present_test.578262415 | Jul 10 06:01:26 PM PDT 24 | Jul 10 06:03:03 PM PDT 24 | 12259880000 ps | ||
| T28 | /workspace/coverage/default/42.prim_present_test.3746224833 | Jul 10 06:01:24 PM PDT 24 | Jul 10 06:02:11 PM PDT 24 | 6599900000 ps | ||
| T29 | /workspace/coverage/default/36.prim_present_test.75367342 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:02:32 PM PDT 24 | 9613100000 ps | ||
| T30 | /workspace/coverage/default/46.prim_present_test.3081270804 | Jul 10 06:01:26 PM PDT 24 | Jul 10 06:02:34 PM PDT 24 | 10052060000 ps | ||
| T31 | /workspace/coverage/default/18.prim_present_test.572770023 | Jul 10 06:01:23 PM PDT 24 | Jul 10 06:02:42 PM PDT 24 | 12070160000 ps | ||
| T32 | /workspace/coverage/default/26.prim_present_test.787724078 | Jul 10 06:01:21 PM PDT 24 | Jul 10 06:02:51 PM PDT 24 | 12632500000 ps | ||
| T33 | /workspace/coverage/default/21.prim_present_test.4220811779 | Jul 10 06:01:21 PM PDT 24 | Jul 10 06:02:02 PM PDT 24 | 4576220000 ps | ||
| T34 | /workspace/coverage/default/6.prim_present_test.1703459328 | Jul 10 06:01:17 PM PDT 24 | Jul 10 06:02:21 PM PDT 24 | 8135020000 ps | ||
| T35 | /workspace/coverage/default/32.prim_present_test.4092671644 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:01:57 PM PDT 24 | 4550800000 ps | ||
| T36 | /workspace/coverage/default/19.prim_present_test.1046265209 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:02:56 PM PDT 24 | 12151380000 ps | ||
| T37 | /workspace/coverage/default/31.prim_present_test.579135468 | Jul 10 06:01:23 PM PDT 24 | Jul 10 06:02:38 PM PDT 24 | 10554260000 ps | ||
| T38 | /workspace/coverage/default/38.prim_present_test.1389185196 | Jul 10 06:01:25 PM PDT 24 | Jul 10 06:01:50 PM PDT 24 | 3142160000 ps | ||
| T39 | /workspace/coverage/default/3.prim_present_test.994167797 | Jul 10 06:01:16 PM PDT 24 | Jul 10 06:01:52 PM PDT 24 | 4447260000 ps | ||
| T40 | /workspace/coverage/default/7.prim_present_test.211191948 | Jul 10 06:01:19 PM PDT 24 | Jul 10 06:02:45 PM PDT 24 | 12315680000 ps | ||
| T41 | /workspace/coverage/default/28.prim_present_test.3047868863 | Jul 10 06:01:20 PM PDT 24 | Jul 10 06:02:38 PM PDT 24 | 8842440000 ps | ||
| T42 | /workspace/coverage/default/14.prim_present_test.3744989080 | Jul 10 06:01:21 PM PDT 24 | Jul 10 06:02:53 PM PDT 24 | 13226460000 ps | ||
| T43 | /workspace/coverage/default/45.prim_present_test.3034647022 | Jul 10 06:01:31 PM PDT 24 | Jul 10 06:02:56 PM PDT 24 | 12610180000 ps | ||
| T44 | /workspace/coverage/default/27.prim_present_test.4112405307 | Jul 10 06:01:21 PM PDT 24 | Jul 10 06:02:56 PM PDT 24 | 12656680000 ps | ||
| T45 | /workspace/coverage/default/43.prim_present_test.1516625761 | Jul 10 06:01:25 PM PDT 24 | Jul 10 06:01:52 PM PDT 24 | 3752240000 ps | ||
| T46 | /workspace/coverage/default/17.prim_present_test.1926500701 | Jul 10 06:01:22 PM PDT 24 | Jul 10 06:01:50 PM PDT 24 | 3860120000 ps | ||
| T47 | /workspace/coverage/default/40.prim_present_test.174141753 | Jul 10 06:01:26 PM PDT 24 | Jul 10 06:02:14 PM PDT 24 | 5748020000 ps | ||
| T48 | /workspace/coverage/default/48.prim_present_test.1295389785 | Jul 10 06:01:26 PM PDT 24 | Jul 10 06:03:01 PM PDT 24 | 15465280000 ps | ||
| T49 | /workspace/coverage/default/24.prim_present_test.1507887076 | Jul 10 06:01:24 PM PDT 24 | Jul 10 06:02:33 PM PDT 24 | 9403540000 ps | ||
| T50 | /workspace/coverage/default/20.prim_present_test.761585804 | Jul 10 06:01:21 PM PDT 24 | Jul 10 06:01:47 PM PDT 24 | 3696440000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.3793526028 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 14987260000 ps |
| CPU time | 61.38 seconds |
| Started | Jul 10 06:01:24 PM PDT 24 |
| Finished | Jul 10 06:03:32 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-d49b852b-78e2-46ca-b844-a89fd6b04b3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3793526028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3793526028 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3861807416 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6628420000 ps |
| CPU time | 26.07 seconds |
| Started | Jul 10 06:01:18 PM PDT 24 |
| Finished | Jul 10 06:02:10 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-8fd4a112-84df-42ab-ac01-73615bfec189 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861807416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3861807416 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1646472292 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8763700000 ps |
| CPU time | 34.39 seconds |
| Started | Jul 10 06:01:18 PM PDT 24 |
| Finished | Jul 10 06:02:26 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-b26dcf25-8b64-46c3-b5a7-9494788737e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646472292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1646472292 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2472621086 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13095640000 ps |
| CPU time | 54.12 seconds |
| Started | Jul 10 06:01:23 PM PDT 24 |
| Finished | Jul 10 06:03:17 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-aad6a7a5-1c4b-4d64-b379-b813aa24fb9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2472621086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2472621086 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2740843281 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11834560000 ps |
| CPU time | 52.23 seconds |
| Started | Jul 10 06:01:18 PM PDT 24 |
| Finished | Jul 10 06:03:01 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-228ac7bd-98a0-4044-a0a3-62097de678bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2740843281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2740843281 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3921456434 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9112140000 ps |
| CPU time | 36.59 seconds |
| Started | Jul 10 06:01:28 PM PDT 24 |
| Finished | Jul 10 06:02:41 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-201ea89e-da5a-4945-ac07-3143d5132454 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921456434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3921456434 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3744989080 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13226460000 ps |
| CPU time | 48.29 seconds |
| Started | Jul 10 06:01:21 PM PDT 24 |
| Finished | Jul 10 06:02:53 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-7fcbef54-b23b-42a7-9f79-c547eabdc558 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744989080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3744989080 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2828989613 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6464120000 ps |
| CPU time | 22.13 seconds |
| Started | Jul 10 06:01:23 PM PDT 24 |
| Finished | Jul 10 06:02:06 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-6862c9ae-7c38-47d3-8988-a05802dece76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828989613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2828989613 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2244307849 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5868300000 ps |
| CPU time | 22.18 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:02:06 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-d77a9ec6-768a-4489-94bf-1ed6c1dc7d9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244307849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2244307849 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1926500701 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3860120000 ps |
| CPU time | 13.75 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:01:50 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-ee9bfe2f-370a-4553-a134-2f40b056988a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926500701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1926500701 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.572770023 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12070160000 ps |
| CPU time | 40.85 seconds |
| Started | Jul 10 06:01:23 PM PDT 24 |
| Finished | Jul 10 06:02:42 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-a1091359-ef8d-45f0-ab55-0d527b434976 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572770023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.572770023 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1046265209 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12151380000 ps |
| CPU time | 47.9 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:02:56 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-12874486-671a-408e-8506-178e154d36a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046265209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1046265209 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3719764964 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10643540000 ps |
| CPU time | 44.63 seconds |
| Started | Jul 10 06:01:24 PM PDT 24 |
| Finished | Jul 10 06:02:59 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-150a46ac-8619-429c-a48d-5a3c49c5b131 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719764964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3719764964 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.761585804 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3696440000 ps |
| CPU time | 13.78 seconds |
| Started | Jul 10 06:01:21 PM PDT 24 |
| Finished | Jul 10 06:01:47 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-86a29c86-6ba4-4730-84f7-edce41b9070f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761585804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.761585804 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4220811779 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4576220000 ps |
| CPU time | 20.17 seconds |
| Started | Jul 10 06:01:21 PM PDT 24 |
| Finished | Jul 10 06:02:02 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-8cd7325b-5603-4dec-ba7b-0bdfa2ba6515 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220811779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4220811779 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1863169024 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6023300000 ps |
| CPU time | 22.58 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:02:06 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-1950335c-9702-410a-83c8-4cd0811d5c25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863169024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1863169024 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2156254176 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10166140000 ps |
| CPU time | 37.2 seconds |
| Started | Jul 10 06:01:21 PM PDT 24 |
| Finished | Jul 10 06:02:33 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-45a37c2c-63a2-4563-b158-d8531a48d78b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156254176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2156254176 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1507887076 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9403540000 ps |
| CPU time | 35.33 seconds |
| Started | Jul 10 06:01:24 PM PDT 24 |
| Finished | Jul 10 06:02:33 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-96627923-290c-497e-adc3-e5c50e45d777 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507887076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1507887076 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1413269105 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9121440000 ps |
| CPU time | 35.7 seconds |
| Started | Jul 10 06:01:26 PM PDT 24 |
| Finished | Jul 10 06:02:38 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-b309a61b-a347-4083-b7ec-f073ebf9359b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413269105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1413269105 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.787724078 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12632500000 ps |
| CPU time | 47.26 seconds |
| Started | Jul 10 06:01:21 PM PDT 24 |
| Finished | Jul 10 06:02:51 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-91c72b7b-787f-43aa-b023-861d4fbce64a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787724078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.787724078 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.4112405307 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12656680000 ps |
| CPU time | 49.39 seconds |
| Started | Jul 10 06:01:21 PM PDT 24 |
| Finished | Jul 10 06:02:56 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-1a8c6bf3-067f-445d-b5b6-8ea8ceb359e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112405307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.4112405307 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3047868863 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8842440000 ps |
| CPU time | 39.62 seconds |
| Started | Jul 10 06:01:20 PM PDT 24 |
| Finished | Jul 10 06:02:38 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-1c51de04-340c-491c-81ce-6b53abda7927 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047868863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3047868863 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3557250377 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15105680000 ps |
| CPU time | 53.86 seconds |
| Started | Jul 10 06:01:25 PM PDT 24 |
| Finished | Jul 10 06:03:10 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-585a5af0-e6e8-4e9e-aa21-3ababe1bb5e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557250377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3557250377 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.994167797 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4447260000 ps |
| CPU time | 18.49 seconds |
| Started | Jul 10 06:01:16 PM PDT 24 |
| Finished | Jul 10 06:01:52 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-5e12ef11-baa5-4a74-be7a-3a48aff71ff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=994167797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.994167797 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2353937039 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4972400000 ps |
| CPU time | 18.04 seconds |
| Started | Jul 10 06:01:23 PM PDT 24 |
| Finished | Jul 10 06:01:58 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-d6284d73-268b-4d29-a006-54cb1ff54ac1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2353937039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2353937039 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.579135468 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10554260000 ps |
| CPU time | 38.11 seconds |
| Started | Jul 10 06:01:23 PM PDT 24 |
| Finished | Jul 10 06:02:38 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-3cf3bc7b-60ca-4f9f-aa3d-baf76b790903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579135468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.579135468 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4092671644 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4550800000 ps |
| CPU time | 17.16 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:01:57 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-f5db1c8b-5385-4406-bc6b-4fc94908b5a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092671644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4092671644 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1851777124 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10034700000 ps |
| CPU time | 44.5 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:02:50 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-84a8d422-f39b-40db-afbd-a81e4f863070 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851777124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1851777124 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.578262415 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12259880000 ps |
| CPU time | 47.98 seconds |
| Started | Jul 10 06:01:26 PM PDT 24 |
| Finished | Jul 10 06:03:03 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-4eddf181-e766-4baf-8350-8a46fe4bfc75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578262415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.578262415 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4035471771 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4666740000 ps |
| CPU time | 21.86 seconds |
| Started | Jul 10 06:01:23 PM PDT 24 |
| Finished | Jul 10 06:02:07 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-bc9b8fd9-5cc8-4ccc-90f0-a78dc62cc3e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035471771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4035471771 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.75367342 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9613100000 ps |
| CPU time | 35.35 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:02:32 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-c3c131f9-5170-4f31-bbc4-6b95afcba294 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75367342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.75367342 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2453853252 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6793340000 ps |
| CPU time | 27.52 seconds |
| Started | Jul 10 06:01:23 PM PDT 24 |
| Finished | Jul 10 06:02:18 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e0a61cbd-9e80-47be-8424-de5afae758ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453853252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2453853252 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1389185196 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3142160000 ps |
| CPU time | 12.35 seconds |
| Started | Jul 10 06:01:25 PM PDT 24 |
| Finished | Jul 10 06:01:50 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-5b59c778-9a78-4230-ae6d-75c6e99a5f1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389185196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1389185196 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.4288643525 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4431140000 ps |
| CPU time | 17.36 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:01:57 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-2ffc9f14-df6c-4c83-94fc-757ab34609d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288643525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4288643525 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3071053059 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5929060000 ps |
| CPU time | 23.75 seconds |
| Started | Jul 10 06:01:23 PM PDT 24 |
| Finished | Jul 10 06:02:13 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-b533b22e-ce68-4a79-bd22-09e1eae0d4ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071053059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3071053059 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.174141753 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5748020000 ps |
| CPU time | 23.78 seconds |
| Started | Jul 10 06:01:26 PM PDT 24 |
| Finished | Jul 10 06:02:14 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c6057f1b-62a9-4d6c-8606-8f6a22b978ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=174141753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.174141753 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3362233723 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10023540000 ps |
| CPU time | 37.91 seconds |
| Started | Jul 10 06:01:22 PM PDT 24 |
| Finished | Jul 10 06:02:36 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-70faa614-cfb4-4f6e-b51e-96c41facad82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362233723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3362233723 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3746224833 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6599900000 ps |
| CPU time | 24.51 seconds |
| Started | Jul 10 06:01:24 PM PDT 24 |
| Finished | Jul 10 06:02:11 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-9b661d83-c11f-4cec-bdfa-8973cdd70327 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746224833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3746224833 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1516625761 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3752240000 ps |
| CPU time | 13.52 seconds |
| Started | Jul 10 06:01:25 PM PDT 24 |
| Finished | Jul 10 06:01:52 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-11e4d2b9-8422-4de0-b459-8c530359d99a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516625761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1516625761 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3745229736 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12334900000 ps |
| CPU time | 40.46 seconds |
| Started | Jul 10 06:01:25 PM PDT 24 |
| Finished | Jul 10 06:02:40 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-fc2c413a-0ad8-4afa-9d97-b6a54cd3f799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745229736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3745229736 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3034647022 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12610180000 ps |
| CPU time | 44.12 seconds |
| Started | Jul 10 06:01:31 PM PDT 24 |
| Finished | Jul 10 06:02:56 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-1c07a256-a02a-42c9-b0e5-766ab87f51fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034647022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3034647022 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3081270804 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10052060000 ps |
| CPU time | 35.73 seconds |
| Started | Jul 10 06:01:26 PM PDT 24 |
| Finished | Jul 10 06:02:34 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-aca01ee5-4d5a-493e-85aa-633047b6a2b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081270804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3081270804 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3078381495 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4008300000 ps |
| CPU time | 15.94 seconds |
| Started | Jul 10 06:01:27 PM PDT 24 |
| Finished | Jul 10 06:01:58 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-6665f945-0e45-44da-bb7b-f8ce431bb377 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078381495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3078381495 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1295389785 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 15465280000 ps |
| CPU time | 50.48 seconds |
| Started | Jul 10 06:01:26 PM PDT 24 |
| Finished | Jul 10 06:03:01 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-5d72b3f1-aa8d-4a2b-b587-e7ab97d74412 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1295389785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1295389785 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.113046376 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8962720000 ps |
| CPU time | 34.94 seconds |
| Started | Jul 10 06:01:28 PM PDT 24 |
| Finished | Jul 10 06:02:36 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-4bec3040-b92a-4b10-a2cb-44fe1809ea37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113046376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.113046376 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2840002209 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11664680000 ps |
| CPU time | 47.69 seconds |
| Started | Jul 10 06:01:24 PM PDT 24 |
| Finished | Jul 10 06:03:06 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-d665f215-16d3-495f-aed3-08f8ea14cb4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840002209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2840002209 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1703459328 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8135020000 ps |
| CPU time | 32.82 seconds |
| Started | Jul 10 06:01:17 PM PDT 24 |
| Finished | Jul 10 06:02:21 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-b847557a-6b61-4bc1-a8ff-e24b26e9a251 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703459328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1703459328 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.211191948 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12315680000 ps |
| CPU time | 44.82 seconds |
| Started | Jul 10 06:01:19 PM PDT 24 |
| Finished | Jul 10 06:02:45 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-cf13a01a-c8af-4e67-b185-79c64653434f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211191948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.211191948 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.10793054 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5965020000 ps |
| CPU time | 25.93 seconds |
| Started | Jul 10 06:01:24 PM PDT 24 |
| Finished | Jul 10 06:02:20 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-b55733e0-f1a5-4020-a016-d6212bfbcbd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10793054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.10793054 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2597995146 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7524320000 ps |
| CPU time | 28.42 seconds |
| Started | Jul 10 06:01:17 PM PDT 24 |
| Finished | Jul 10 06:02:12 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-ae8be1c4-4735-4eab-93f8-fb17fa35b690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597995146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2597995146 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |