| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.1059396362 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1523345859 |
| /workspace/coverage/default/10.prim_present_test.60521038 |
| /workspace/coverage/default/11.prim_present_test.290148517 |
| /workspace/coverage/default/12.prim_present_test.2665350224 |
| /workspace/coverage/default/13.prim_present_test.2074049149 |
| /workspace/coverage/default/14.prim_present_test.2438869164 |
| /workspace/coverage/default/15.prim_present_test.2905433413 |
| /workspace/coverage/default/16.prim_present_test.3357272142 |
| /workspace/coverage/default/17.prim_present_test.690747729 |
| /workspace/coverage/default/18.prim_present_test.361806404 |
| /workspace/coverage/default/19.prim_present_test.3363089994 |
| /workspace/coverage/default/2.prim_present_test.1230185509 |
| /workspace/coverage/default/20.prim_present_test.3640685557 |
| /workspace/coverage/default/21.prim_present_test.1611558840 |
| /workspace/coverage/default/22.prim_present_test.3919599175 |
| /workspace/coverage/default/23.prim_present_test.203910530 |
| /workspace/coverage/default/24.prim_present_test.4119465512 |
| /workspace/coverage/default/25.prim_present_test.1515995464 |
| /workspace/coverage/default/26.prim_present_test.465189792 |
| /workspace/coverage/default/27.prim_present_test.1291035915 |
| /workspace/coverage/default/28.prim_present_test.2867362544 |
| /workspace/coverage/default/29.prim_present_test.4044996829 |
| /workspace/coverage/default/3.prim_present_test.1984407676 |
| /workspace/coverage/default/30.prim_present_test.3209944019 |
| /workspace/coverage/default/31.prim_present_test.3720861865 |
| /workspace/coverage/default/32.prim_present_test.2119616083 |
| /workspace/coverage/default/33.prim_present_test.2073686452 |
| /workspace/coverage/default/34.prim_present_test.2666541373 |
| /workspace/coverage/default/35.prim_present_test.385229027 |
| /workspace/coverage/default/36.prim_present_test.1307577217 |
| /workspace/coverage/default/37.prim_present_test.746876836 |
| /workspace/coverage/default/38.prim_present_test.1332597387 |
| /workspace/coverage/default/39.prim_present_test.2327784656 |
| /workspace/coverage/default/4.prim_present_test.1526397731 |
| /workspace/coverage/default/40.prim_present_test.2266037106 |
| /workspace/coverage/default/41.prim_present_test.2053049029 |
| /workspace/coverage/default/42.prim_present_test.880724199 |
| /workspace/coverage/default/43.prim_present_test.289706779 |
| /workspace/coverage/default/44.prim_present_test.1139199666 |
| /workspace/coverage/default/45.prim_present_test.1642064327 |
| /workspace/coverage/default/46.prim_present_test.294491639 |
| /workspace/coverage/default/47.prim_present_test.2723386183 |
| /workspace/coverage/default/48.prim_present_test.2360614038 |
| /workspace/coverage/default/49.prim_present_test.3798381536 |
| /workspace/coverage/default/5.prim_present_test.1850416489 |
| /workspace/coverage/default/6.prim_present_test.4067941152 |
| /workspace/coverage/default/7.prim_present_test.1325898547 |
| /workspace/coverage/default/8.prim_present_test.838505675 |
| /workspace/coverage/default/9.prim_present_test.432733209 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/25.prim_present_test.1515995464 | Jul 11 05:42:20 PM PDT 24 | Jul 11 05:43:50 PM PDT 24 | 13770200000 ps | ||
| T2 | /workspace/coverage/default/1.prim_present_test.1059396362 | Jul 11 05:42:13 PM PDT 24 | Jul 11 05:43:31 PM PDT 24 | 10691900000 ps | ||
| T3 | /workspace/coverage/default/30.prim_present_test.3209944019 | Jul 11 05:42:20 PM PDT 24 | Jul 11 05:43:35 PM PDT 24 | 9782360000 ps | ||
| T4 | /workspace/coverage/default/9.prim_present_test.432733209 | Jul 11 05:42:42 PM PDT 24 | Jul 11 05:44:21 PM PDT 24 | 12312580000 ps | ||
| T5 | /workspace/coverage/default/23.prim_present_test.203910530 | Jul 11 05:42:19 PM PDT 24 | Jul 11 05:44:06 PM PDT 24 | 14145920000 ps | ||
| T6 | /workspace/coverage/default/10.prim_present_test.60521038 | Jul 11 05:42:13 PM PDT 24 | Jul 11 05:42:40 PM PDT 24 | 4315200000 ps | ||
| T7 | /workspace/coverage/default/21.prim_present_test.1611558840 | Jul 11 05:42:42 PM PDT 24 | Jul 11 05:44:03 PM PDT 24 | 9822660000 ps | ||
| T8 | /workspace/coverage/default/6.prim_present_test.4067941152 | Jul 11 05:42:37 PM PDT 24 | Jul 11 05:43:55 PM PDT 24 | 10829540000 ps | ||
| T9 | /workspace/coverage/default/12.prim_present_test.2665350224 | Jul 11 05:42:14 PM PDT 24 | Jul 11 05:43:55 PM PDT 24 | 12698840000 ps | ||
| T10 | /workspace/coverage/default/44.prim_present_test.1139199666 | Jul 11 05:42:49 PM PDT 24 | Jul 11 05:43:38 PM PDT 24 | 4839100000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.2327784656 | Jul 11 05:42:39 PM PDT 24 | Jul 11 05:44:10 PM PDT 24 | 14175680000 ps | ||
| T12 | /workspace/coverage/default/43.prim_present_test.289706779 | Jul 11 05:42:41 PM PDT 24 | Jul 11 05:43:28 PM PDT 24 | 4867620000 ps | ||
| T13 | /workspace/coverage/default/35.prim_present_test.385229027 | Jul 11 05:42:21 PM PDT 24 | Jul 11 05:44:10 PM PDT 24 | 14167620000 ps | ||
| T14 | /workspace/coverage/default/18.prim_present_test.361806404 | Jul 11 05:42:40 PM PDT 24 | Jul 11 05:43:17 PM PDT 24 | 4815540000 ps | ||
| T15 | /workspace/coverage/default/33.prim_present_test.2073686452 | Jul 11 05:42:35 PM PDT 24 | Jul 11 05:43:27 PM PDT 24 | 6929740000 ps | ||
| T16 | /workspace/coverage/default/0.prim_present_test.1523345859 | Jul 11 05:42:40 PM PDT 24 | Jul 11 05:43:30 PM PDT 24 | 6932840000 ps | ||
| T17 | /workspace/coverage/default/42.prim_present_test.880724199 | Jul 11 05:42:26 PM PDT 24 | Jul 11 05:44:13 PM PDT 24 | 15413820000 ps | ||
| T18 | /workspace/coverage/default/3.prim_present_test.1984407676 | Jul 11 05:42:34 PM PDT 24 | Jul 11 05:43:54 PM PDT 24 | 13139040000 ps | ||
| T19 | /workspace/coverage/default/26.prim_present_test.465189792 | Jul 11 05:42:25 PM PDT 24 | Jul 11 05:43:33 PM PDT 24 | 11256100000 ps | ||
| T20 | /workspace/coverage/default/13.prim_present_test.2074049149 | Jul 11 05:42:18 PM PDT 24 | Jul 11 05:43:03 PM PDT 24 | 5602320000 ps | ||
| T21 | /workspace/coverage/default/32.prim_present_test.2119616083 | Jul 11 05:42:36 PM PDT 24 | Jul 11 05:43:40 PM PDT 24 | 8955900000 ps | ||
| T22 | /workspace/coverage/default/28.prim_present_test.2867362544 | Jul 11 05:42:38 PM PDT 24 | Jul 11 05:43:47 PM PDT 24 | 10947340000 ps | ||
| T23 | /workspace/coverage/default/36.prim_present_test.1307577217 | Jul 11 05:42:40 PM PDT 24 | Jul 11 05:43:53 PM PDT 24 | 10703680000 ps | ||
| T24 | /workspace/coverage/default/48.prim_present_test.2360614038 | Jul 11 05:42:39 PM PDT 24 | Jul 11 05:43:34 PM PDT 24 | 7604300000 ps | ||
| T25 | /workspace/coverage/default/5.prim_present_test.1850416489 | Jul 11 05:42:13 PM PDT 24 | Jul 11 05:43:41 PM PDT 24 | 14217840000 ps | ||
| T26 | /workspace/coverage/default/14.prim_present_test.2438869164 | Jul 11 05:42:42 PM PDT 24 | Jul 11 05:44:32 PM PDT 24 | 13826000000 ps | ||
| T27 | /workspace/coverage/default/45.prim_present_test.1642064327 | Jul 11 05:42:45 PM PDT 24 | Jul 11 05:43:20 PM PDT 24 | 4950700000 ps | ||
| T28 | /workspace/coverage/default/41.prim_present_test.2053049029 | Jul 11 05:42:45 PM PDT 24 | Jul 11 05:44:28 PM PDT 24 | 15178220000 ps | ||
| T29 | /workspace/coverage/default/49.prim_present_test.3798381536 | Jul 11 05:42:38 PM PDT 24 | Jul 11 05:44:02 PM PDT 24 | 12349160000 ps | ||
| T30 | /workspace/coverage/default/29.prim_present_test.4044996829 | Jul 11 05:42:50 PM PDT 24 | Jul 11 05:43:35 PM PDT 24 | 4445400000 ps | ||
| T31 | /workspace/coverage/default/40.prim_present_test.2266037106 | Jul 11 05:42:42 PM PDT 24 | Jul 11 05:43:18 PM PDT 24 | 3444100000 ps | ||
| T32 | /workspace/coverage/default/8.prim_present_test.838505675 | Jul 11 05:42:15 PM PDT 24 | Jul 11 05:42:43 PM PDT 24 | 4303420000 ps | ||
| T33 | /workspace/coverage/default/27.prim_present_test.1291035915 | Jul 11 05:42:33 PM PDT 24 | Jul 11 05:43:25 PM PDT 24 | 7213080000 ps | ||
| T34 | /workspace/coverage/default/22.prim_present_test.3919599175 | Jul 11 05:42:40 PM PDT 24 | Jul 11 05:43:23 PM PDT 24 | 5912940000 ps | ||
| T35 | /workspace/coverage/default/34.prim_present_test.2666541373 | Jul 11 05:42:37 PM PDT 24 | Jul 11 05:43:09 PM PDT 24 | 3829740000 ps | ||
| T36 | /workspace/coverage/default/46.prim_present_test.294491639 | Jul 11 05:42:22 PM PDT 24 | Jul 11 05:44:11 PM PDT 24 | 14513580000 ps | ||
| T37 | /workspace/coverage/default/4.prim_present_test.1526397731 | Jul 11 05:42:43 PM PDT 24 | Jul 11 05:43:13 PM PDT 24 | 3946300000 ps | ||
| T38 | /workspace/coverage/default/37.prim_present_test.746876836 | Jul 11 05:42:18 PM PDT 24 | Jul 11 05:43:05 PM PDT 24 | 6780940000 ps | ||
| T39 | /workspace/coverage/default/19.prim_present_test.3363089994 | Jul 11 05:42:33 PM PDT 24 | Jul 11 05:43:21 PM PDT 24 | 6648880000 ps | ||
| T40 | /workspace/coverage/default/47.prim_present_test.2723386183 | Jul 11 05:42:40 PM PDT 24 | Jul 11 05:43:11 PM PDT 24 | 3801220000 ps | ||
| T41 | /workspace/coverage/default/17.prim_present_test.690747729 | Jul 11 05:42:15 PM PDT 24 | Jul 11 05:42:58 PM PDT 24 | 6431880000 ps | ||
| T42 | /workspace/coverage/default/7.prim_present_test.1325898547 | Jul 11 05:42:48 PM PDT 24 | Jul 11 05:44:11 PM PDT 24 | 9407880000 ps | ||
| T43 | /workspace/coverage/default/11.prim_present_test.290148517 | Jul 11 05:42:15 PM PDT 24 | Jul 11 05:43:32 PM PDT 24 | 12227020000 ps | ||
| T44 | /workspace/coverage/default/24.prim_present_test.4119465512 | Jul 11 05:42:37 PM PDT 24 | Jul 11 05:43:31 PM PDT 24 | 7138060000 ps | ||
| T45 | /workspace/coverage/default/2.prim_present_test.1230185509 | Jul 11 05:42:43 PM PDT 24 | Jul 11 05:43:23 PM PDT 24 | 3878100000 ps | ||
| T46 | /workspace/coverage/default/16.prim_present_test.3357272142 | Jul 11 05:42:19 PM PDT 24 | Jul 11 05:43:49 PM PDT 24 | 11781860000 ps | ||
| T47 | /workspace/coverage/default/15.prim_present_test.2905433413 | Jul 11 05:42:50 PM PDT 24 | Jul 11 05:43:53 PM PDT 24 | 7015920000 ps | ||
| T48 | /workspace/coverage/default/38.prim_present_test.1332597387 | Jul 11 05:42:48 PM PDT 24 | Jul 11 05:44:27 PM PDT 24 | 11866800000 ps | ||
| T49 | /workspace/coverage/default/20.prim_present_test.3640685557 | Jul 11 05:42:21 PM PDT 24 | Jul 11 05:43:22 PM PDT 24 | 7391640000 ps | ||
| T50 | /workspace/coverage/default/31.prim_present_test.3720861865 | Jul 11 05:42:49 PM PDT 24 | Jul 11 05:44:37 PM PDT 24 | 13556300000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.1059396362 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10691900000 ps |
| CPU time | 40.4 seconds |
| Started | Jul 11 05:42:13 PM PDT 24 |
| Finished | Jul 11 05:43:31 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-0dc397b3-14bb-4a6f-82e5-47be770da9f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059396362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1059396362 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1523345859 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6932840000 ps |
| CPU time | 23.08 seconds |
| Started | Jul 11 05:42:40 PM PDT 24 |
| Finished | Jul 11 05:43:30 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-f8948caf-53f4-44d4-a49e-4ebf0804c024 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523345859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1523345859 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.60521038 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4315200000 ps |
| CPU time | 13.49 seconds |
| Started | Jul 11 05:42:13 PM PDT 24 |
| Finished | Jul 11 05:42:40 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-c65ba873-f4f7-4a29-b381-744222948fbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60521038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.60521038 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.290148517 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12227020000 ps |
| CPU time | 40.43 seconds |
| Started | Jul 11 05:42:15 PM PDT 24 |
| Finished | Jul 11 05:43:32 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-f8665e81-f72d-42a3-aa09-414dea1500b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290148517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.290148517 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2665350224 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12698840000 ps |
| CPU time | 51.33 seconds |
| Started | Jul 11 05:42:14 PM PDT 24 |
| Finished | Jul 11 05:43:55 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-ff86e6eb-1834-49be-a29c-2d3ab5ed1986 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665350224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2665350224 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2074049149 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5602320000 ps |
| CPU time | 21.17 seconds |
| Started | Jul 11 05:42:18 PM PDT 24 |
| Finished | Jul 11 05:43:03 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-9d9c935e-6865-459f-9ac0-53ae7f3aee06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074049149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2074049149 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2438869164 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13826000000 ps |
| CPU time | 52.69 seconds |
| Started | Jul 11 05:42:42 PM PDT 24 |
| Finished | Jul 11 05:44:32 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-74712a20-a7cd-41cc-8359-e452e24b2440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438869164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2438869164 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2905433413 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7015920000 ps |
| CPU time | 28.62 seconds |
| Started | Jul 11 05:42:50 PM PDT 24 |
| Finished | Jul 11 05:43:53 PM PDT 24 |
| Peak memory | 144300 kb |
| Host | smart-0318c037-abd6-4666-81a4-71dbd2c1a206 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905433413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2905433413 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3357272142 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11781860000 ps |
| CPU time | 44.67 seconds |
| Started | Jul 11 05:42:19 PM PDT 24 |
| Finished | Jul 11 05:43:49 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-90feb96d-96cb-4f8a-a46d-75796e784f18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357272142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3357272142 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.690747729 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6431880000 ps |
| CPU time | 22.14 seconds |
| Started | Jul 11 05:42:15 PM PDT 24 |
| Finished | Jul 11 05:42:58 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-bc4041bf-d726-4cf4-98b4-dc3da6dbbe48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690747729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.690747729 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.361806404 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4815540000 ps |
| CPU time | 16.34 seconds |
| Started | Jul 11 05:42:40 PM PDT 24 |
| Finished | Jul 11 05:43:17 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-2df240de-fbe4-4f41-8941-306066b03c2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361806404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.361806404 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3363089994 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6648880000 ps |
| CPU time | 23.51 seconds |
| Started | Jul 11 05:42:33 PM PDT 24 |
| Finished | Jul 11 05:43:21 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-a4104b6a-caa4-4967-b87f-1d5859df6498 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363089994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3363089994 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1230185509 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3878100000 ps |
| CPU time | 16.54 seconds |
| Started | Jul 11 05:42:43 PM PDT 24 |
| Finished | Jul 11 05:43:23 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-d5a06aec-2c6b-42f0-b779-d57e006213a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230185509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1230185509 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3640685557 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7391640000 ps |
| CPU time | 29.37 seconds |
| Started | Jul 11 05:42:21 PM PDT 24 |
| Finished | Jul 11 05:43:22 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-528157c2-02a3-49f8-b063-872e332b118f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3640685557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3640685557 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1611558840 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9822660000 ps |
| CPU time | 37.34 seconds |
| Started | Jul 11 05:42:42 PM PDT 24 |
| Finished | Jul 11 05:44:03 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-3ca205ff-ccbb-42bf-bfab-6c45342db1f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611558840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1611558840 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3919599175 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5912940000 ps |
| CPU time | 19.45 seconds |
| Started | Jul 11 05:42:40 PM PDT 24 |
| Finished | Jul 11 05:43:23 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-365bc5cc-9992-42df-86cb-9de8bf5b9408 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3919599175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3919599175 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.203910530 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14145920000 ps |
| CPU time | 53.42 seconds |
| Started | Jul 11 05:42:19 PM PDT 24 |
| Finished | Jul 11 05:44:06 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-00ede49d-900f-4d23-8512-7d25f3ca7122 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203910530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.203910530 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4119465512 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7138060000 ps |
| CPU time | 25.16 seconds |
| Started | Jul 11 05:42:37 PM PDT 24 |
| Finished | Jul 11 05:43:31 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-2bf2a97e-1105-448e-8fb2-8aba8e7e086e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119465512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4119465512 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1515995464 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13770200000 ps |
| CPU time | 45.7 seconds |
| Started | Jul 11 05:42:20 PM PDT 24 |
| Finished | Jul 11 05:43:50 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-dec7db2e-7f90-4f8c-94cf-9406f465b009 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515995464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1515995464 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.465189792 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11256100000 ps |
| CPU time | 33.57 seconds |
| Started | Jul 11 05:42:25 PM PDT 24 |
| Finished | Jul 11 05:43:33 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-249fa28f-0c2e-4599-8879-701c0fb386af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465189792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.465189792 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1291035915 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7213080000 ps |
| CPU time | 25.47 seconds |
| Started | Jul 11 05:42:33 PM PDT 24 |
| Finished | Jul 11 05:43:25 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-274ee60a-30f4-4dcc-9995-2487698c19fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291035915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1291035915 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2867362544 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10947340000 ps |
| CPU time | 34.46 seconds |
| Started | Jul 11 05:42:38 PM PDT 24 |
| Finished | Jul 11 05:43:47 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-45e2be55-cc3c-4f4b-8fde-9e5134eed3c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867362544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2867362544 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4044996829 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4445400000 ps |
| CPU time | 19.43 seconds |
| Started | Jul 11 05:42:50 PM PDT 24 |
| Finished | Jul 11 05:43:35 PM PDT 24 |
| Peak memory | 144368 kb |
| Host | smart-3f24092a-b91c-4758-9b34-b3060632006e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044996829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4044996829 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1984407676 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13139040000 ps |
| CPU time | 41.01 seconds |
| Started | Jul 11 05:42:34 PM PDT 24 |
| Finished | Jul 11 05:43:54 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-478b6562-9061-4e7d-9115-a06dc430b185 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984407676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1984407676 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3209944019 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9782360000 ps |
| CPU time | 36.91 seconds |
| Started | Jul 11 05:42:20 PM PDT 24 |
| Finished | Jul 11 05:43:35 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-649f64d2-d2f3-4cfe-ac93-d59913b6d6d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3209944019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3209944019 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3720861865 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13556300000 ps |
| CPU time | 52.62 seconds |
| Started | Jul 11 05:42:49 PM PDT 24 |
| Finished | Jul 11 05:44:37 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-106af56b-3a3e-464f-b8a1-2ebedfdffbb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720861865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3720861865 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2119616083 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8955900000 ps |
| CPU time | 30.76 seconds |
| Started | Jul 11 05:42:36 PM PDT 24 |
| Finished | Jul 11 05:43:40 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-83699c89-f581-42f5-9724-b31b2ef47827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2119616083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2119616083 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2073686452 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6929740000 ps |
| CPU time | 23.85 seconds |
| Started | Jul 11 05:42:35 PM PDT 24 |
| Finished | Jul 11 05:43:27 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-5314c539-8aa6-4e49-b747-df45ee10bab1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073686452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2073686452 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2666541373 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3829740000 ps |
| CPU time | 14.01 seconds |
| Started | Jul 11 05:42:37 PM PDT 24 |
| Finished | Jul 11 05:43:09 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-884bef4b-9818-41eb-ba64-bb8cd6d6ae20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666541373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2666541373 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.385229027 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14167620000 ps |
| CPU time | 53.6 seconds |
| Started | Jul 11 05:42:21 PM PDT 24 |
| Finished | Jul 11 05:44:10 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-5b0a9b01-ff05-4b5c-b5ef-c5f5facdbfc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385229027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.385229027 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1307577217 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10703680000 ps |
| CPU time | 35.33 seconds |
| Started | Jul 11 05:42:40 PM PDT 24 |
| Finished | Jul 11 05:43:53 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-b8241b65-eba8-45b9-a04b-9537fe5e38c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1307577217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1307577217 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.746876836 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6780940000 ps |
| CPU time | 23.5 seconds |
| Started | Jul 11 05:42:18 PM PDT 24 |
| Finished | Jul 11 05:43:05 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-4506ef8f-4a8d-43f6-8e00-7890c920a9a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746876836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.746876836 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1332597387 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11866800000 ps |
| CPU time | 47.18 seconds |
| Started | Jul 11 05:42:48 PM PDT 24 |
| Finished | Jul 11 05:44:27 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-c8159e76-8e74-4a45-aedc-40dca1b93695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332597387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1332597387 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2327784656 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14175680000 ps |
| CPU time | 45.47 seconds |
| Started | Jul 11 05:42:39 PM PDT 24 |
| Finished | Jul 11 05:44:10 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-34dadb07-bed9-4960-9c2e-5ef7b8ba84de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2327784656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2327784656 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1526397731 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3946300000 ps |
| CPU time | 13.21 seconds |
| Started | Jul 11 05:42:43 PM PDT 24 |
| Finished | Jul 11 05:43:13 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-65609cf4-452c-4eec-bb74-0d87ad351fd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526397731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1526397731 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2266037106 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3444100000 ps |
| CPU time | 14.52 seconds |
| Started | Jul 11 05:42:42 PM PDT 24 |
| Finished | Jul 11 05:43:18 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-d5624bfc-391a-4125-9cfa-b6cbc5d29d39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266037106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2266037106 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2053049029 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 15178220000 ps |
| CPU time | 51.37 seconds |
| Started | Jul 11 05:42:45 PM PDT 24 |
| Finished | Jul 11 05:44:28 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-8bf82777-bfc9-4e82-a07e-72c986dbbc10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053049029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2053049029 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.880724199 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 15413820000 ps |
| CPU time | 53.53 seconds |
| Started | Jul 11 05:42:26 PM PDT 24 |
| Finished | Jul 11 05:44:13 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-e76e7ac3-a3be-46a7-a1f0-fa93da92803f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880724199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.880724199 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.289706779 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4867620000 ps |
| CPU time | 20.03 seconds |
| Started | Jul 11 05:42:41 PM PDT 24 |
| Finished | Jul 11 05:43:28 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-75e4dd4a-2fee-4970-9a39-e85368e8856f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289706779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.289706779 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1139199666 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4839100000 ps |
| CPU time | 21.07 seconds |
| Started | Jul 11 05:42:49 PM PDT 24 |
| Finished | Jul 11 05:43:38 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-28baa660-e649-45d7-8fb9-97b3841357c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139199666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1139199666 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1642064327 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4950700000 ps |
| CPU time | 15.84 seconds |
| Started | Jul 11 05:42:45 PM PDT 24 |
| Finished | Jul 11 05:43:20 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-3bf5473e-8fb3-4c14-9e48-92d31c3b1b64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642064327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1642064327 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.294491639 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14513580000 ps |
| CPU time | 54.29 seconds |
| Started | Jul 11 05:42:22 PM PDT 24 |
| Finished | Jul 11 05:44:11 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-adf739fd-4333-4622-bb59-91d01d8ae48e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294491639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.294491639 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2723386183 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3801220000 ps |
| CPU time | 12.86 seconds |
| Started | Jul 11 05:42:40 PM PDT 24 |
| Finished | Jul 11 05:43:11 PM PDT 24 |
| Peak memory | 144708 kb |
| Host | smart-0262ce13-212a-41c6-9e28-df85a555c151 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723386183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2723386183 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2360614038 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7604300000 ps |
| CPU time | 26.05 seconds |
| Started | Jul 11 05:42:39 PM PDT 24 |
| Finished | Jul 11 05:43:34 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-37066fbf-3925-4818-822b-b4f9e44dc67f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2360614038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2360614038 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3798381536 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 12349160000 ps |
| CPU time | 41.97 seconds |
| Started | Jul 11 05:42:38 PM PDT 24 |
| Finished | Jul 11 05:44:02 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-30bedd95-4563-4a93-a29d-03723e94fe8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3798381536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3798381536 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1850416489 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 14217840000 ps |
| CPU time | 45.95 seconds |
| Started | Jul 11 05:42:13 PM PDT 24 |
| Finished | Jul 11 05:43:41 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-d7e54b38-73f2-4662-9dec-e167608b935a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850416489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1850416489 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4067941152 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10829540000 ps |
| CPU time | 37.85 seconds |
| Started | Jul 11 05:42:37 PM PDT 24 |
| Finished | Jul 11 05:43:55 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-5145f409-1383-4b1d-810a-df558ee50f22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067941152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4067941152 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1325898547 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 9407880000 ps |
| CPU time | 38.94 seconds |
| Started | Jul 11 05:42:48 PM PDT 24 |
| Finished | Jul 11 05:44:11 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-1b72ad02-5b59-49f3-9771-39856e131e75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325898547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1325898547 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.838505675 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4303420000 ps |
| CPU time | 14.45 seconds |
| Started | Jul 11 05:42:15 PM PDT 24 |
| Finished | Jul 11 05:42:43 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-82d0a9f2-4735-45ef-8254-5d15a92af949 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838505675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.838505675 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.432733209 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12312580000 ps |
| CPU time | 46.59 seconds |
| Started | Jul 11 05:42:42 PM PDT 24 |
| Finished | Jul 11 05:44:21 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-f62e8538-9ba7-4222-9c2e-a540964647e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432733209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.432733209 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |