| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/17.prim_present_test.1101671277 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2254169389 |
| /workspace/coverage/default/1.prim_present_test.407607671 |
| /workspace/coverage/default/10.prim_present_test.4271289386 |
| /workspace/coverage/default/11.prim_present_test.2260755894 |
| /workspace/coverage/default/12.prim_present_test.384293206 |
| /workspace/coverage/default/13.prim_present_test.754252130 |
| /workspace/coverage/default/14.prim_present_test.536392290 |
| /workspace/coverage/default/15.prim_present_test.1477690317 |
| /workspace/coverage/default/16.prim_present_test.321153193 |
| /workspace/coverage/default/18.prim_present_test.2231795060 |
| /workspace/coverage/default/19.prim_present_test.3319477243 |
| /workspace/coverage/default/2.prim_present_test.4294821814 |
| /workspace/coverage/default/20.prim_present_test.737795220 |
| /workspace/coverage/default/21.prim_present_test.520398040 |
| /workspace/coverage/default/22.prim_present_test.1046515902 |
| /workspace/coverage/default/23.prim_present_test.14233581 |
| /workspace/coverage/default/24.prim_present_test.3735355159 |
| /workspace/coverage/default/25.prim_present_test.489023030 |
| /workspace/coverage/default/26.prim_present_test.10559001 |
| /workspace/coverage/default/27.prim_present_test.813492722 |
| /workspace/coverage/default/28.prim_present_test.4121315714 |
| /workspace/coverage/default/29.prim_present_test.1432149698 |
| /workspace/coverage/default/3.prim_present_test.1095444532 |
| /workspace/coverage/default/30.prim_present_test.3424963441 |
| /workspace/coverage/default/31.prim_present_test.801542753 |
| /workspace/coverage/default/32.prim_present_test.1979024345 |
| /workspace/coverage/default/33.prim_present_test.3894373304 |
| /workspace/coverage/default/34.prim_present_test.49885922 |
| /workspace/coverage/default/35.prim_present_test.3554584255 |
| /workspace/coverage/default/36.prim_present_test.2168689568 |
| /workspace/coverage/default/37.prim_present_test.3779510536 |
| /workspace/coverage/default/38.prim_present_test.3551004975 |
| /workspace/coverage/default/39.prim_present_test.1175734209 |
| /workspace/coverage/default/4.prim_present_test.3583927304 |
| /workspace/coverage/default/40.prim_present_test.2119060761 |
| /workspace/coverage/default/41.prim_present_test.229090483 |
| /workspace/coverage/default/42.prim_present_test.4258016216 |
| /workspace/coverage/default/43.prim_present_test.4205111051 |
| /workspace/coverage/default/44.prim_present_test.2664772663 |
| /workspace/coverage/default/45.prim_present_test.472066151 |
| /workspace/coverage/default/46.prim_present_test.944972976 |
| /workspace/coverage/default/47.prim_present_test.3392306939 |
| /workspace/coverage/default/48.prim_present_test.3723547480 |
| /workspace/coverage/default/49.prim_present_test.3100188121 |
| /workspace/coverage/default/5.prim_present_test.3171534866 |
| /workspace/coverage/default/6.prim_present_test.2834798547 |
| /workspace/coverage/default/7.prim_present_test.2482736522 |
| /workspace/coverage/default/8.prim_present_test.2326707699 |
| /workspace/coverage/default/9.prim_present_test.881534409 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/25.prim_present_test.489023030 | Jul 12 05:01:41 PM PDT 24 | Jul 12 05:02:54 PM PDT 24 | 11430320000 ps | ||
| T2 | /workspace/coverage/default/48.prim_present_test.3723547480 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:03:00 PM PDT 24 | 9870400000 ps | ||
| T3 | /workspace/coverage/default/44.prim_present_test.2664772663 | Jul 12 05:01:51 PM PDT 24 | Jul 12 05:02:55 PM PDT 24 | 11060800000 ps | ||
| T4 | /workspace/coverage/default/26.prim_present_test.10559001 | Jul 12 05:01:51 PM PDT 24 | Jul 12 05:02:49 PM PDT 24 | 10020440000 ps | ||
| T5 | /workspace/coverage/default/9.prim_present_test.881534409 | Jul 12 05:01:49 PM PDT 24 | Jul 12 05:02:36 PM PDT 24 | 4818020000 ps | ||
| T6 | /workspace/coverage/default/47.prim_present_test.3392306939 | Jul 12 05:01:50 PM PDT 24 | Jul 12 05:02:22 PM PDT 24 | 4974260000 ps | ||
| T7 | /workspace/coverage/default/36.prim_present_test.2168689568 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:03:17 PM PDT 24 | 11437760000 ps | ||
| T8 | /workspace/coverage/default/17.prim_present_test.1101671277 | Jul 12 05:01:44 PM PDT 24 | Jul 12 05:02:07 PM PDT 24 | 3242600000 ps | ||
| T9 | /workspace/coverage/default/37.prim_present_test.3779510536 | Jul 12 05:01:45 PM PDT 24 | Jul 12 05:02:56 PM PDT 24 | 11073200000 ps | ||
| T10 | /workspace/coverage/default/5.prim_present_test.3171534866 | Jul 12 05:01:44 PM PDT 24 | Jul 12 05:02:52 PM PDT 24 | 8600640000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.1175734209 | Jul 12 05:01:49 PM PDT 24 | Jul 12 05:03:17 PM PDT 24 | 11554320000 ps | ||
| T12 | /workspace/coverage/default/38.prim_present_test.3551004975 | Jul 12 05:01:49 PM PDT 24 | Jul 12 05:03:16 PM PDT 24 | 13215920000 ps | ||
| T13 | /workspace/coverage/default/3.prim_present_test.1095444532 | Jul 12 05:01:40 PM PDT 24 | Jul 12 05:03:17 PM PDT 24 | 14033080000 ps | ||
| T14 | /workspace/coverage/default/14.prim_present_test.536392290 | Jul 12 05:01:42 PM PDT 24 | Jul 12 05:02:10 PM PDT 24 | 3310180000 ps | ||
| T15 | /workspace/coverage/default/20.prim_present_test.737795220 | Jul 12 05:01:52 PM PDT 24 | Jul 12 05:03:12 PM PDT 24 | 13516000000 ps | ||
| T16 | /workspace/coverage/default/41.prim_present_test.229090483 | Jul 12 05:01:52 PM PDT 24 | Jul 12 05:02:26 PM PDT 24 | 4905440000 ps | ||
| T17 | /workspace/coverage/default/32.prim_present_test.1979024345 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:02:36 PM PDT 24 | 5757940000 ps | ||
| T18 | /workspace/coverage/default/12.prim_present_test.384293206 | Jul 12 05:01:44 PM PDT 24 | Jul 12 05:02:40 PM PDT 24 | 8801520000 ps | ||
| T19 | /workspace/coverage/default/40.prim_present_test.2119060761 | Jul 12 05:01:50 PM PDT 24 | Jul 12 05:03:02 PM PDT 24 | 10649120000 ps | ||
| T20 | /workspace/coverage/default/33.prim_present_test.3894373304 | Jul 12 05:01:49 PM PDT 24 | Jul 12 05:02:59 PM PDT 24 | 11613220000 ps | ||
| T21 | /workspace/coverage/default/46.prim_present_test.944972976 | Jul 12 05:01:51 PM PDT 24 | Jul 12 05:02:20 PM PDT 24 | 4530340000 ps | ||
| T22 | /workspace/coverage/default/49.prim_present_test.3100188121 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:02:30 PM PDT 24 | 5329520000 ps | ||
| T23 | /workspace/coverage/default/4.prim_present_test.3583927304 | Jul 12 05:01:43 PM PDT 24 | Jul 12 05:03:07 PM PDT 24 | 10593320000 ps | ||
| T24 | /workspace/coverage/default/7.prim_present_test.2482736522 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:03:21 PM PDT 24 | 12107980000 ps | ||
| T25 | /workspace/coverage/default/43.prim_present_test.4205111051 | Jul 12 05:01:46 PM PDT 24 | Jul 12 05:02:39 PM PDT 24 | 7158520000 ps | ||
| T26 | /workspace/coverage/default/22.prim_present_test.1046515902 | Jul 12 05:01:46 PM PDT 24 | Jul 12 05:02:54 PM PDT 24 | 10600140000 ps | ||
| T27 | /workspace/coverage/default/28.prim_present_test.4121315714 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:02:39 PM PDT 24 | 6800160000 ps | ||
| T28 | /workspace/coverage/default/8.prim_present_test.2326707699 | Jul 12 05:01:45 PM PDT 24 | Jul 12 05:03:16 PM PDT 24 | 14601620000 ps | ||
| T29 | /workspace/coverage/default/6.prim_present_test.2834798547 | Jul 12 05:01:51 PM PDT 24 | Jul 12 05:02:45 PM PDT 24 | 9277680000 ps | ||
| T30 | /workspace/coverage/default/35.prim_present_test.3554584255 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:03:16 PM PDT 24 | 13341160000 ps | ||
| T31 | /workspace/coverage/default/10.prim_present_test.4271289386 | Jul 12 05:01:42 PM PDT 24 | Jul 12 05:03:11 PM PDT 24 | 13491820000 ps | ||
| T32 | /workspace/coverage/default/1.prim_present_test.407607671 | Jul 12 05:01:41 PM PDT 24 | Jul 12 05:02:37 PM PDT 24 | 6908660000 ps | ||
| T33 | /workspace/coverage/default/21.prim_present_test.520398040 | Jul 12 05:01:44 PM PDT 24 | Jul 12 05:03:06 PM PDT 24 | 12944360000 ps | ||
| T34 | /workspace/coverage/default/29.prim_present_test.1432149698 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:03:40 PM PDT 24 | 14697720000 ps | ||
| T35 | /workspace/coverage/default/19.prim_present_test.3319477243 | Jul 12 05:01:42 PM PDT 24 | Jul 12 05:02:08 PM PDT 24 | 3780760000 ps | ||
| T36 | /workspace/coverage/default/0.prim_present_test.2254169389 | Jul 12 05:01:41 PM PDT 24 | Jul 12 05:02:11 PM PDT 24 | 4609700000 ps | ||
| T37 | /workspace/coverage/default/34.prim_present_test.49885922 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:02:15 PM PDT 24 | 3848340000 ps | ||
| T38 | /workspace/coverage/default/16.prim_present_test.321153193 | Jul 12 05:01:48 PM PDT 24 | Jul 12 05:02:36 PM PDT 24 | 7085360000 ps | ||
| T39 | /workspace/coverage/default/27.prim_present_test.813492722 | Jul 12 05:01:49 PM PDT 24 | Jul 12 05:02:18 PM PDT 24 | 5663700000 ps | ||
| T40 | /workspace/coverage/default/31.prim_present_test.801542753 | Jul 12 05:01:49 PM PDT 24 | Jul 12 05:03:35 PM PDT 24 | 14470180000 ps | ||
| T41 | /workspace/coverage/default/45.prim_present_test.472066151 | Jul 12 05:01:52 PM PDT 24 | Jul 12 05:03:23 PM PDT 24 | 12276000000 ps | ||
| T42 | /workspace/coverage/default/42.prim_present_test.4258016216 | Jul 12 05:01:51 PM PDT 24 | Jul 12 05:03:45 PM PDT 24 | 15243940000 ps | ||
| T43 | /workspace/coverage/default/18.prim_present_test.2231795060 | Jul 12 05:01:40 PM PDT 24 | Jul 12 05:02:44 PM PDT 24 | 8061860000 ps | ||
| T44 | /workspace/coverage/default/24.prim_present_test.3735355159 | Jul 12 05:01:41 PM PDT 24 | Jul 12 05:02:37 PM PDT 24 | 7951500000 ps | ||
| T45 | /workspace/coverage/default/2.prim_present_test.4294821814 | Jul 12 05:01:47 PM PDT 24 | Jul 12 05:03:29 PM PDT 24 | 14013240000 ps | ||
| T46 | /workspace/coverage/default/23.prim_present_test.14233581 | Jul 12 05:01:40 PM PDT 24 | Jul 12 05:03:00 PM PDT 24 | 11396840000 ps | ||
| T47 | /workspace/coverage/default/15.prim_present_test.1477690317 | Jul 12 05:01:47 PM PDT 24 | Jul 12 05:03:12 PM PDT 24 | 12423560000 ps | ||
| T48 | /workspace/coverage/default/11.prim_present_test.2260755894 | Jul 12 05:01:42 PM PDT 24 | Jul 12 05:03:06 PM PDT 24 | 14054780000 ps | ||
| T49 | /workspace/coverage/default/13.prim_present_test.754252130 | Jul 12 05:01:42 PM PDT 24 | Jul 12 05:02:18 PM PDT 24 | 4167640000 ps | ||
| T50 | /workspace/coverage/default/30.prim_present_test.3424963441 | Jul 12 05:01:47 PM PDT 24 | Jul 12 05:03:18 PM PDT 24 | 13307060000 ps |
| Test location | /workspace/coverage/default/17.prim_present_test.1101671277 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3242600000 ps |
| CPU time | 12.19 seconds |
| Started | Jul 12 05:01:44 PM PDT 24 |
| Finished | Jul 12 05:02:07 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-d9e58233-1059-4eb1-b7fe-bff5ea7df726 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101671277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1101671277 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2254169389 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4609700000 ps |
| CPU time | 16.07 seconds |
| Started | Jul 12 05:01:41 PM PDT 24 |
| Finished | Jul 12 05:02:11 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-fe5d33ab-bc27-4931-8968-c841ad9ce588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254169389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2254169389 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.407607671 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6908660000 ps |
| CPU time | 28.83 seconds |
| Started | Jul 12 05:01:41 PM PDT 24 |
| Finished | Jul 12 05:02:37 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-b16ef1f1-d951-4abb-bf5d-d5b0e9325f59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407607671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.407607671 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.4271289386 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13491820000 ps |
| CPU time | 47.56 seconds |
| Started | Jul 12 05:01:42 PM PDT 24 |
| Finished | Jul 12 05:03:11 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-9a298253-6fa7-4667-9e04-75bfa155b031 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271289386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.4271289386 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2260755894 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14054780000 ps |
| CPU time | 45.46 seconds |
| Started | Jul 12 05:01:42 PM PDT 24 |
| Finished | Jul 12 05:03:06 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-95c0afa3-148a-41a9-9215-ed7c4a4aa737 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260755894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2260755894 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.384293206 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8801520000 ps |
| CPU time | 29.58 seconds |
| Started | Jul 12 05:01:44 PM PDT 24 |
| Finished | Jul 12 05:02:40 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-d8a565dc-4c37-4a73-880a-a0b0a9fd518e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384293206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.384293206 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.754252130 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4167640000 ps |
| CPU time | 18.21 seconds |
| Started | Jul 12 05:01:42 PM PDT 24 |
| Finished | Jul 12 05:02:18 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-b0a6d360-d93e-494a-874d-635082555a13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754252130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.754252130 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.536392290 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3310180000 ps |
| CPU time | 14.44 seconds |
| Started | Jul 12 05:01:42 PM PDT 24 |
| Finished | Jul 12 05:02:10 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-338547f0-54e4-4dfb-842a-99744f788d54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536392290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.536392290 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1477690317 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12423560000 ps |
| CPU time | 44.81 seconds |
| Started | Jul 12 05:01:47 PM PDT 24 |
| Finished | Jul 12 05:03:12 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-0d59a925-b033-47a7-9bfd-dc342269ddc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1477690317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1477690317 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.321153193 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7085360000 ps |
| CPU time | 25.14 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:02:36 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-4e7ced50-853a-48a0-b10b-f3396d67f0c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=321153193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.321153193 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2231795060 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8061860000 ps |
| CPU time | 32.85 seconds |
| Started | Jul 12 05:01:40 PM PDT 24 |
| Finished | Jul 12 05:02:44 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-32cb9420-ff67-4f38-a0e1-89dfd7d94d94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2231795060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2231795060 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3319477243 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3780760000 ps |
| CPU time | 13.74 seconds |
| Started | Jul 12 05:01:42 PM PDT 24 |
| Finished | Jul 12 05:02:08 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-54c08621-072f-4bf4-944d-4886c194b2cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319477243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3319477243 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4294821814 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14013240000 ps |
| CPU time | 54.49 seconds |
| Started | Jul 12 05:01:47 PM PDT 24 |
| Finished | Jul 12 05:03:29 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-32a53b7f-fb47-430d-95f4-b07d3c387d13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294821814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4294821814 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.737795220 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13516000000 ps |
| CPU time | 42.58 seconds |
| Started | Jul 12 05:01:52 PM PDT 24 |
| Finished | Jul 12 05:03:12 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-84967cf6-c6af-47c9-86a0-54e23dcca989 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737795220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.737795220 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.520398040 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12944360000 ps |
| CPU time | 43.48 seconds |
| Started | Jul 12 05:01:44 PM PDT 24 |
| Finished | Jul 12 05:03:06 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-2df6190a-4a39-4f53-8a94-dd2cbe6222af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520398040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.520398040 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1046515902 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10600140000 ps |
| CPU time | 36.11 seconds |
| Started | Jul 12 05:01:46 PM PDT 24 |
| Finished | Jul 12 05:02:54 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-218ea831-0d60-40a6-ac85-89895ab94e90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046515902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1046515902 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.14233581 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11396840000 ps |
| CPU time | 42.08 seconds |
| Started | Jul 12 05:01:40 PM PDT 24 |
| Finished | Jul 12 05:03:00 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-8a85dfee-2671-4db4-96fc-d5a417f5023c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14233581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.14233581 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3735355159 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7951500000 ps |
| CPU time | 29.01 seconds |
| Started | Jul 12 05:01:41 PM PDT 24 |
| Finished | Jul 12 05:02:37 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-d778d210-0df0-4700-89fd-b33f8c848c0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735355159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3735355159 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.489023030 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11430320000 ps |
| CPU time | 38.54 seconds |
| Started | Jul 12 05:01:41 PM PDT 24 |
| Finished | Jul 12 05:02:54 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-5c3167c1-b785-4110-a260-07d6b2e033bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489023030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.489023030 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.10559001 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10020440000 ps |
| CPU time | 31.4 seconds |
| Started | Jul 12 05:01:51 PM PDT 24 |
| Finished | Jul 12 05:02:49 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-b147f695-4455-40a6-bdf5-06ef02d754dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10559001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.10559001 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.813492722 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5663700000 ps |
| CPU time | 15.6 seconds |
| Started | Jul 12 05:01:49 PM PDT 24 |
| Finished | Jul 12 05:02:18 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-146aaeaa-0d63-4dba-9ea5-eef75fa96183 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813492722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.813492722 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.4121315714 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6800160000 ps |
| CPU time | 26.58 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:02:39 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-05a277b1-ce0d-4006-8637-88ee8da88f57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121315714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.4121315714 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1432149698 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 14697720000 ps |
| CPU time | 57.3 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:03:40 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-ab320bd1-4a47-4989-af2b-fcc610a63cc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432149698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1432149698 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1095444532 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14033080000 ps |
| CPU time | 50.89 seconds |
| Started | Jul 12 05:01:40 PM PDT 24 |
| Finished | Jul 12 05:03:17 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-a5270f8e-8259-4ebe-a737-9baac0f095ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095444532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1095444532 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3424963441 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13307060000 ps |
| CPU time | 48.04 seconds |
| Started | Jul 12 05:01:47 PM PDT 24 |
| Finished | Jul 12 05:03:18 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-90e0c478-e5c9-4089-af8a-c7982fe2691c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424963441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3424963441 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.801542753 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14470180000 ps |
| CPU time | 55.56 seconds |
| Started | Jul 12 05:01:49 PM PDT 24 |
| Finished | Jul 12 05:03:35 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-898d505a-f369-4d07-bfaa-1658f4779b5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801542753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.801542753 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1979024345 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5757940000 ps |
| CPU time | 24.05 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:02:36 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-4c67eff8-f477-4b59-9376-f67c15ed724c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979024345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1979024345 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3894373304 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11613220000 ps |
| CPU time | 36.88 seconds |
| Started | Jul 12 05:01:49 PM PDT 24 |
| Finished | Jul 12 05:02:59 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-03e0c855-e16e-40db-93b7-c6400bcba2d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894373304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3894373304 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.49885922 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3848340000 ps |
| CPU time | 13.49 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:02:15 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-bdfe6678-49a4-4b22-9c8e-24f6a3a49863 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49885922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.49885922 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3554584255 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13341160000 ps |
| CPU time | 46.41 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:03:16 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-717ea175-695b-4e2d-8617-60b6652095bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554584255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3554584255 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2168689568 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11437760000 ps |
| CPU time | 44.11 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:03:17 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-c1a08a93-d738-4f93-819b-8b8236dba49a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168689568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2168689568 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3779510536 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11073200000 ps |
| CPU time | 37.49 seconds |
| Started | Jul 12 05:01:45 PM PDT 24 |
| Finished | Jul 12 05:02:56 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-9079f1f6-c125-498d-a526-e18ce2ef5283 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779510536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3779510536 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3551004975 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13215920000 ps |
| CPU time | 45.59 seconds |
| Started | Jul 12 05:01:49 PM PDT 24 |
| Finished | Jul 12 05:03:16 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-d86d621f-2a06-442e-8358-409911102997 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551004975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3551004975 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1175734209 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11554320000 ps |
| CPU time | 43.98 seconds |
| Started | Jul 12 05:01:49 PM PDT 24 |
| Finished | Jul 12 05:03:17 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-386b4601-0c43-4f8c-a2d9-fb19c5274330 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1175734209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1175734209 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3583927304 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10593320000 ps |
| CPU time | 42.94 seconds |
| Started | Jul 12 05:01:43 PM PDT 24 |
| Finished | Jul 12 05:03:07 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-f185c26f-330a-4801-8794-9c4d42e6f912 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583927304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3583927304 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2119060761 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10649120000 ps |
| CPU time | 37.25 seconds |
| Started | Jul 12 05:01:50 PM PDT 24 |
| Finished | Jul 12 05:03:02 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-a52327ee-0e11-45b1-95fb-8e7f90764065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2119060761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2119060761 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.229090483 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4905440000 ps |
| CPU time | 17.73 seconds |
| Started | Jul 12 05:01:52 PM PDT 24 |
| Finished | Jul 12 05:02:26 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-2e59aa9b-6e02-4139-a533-d22c13a70979 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229090483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.229090483 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4258016216 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15243940000 ps |
| CPU time | 59.02 seconds |
| Started | Jul 12 05:01:51 PM PDT 24 |
| Finished | Jul 12 05:03:45 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e90ca614-e0a8-459a-b505-ec9b72aef6b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258016216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4258016216 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4205111051 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7158520000 ps |
| CPU time | 27.43 seconds |
| Started | Jul 12 05:01:46 PM PDT 24 |
| Finished | Jul 12 05:02:39 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-2573dde5-f860-4391-954d-033e2c47765b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205111051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4205111051 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2664772663 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11060800000 ps |
| CPU time | 34.03 seconds |
| Started | Jul 12 05:01:51 PM PDT 24 |
| Finished | Jul 12 05:02:55 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-8a087ae5-e302-4c23-b07b-245c99277d49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664772663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2664772663 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.472066151 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12276000000 ps |
| CPU time | 46.26 seconds |
| Started | Jul 12 05:01:52 PM PDT 24 |
| Finished | Jul 12 05:03:23 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-93ea30ee-d9e2-4451-b217-14d46e41f342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472066151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.472066151 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.944972976 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4530340000 ps |
| CPU time | 15.82 seconds |
| Started | Jul 12 05:01:51 PM PDT 24 |
| Finished | Jul 12 05:02:20 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-33fe7b4d-48a9-43b4-acfe-2f513380a6b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944972976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.944972976 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3392306939 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4974260000 ps |
| CPU time | 16.46 seconds |
| Started | Jul 12 05:01:50 PM PDT 24 |
| Finished | Jul 12 05:02:22 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-72da6552-0955-4447-869b-75da88c2f646 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392306939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3392306939 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3723547480 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9870400000 ps |
| CPU time | 37.8 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:03:00 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-336ace17-b4b5-49b2-90f4-f9f679111dc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723547480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3723547480 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3100188121 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5329520000 ps |
| CPU time | 21.49 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:02:30 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-58bfd922-2b06-460f-9765-e63139b246cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100188121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3100188121 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3171534866 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8600640000 ps |
| CPU time | 35 seconds |
| Started | Jul 12 05:01:44 PM PDT 24 |
| Finished | Jul 12 05:02:52 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-aa1d1079-5d9e-4602-90c4-510ed3856b41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171534866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3171534866 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2834798547 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9277680000 ps |
| CPU time | 28.91 seconds |
| Started | Jul 12 05:01:51 PM PDT 24 |
| Finished | Jul 12 05:02:45 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-1a223058-be82-40ee-bc93-7addde4db66f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834798547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2834798547 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2482736522 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12107980000 ps |
| CPU time | 47.59 seconds |
| Started | Jul 12 05:01:48 PM PDT 24 |
| Finished | Jul 12 05:03:21 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-1805ba7d-3166-4baa-ad26-c87a8f0e6462 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482736522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2482736522 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2326707699 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14601620000 ps |
| CPU time | 49.32 seconds |
| Started | Jul 12 05:01:45 PM PDT 24 |
| Finished | Jul 12 05:03:16 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-86295316-d749-44d6-b77c-471d8e9b9fd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326707699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2326707699 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.881534409 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4818020000 ps |
| CPU time | 23.68 seconds |
| Started | Jul 12 05:01:49 PM PDT 24 |
| Finished | Jul 12 05:02:36 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-6de0329f-0dc6-4e98-8920-3603ea191230 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881534409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.881534409 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |