| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3944480192 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3167350413 |
| /workspace/coverage/default/1.prim_present_test.1340105538 |
| /workspace/coverage/default/11.prim_present_test.777070661 |
| /workspace/coverage/default/12.prim_present_test.3022841425 |
| /workspace/coverage/default/13.prim_present_test.2286263887 |
| /workspace/coverage/default/14.prim_present_test.2652052891 |
| /workspace/coverage/default/15.prim_present_test.3389239204 |
| /workspace/coverage/default/16.prim_present_test.3158963708 |
| /workspace/coverage/default/17.prim_present_test.1159290027 |
| /workspace/coverage/default/18.prim_present_test.1483898453 |
| /workspace/coverage/default/19.prim_present_test.844040858 |
| /workspace/coverage/default/2.prim_present_test.2163211010 |
| /workspace/coverage/default/20.prim_present_test.1843813541 |
| /workspace/coverage/default/21.prim_present_test.1828464732 |
| /workspace/coverage/default/22.prim_present_test.518049616 |
| /workspace/coverage/default/23.prim_present_test.2758270609 |
| /workspace/coverage/default/24.prim_present_test.152526106 |
| /workspace/coverage/default/25.prim_present_test.1208200757 |
| /workspace/coverage/default/26.prim_present_test.4107413521 |
| /workspace/coverage/default/27.prim_present_test.4145001810 |
| /workspace/coverage/default/28.prim_present_test.64601085 |
| /workspace/coverage/default/29.prim_present_test.524619592 |
| /workspace/coverage/default/3.prim_present_test.3253344644 |
| /workspace/coverage/default/30.prim_present_test.3737523822 |
| /workspace/coverage/default/31.prim_present_test.2148723948 |
| /workspace/coverage/default/32.prim_present_test.2348147240 |
| /workspace/coverage/default/33.prim_present_test.3903412685 |
| /workspace/coverage/default/34.prim_present_test.1074759775 |
| /workspace/coverage/default/35.prim_present_test.1501855782 |
| /workspace/coverage/default/36.prim_present_test.1077769948 |
| /workspace/coverage/default/37.prim_present_test.1327778448 |
| /workspace/coverage/default/38.prim_present_test.963577609 |
| /workspace/coverage/default/39.prim_present_test.1227936570 |
| /workspace/coverage/default/4.prim_present_test.2595317055 |
| /workspace/coverage/default/40.prim_present_test.4134863051 |
| /workspace/coverage/default/41.prim_present_test.1311169427 |
| /workspace/coverage/default/42.prim_present_test.2668156592 |
| /workspace/coverage/default/43.prim_present_test.279326906 |
| /workspace/coverage/default/44.prim_present_test.432779556 |
| /workspace/coverage/default/45.prim_present_test.2591515155 |
| /workspace/coverage/default/46.prim_present_test.951400201 |
| /workspace/coverage/default/47.prim_present_test.4242698203 |
| /workspace/coverage/default/48.prim_present_test.332940472 |
| /workspace/coverage/default/49.prim_present_test.2659943969 |
| /workspace/coverage/default/5.prim_present_test.119691406 |
| /workspace/coverage/default/6.prim_present_test.651334514 |
| /workspace/coverage/default/7.prim_present_test.1822274560 |
| /workspace/coverage/default/8.prim_present_test.2351025176 |
| /workspace/coverage/default/9.prim_present_test.2964384494 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_present_test.2964384494 | Jul 13 05:50:00 PM PDT 24 | Jul 13 05:51:45 PM PDT 24 | 13421140000 ps | ||
| T2 | /workspace/coverage/default/14.prim_present_test.2652052891 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:50:39 PM PDT 24 | 3940100000 ps | ||
| T3 | /workspace/coverage/default/38.prim_present_test.963577609 | Jul 13 05:50:06 PM PDT 24 | Jul 13 05:52:10 PM PDT 24 | 14415620000 ps | ||
| T4 | /workspace/coverage/default/10.prim_present_test.3944480192 | Jul 13 05:50:01 PM PDT 24 | Jul 13 05:50:40 PM PDT 24 | 4266220000 ps | ||
| T5 | /workspace/coverage/default/21.prim_present_test.1828464732 | Jul 13 05:50:11 PM PDT 24 | Jul 13 05:51:35 PM PDT 24 | 10972140000 ps | ||
| T6 | /workspace/coverage/default/43.prim_present_test.279326906 | Jul 13 05:50:06 PM PDT 24 | Jul 13 05:51:42 PM PDT 24 | 12556860000 ps | ||
| T7 | /workspace/coverage/default/20.prim_present_test.1843813541 | Jul 13 05:50:07 PM PDT 24 | Jul 13 05:51:06 PM PDT 24 | 6648260000 ps | ||
| T8 | /workspace/coverage/default/22.prim_present_test.518049616 | Jul 13 05:50:06 PM PDT 24 | Jul 13 05:51:48 PM PDT 24 | 12860660000 ps | ||
| T9 | /workspace/coverage/default/13.prim_present_test.2286263887 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:50:54 PM PDT 24 | 6795200000 ps | ||
| T10 | /workspace/coverage/default/8.prim_present_test.2351025176 | Jul 13 05:50:01 PM PDT 24 | Jul 13 05:51:38 PM PDT 24 | 11068240000 ps | ||
| T11 | /workspace/coverage/default/0.prim_present_test.3167350413 | Jul 13 05:50:00 PM PDT 24 | Jul 13 05:51:49 PM PDT 24 | 13582960000 ps | ||
| T12 | /workspace/coverage/default/1.prim_present_test.1340105538 | Jul 13 05:50:00 PM PDT 24 | Jul 13 05:51:34 PM PDT 24 | 12205320000 ps | ||
| T13 | /workspace/coverage/default/41.prim_present_test.1311169427 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:51:15 PM PDT 24 | 7562760000 ps | ||
| T14 | /workspace/coverage/default/31.prim_present_test.2148723948 | Jul 13 05:50:10 PM PDT 24 | Jul 13 05:51:33 PM PDT 24 | 10073760000 ps | ||
| T15 | /workspace/coverage/default/26.prim_present_test.4107413521 | Jul 13 05:50:05 PM PDT 24 | Jul 13 05:50:56 PM PDT 24 | 6380420000 ps | ||
| T16 | /workspace/coverage/default/49.prim_present_test.2659943969 | Jul 13 05:50:13 PM PDT 24 | Jul 13 05:51:09 PM PDT 24 | 6417620000 ps | ||
| T17 | /workspace/coverage/default/40.prim_present_test.4134863051 | Jul 13 05:50:10 PM PDT 24 | Jul 13 05:52:07 PM PDT 24 | 14136620000 ps | ||
| T18 | /workspace/coverage/default/39.prim_present_test.1227936570 | Jul 13 05:50:07 PM PDT 24 | Jul 13 05:51:46 PM PDT 24 | 12577940000 ps | ||
| T19 | /workspace/coverage/default/6.prim_present_test.651334514 | Jul 13 05:50:00 PM PDT 24 | Jul 13 05:50:43 PM PDT 24 | 4443540000 ps | ||
| T20 | /workspace/coverage/default/11.prim_present_test.777070661 | Jul 13 05:50:06 PM PDT 24 | Jul 13 05:51:56 PM PDT 24 | 13218400000 ps | ||
| T21 | /workspace/coverage/default/46.prim_present_test.951400201 | Jul 13 05:50:09 PM PDT 24 | Jul 13 05:51:23 PM PDT 24 | 9928060000 ps | ||
| T22 | /workspace/coverage/default/48.prim_present_test.332940472 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:52:03 PM PDT 24 | 14948200000 ps | ||
| T23 | /workspace/coverage/default/30.prim_present_test.3737523822 | Jul 13 05:50:07 PM PDT 24 | Jul 13 05:51:09 PM PDT 24 | 6827440000 ps | ||
| T24 | /workspace/coverage/default/12.prim_present_test.3022841425 | Jul 13 05:50:07 PM PDT 24 | Jul 13 05:52:17 PM PDT 24 | 15295400000 ps | ||
| T25 | /workspace/coverage/default/17.prim_present_test.1159290027 | Jul 13 05:50:06 PM PDT 24 | Jul 13 05:51:29 PM PDT 24 | 10417240000 ps | ||
| T26 | /workspace/coverage/default/18.prim_present_test.1483898453 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:50:38 PM PDT 24 | 3607780000 ps | ||
| T27 | /workspace/coverage/default/42.prim_present_test.2668156592 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:51:59 PM PDT 24 | 11965380000 ps | ||
| T28 | /workspace/coverage/default/5.prim_present_test.119691406 | Jul 13 05:50:01 PM PDT 24 | Jul 13 05:51:45 PM PDT 24 | 11952360000 ps | ||
| T29 | /workspace/coverage/default/45.prim_present_test.2591515155 | Jul 13 05:50:09 PM PDT 24 | Jul 13 05:50:44 PM PDT 24 | 4601020000 ps | ||
| T30 | /workspace/coverage/default/44.prim_present_test.432779556 | Jul 13 05:50:10 PM PDT 24 | Jul 13 05:51:32 PM PDT 24 | 8490280000 ps | ||
| T31 | /workspace/coverage/default/19.prim_present_test.844040858 | Jul 13 05:50:13 PM PDT 24 | Jul 13 05:52:02 PM PDT 24 | 13334340000 ps | ||
| T32 | /workspace/coverage/default/36.prim_present_test.1077769948 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:51:35 PM PDT 24 | 11560520000 ps | ||
| T33 | /workspace/coverage/default/47.prim_present_test.4242698203 | Jul 13 05:50:06 PM PDT 24 | Jul 13 05:51:30 PM PDT 24 | 13797480000 ps | ||
| T34 | /workspace/coverage/default/7.prim_present_test.1822274560 | Jul 13 05:50:01 PM PDT 24 | Jul 13 05:51:34 PM PDT 24 | 11724820000 ps | ||
| T35 | /workspace/coverage/default/29.prim_present_test.524619592 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:51:34 PM PDT 24 | 11447680000 ps | ||
| T36 | /workspace/coverage/default/3.prim_present_test.3253344644 | Jul 13 05:49:59 PM PDT 24 | Jul 13 05:51:39 PM PDT 24 | 10476140000 ps | ||
| T37 | /workspace/coverage/default/35.prim_present_test.1501855782 | Jul 13 05:50:10 PM PDT 24 | Jul 13 05:51:14 PM PDT 24 | 7688620000 ps | ||
| T38 | /workspace/coverage/default/23.prim_present_test.2758270609 | Jul 13 05:50:07 PM PDT 24 | Jul 13 05:51:30 PM PDT 24 | 9642860000 ps | ||
| T39 | /workspace/coverage/default/34.prim_present_test.1074759775 | Jul 13 05:50:10 PM PDT 24 | Jul 13 05:51:15 PM PDT 24 | 10695000000 ps | ||
| T40 | /workspace/coverage/default/25.prim_present_test.1208200757 | Jul 13 05:50:07 PM PDT 24 | Jul 13 05:52:22 PM PDT 24 | 14783900000 ps | ||
| T41 | /workspace/coverage/default/24.prim_present_test.152526106 | Jul 13 05:50:07 PM PDT 24 | Jul 13 05:50:33 PM PDT 24 | 3286000000 ps | ||
| T42 | /workspace/coverage/default/15.prim_present_test.3389239204 | Jul 13 05:50:07 PM PDT 24 | Jul 13 05:51:52 PM PDT 24 | 12688300000 ps | ||
| T43 | /workspace/coverage/default/37.prim_present_test.1327778448 | Jul 13 05:50:06 PM PDT 24 | Jul 13 05:51:23 PM PDT 24 | 9439500000 ps | ||
| T44 | /workspace/coverage/default/16.prim_present_test.3158963708 | Jul 13 05:50:09 PM PDT 24 | Jul 13 05:51:44 PM PDT 24 | 10053920000 ps | ||
| T45 | /workspace/coverage/default/27.prim_present_test.4145001810 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:51:39 PM PDT 24 | 11374520000 ps | ||
| T46 | /workspace/coverage/default/28.prim_present_test.64601085 | Jul 13 05:50:10 PM PDT 24 | Jul 13 05:50:45 PM PDT 24 | 4862040000 ps | ||
| T47 | /workspace/coverage/default/32.prim_present_test.2348147240 | Jul 13 05:50:13 PM PDT 24 | Jul 13 05:52:09 PM PDT 24 | 13821040000 ps | ||
| T48 | /workspace/coverage/default/33.prim_present_test.3903412685 | Jul 13 05:50:08 PM PDT 24 | Jul 13 05:51:35 PM PDT 24 | 10323000000 ps | ||
| T49 | /workspace/coverage/default/2.prim_present_test.2163211010 | Jul 13 05:50:01 PM PDT 24 | Jul 13 05:51:06 PM PDT 24 | 6982440000 ps | ||
| T50 | /workspace/coverage/default/4.prim_present_test.2595317055 | Jul 13 05:50:00 PM PDT 24 | Jul 13 05:51:26 PM PDT 24 | 13773300000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3944480192 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4266220000 ps |
| CPU time | 19.28 seconds |
| Started | Jul 13 05:50:01 PM PDT 24 |
| Finished | Jul 13 05:50:40 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-068ebaf4-346b-4960-b23b-75d903d2f607 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944480192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3944480192 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3167350413 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13582960000 ps |
| CPU time | 56.15 seconds |
| Started | Jul 13 05:50:00 PM PDT 24 |
| Finished | Jul 13 05:51:49 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-678d41c9-47c6-47b5-99fb-fba785c7dc97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3167350413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3167350413 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1340105538 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12205320000 ps |
| CPU time | 48.62 seconds |
| Started | Jul 13 05:50:00 PM PDT 24 |
| Finished | Jul 13 05:51:34 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-1660c989-8e29-405a-8607-f33931bcd5b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340105538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1340105538 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.777070661 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13218400000 ps |
| CPU time | 55.87 seconds |
| Started | Jul 13 05:50:06 PM PDT 24 |
| Finished | Jul 13 05:51:56 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-c611bd86-8a09-44eb-9a79-559c829fb3d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777070661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.777070661 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3022841425 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 15295400000 ps |
| CPU time | 65.67 seconds |
| Started | Jul 13 05:50:07 PM PDT 24 |
| Finished | Jul 13 05:52:17 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-77fad96d-1dd6-483e-9464-58a5d408c578 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022841425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3022841425 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2286263887 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6795200000 ps |
| CPU time | 24.67 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:50:54 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-e532745e-0da9-4b94-bdb0-a4faa4a3cdd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286263887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2286263887 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2652052891 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3940100000 ps |
| CPU time | 16.08 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:50:39 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-99f638c1-04d2-4a11-b93f-3318d19e30b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652052891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2652052891 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3389239204 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12688300000 ps |
| CPU time | 53.39 seconds |
| Started | Jul 13 05:50:07 PM PDT 24 |
| Finished | Jul 13 05:51:52 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-756c5282-cf89-499e-abb5-5e48f1881288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389239204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3389239204 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3158963708 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10053920000 ps |
| CPU time | 45.79 seconds |
| Started | Jul 13 05:50:09 PM PDT 24 |
| Finished | Jul 13 05:51:44 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-7e3cadba-87e6-4596-8672-1cd26d2c619c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158963708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3158963708 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1159290027 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10417240000 ps |
| CPU time | 42.43 seconds |
| Started | Jul 13 05:50:06 PM PDT 24 |
| Finished | Jul 13 05:51:29 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-9bc98f90-62e5-43c6-9ee8-746fe82e35f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159290027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1159290027 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1483898453 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3607780000 ps |
| CPU time | 14.88 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:50:38 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-b904aaf3-0107-4004-b546-9193d4230788 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483898453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1483898453 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.844040858 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13334340000 ps |
| CPU time | 55.28 seconds |
| Started | Jul 13 05:50:13 PM PDT 24 |
| Finished | Jul 13 05:52:02 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-642332ae-2263-4a1d-8231-8523a96d6915 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844040858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.844040858 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2163211010 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6982440000 ps |
| CPU time | 32.4 seconds |
| Started | Jul 13 05:50:01 PM PDT 24 |
| Finished | Jul 13 05:51:06 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-f7f41dd0-f75f-406b-8644-d7b51cdaba6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163211010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2163211010 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1843813541 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6648260000 ps |
| CPU time | 29.94 seconds |
| Started | Jul 13 05:50:07 PM PDT 24 |
| Finished | Jul 13 05:51:06 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-a4027e79-b617-41c4-baee-7d1a1928ec69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1843813541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1843813541 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1828464732 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 10972140000 ps |
| CPU time | 44.53 seconds |
| Started | Jul 13 05:50:11 PM PDT 24 |
| Finished | Jul 13 05:51:35 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-508ae868-7de0-4be1-bcc8-c01c8cdffae6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828464732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1828464732 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.518049616 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12860660000 ps |
| CPU time | 52.75 seconds |
| Started | Jul 13 05:50:06 PM PDT 24 |
| Finished | Jul 13 05:51:48 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-32fc1c99-e701-4db1-b137-c8fa33520f6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=518049616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.518049616 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2758270609 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9642860000 ps |
| CPU time | 41.92 seconds |
| Started | Jul 13 05:50:07 PM PDT 24 |
| Finished | Jul 13 05:51:30 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-74f3ff1e-1b19-4158-b52b-7fae536a0870 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758270609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2758270609 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.152526106 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3286000000 ps |
| CPU time | 13.61 seconds |
| Started | Jul 13 05:50:07 PM PDT 24 |
| Finished | Jul 13 05:50:33 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-2b2e8c09-12c1-4baa-94a9-dc906dbbc3fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152526106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.152526106 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1208200757 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14783900000 ps |
| CPU time | 68.13 seconds |
| Started | Jul 13 05:50:07 PM PDT 24 |
| Finished | Jul 13 05:52:22 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-b98d0f2e-a102-4bc7-af2e-ef30961dcbb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208200757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1208200757 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.4107413521 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6380420000 ps |
| CPU time | 26.69 seconds |
| Started | Jul 13 05:50:05 PM PDT 24 |
| Finished | Jul 13 05:50:56 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-932abe8f-b671-4ae1-b168-de9209423e1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4107413521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.4107413521 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.4145001810 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11374520000 ps |
| CPU time | 45.85 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:51:39 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-eee135a4-7e90-4493-b3cc-502f4099dc77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145001810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.4145001810 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.64601085 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4862040000 ps |
| CPU time | 18.02 seconds |
| Started | Jul 13 05:50:10 PM PDT 24 |
| Finished | Jul 13 05:50:45 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-0612a4d9-3e56-4539-b3dd-6950b48676bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64601085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.64601085 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.524619592 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11447680000 ps |
| CPU time | 45.01 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:51:34 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-9a8b5851-a570-46fe-a0a7-c04ad55b086c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=524619592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.524619592 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3253344644 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10476140000 ps |
| CPU time | 48.36 seconds |
| Started | Jul 13 05:49:59 PM PDT 24 |
| Finished | Jul 13 05:51:39 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-9d75f911-4740-4b7f-a9d6-53dfa48f265e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253344644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3253344644 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3737523822 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6827440000 ps |
| CPU time | 31.06 seconds |
| Started | Jul 13 05:50:07 PM PDT 24 |
| Finished | Jul 13 05:51:09 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-2768cc66-d56b-4a40-a00d-14b72f810110 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737523822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3737523822 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2148723948 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10073760000 ps |
| CPU time | 41.95 seconds |
| Started | Jul 13 05:50:10 PM PDT 24 |
| Finished | Jul 13 05:51:33 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-8e70db0f-5fb1-4e09-8f4b-6a2cbf0f6155 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148723948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2148723948 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2348147240 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13821040000 ps |
| CPU time | 58.39 seconds |
| Started | Jul 13 05:50:13 PM PDT 24 |
| Finished | Jul 13 05:52:09 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-0d5e36fa-5876-4b36-939e-60debf9ffa63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348147240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2348147240 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3903412685 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10323000000 ps |
| CPU time | 45.08 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:51:35 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-d4bbf574-9d99-4903-bdee-972826b962e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903412685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3903412685 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1074759775 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10695000000 ps |
| CPU time | 34.75 seconds |
| Started | Jul 13 05:50:10 PM PDT 24 |
| Finished | Jul 13 05:51:15 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-2f046956-3cd9-42af-86dd-c6fb4dbc62f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074759775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1074759775 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1501855782 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 7688620000 ps |
| CPU time | 32.26 seconds |
| Started | Jul 13 05:50:10 PM PDT 24 |
| Finished | Jul 13 05:51:14 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-2bbbe5cb-bc99-4ba8-997f-f1c974e77a91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1501855782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1501855782 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1077769948 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 11560520000 ps |
| CPU time | 45.08 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:51:35 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-b5824078-6c2b-4f87-9928-2c185baef79d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077769948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1077769948 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1327778448 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 9439500000 ps |
| CPU time | 40.06 seconds |
| Started | Jul 13 05:50:06 PM PDT 24 |
| Finished | Jul 13 05:51:23 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-a783d9e4-69ae-493c-b9a1-a07025e7378f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327778448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1327778448 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.963577609 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 14415620000 ps |
| CPU time | 62.12 seconds |
| Started | Jul 13 05:50:06 PM PDT 24 |
| Finished | Jul 13 05:52:10 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-5ba03fe6-acc0-4a56-843e-4435fcf133e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963577609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.963577609 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1227936570 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12577940000 ps |
| CPU time | 50.6 seconds |
| Started | Jul 13 05:50:07 PM PDT 24 |
| Finished | Jul 13 05:51:46 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e9f3c9c3-437d-4b88-8fa5-bc4637f1bc14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227936570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1227936570 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2595317055 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13773300000 ps |
| CPU time | 45.58 seconds |
| Started | Jul 13 05:50:00 PM PDT 24 |
| Finished | Jul 13 05:51:26 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-17508609-e853-4bb6-a8ee-ff0f72f214fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595317055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2595317055 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4134863051 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14136620000 ps |
| CPU time | 59 seconds |
| Started | Jul 13 05:50:10 PM PDT 24 |
| Finished | Jul 13 05:52:07 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-45969283-2b3f-4a49-b659-eded0d10770c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134863051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4134863051 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1311169427 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7562760000 ps |
| CPU time | 33.37 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:51:15 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-3a102345-74f3-451b-8d6c-e6b835b7bd08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311169427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1311169427 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2668156592 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11965380000 ps |
| CPU time | 55 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:51:59 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-6afdea73-76c7-4a31-9bec-29769c5c702c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668156592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2668156592 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.279326906 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12556860000 ps |
| CPU time | 50.17 seconds |
| Started | Jul 13 05:50:06 PM PDT 24 |
| Finished | Jul 13 05:51:42 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-1cde5b0c-a443-42ad-b52c-b174e998ca5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279326906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.279326906 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.432779556 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8490280000 ps |
| CPU time | 39.98 seconds |
| Started | Jul 13 05:50:10 PM PDT 24 |
| Finished | Jul 13 05:51:32 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-6d15cd7f-832b-4205-b000-d1d8e8452d1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432779556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.432779556 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2591515155 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4601020000 ps |
| CPU time | 18.55 seconds |
| Started | Jul 13 05:50:09 PM PDT 24 |
| Finished | Jul 13 05:50:44 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-b3e2f78e-2d45-436d-8aa4-79d13d7c1c20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591515155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2591515155 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.951400201 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9928060000 ps |
| CPU time | 38.97 seconds |
| Started | Jul 13 05:50:09 PM PDT 24 |
| Finished | Jul 13 05:51:23 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-3b0a9c1f-47b6-47be-a88a-d24d0bf3ba0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951400201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.951400201 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4242698203 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13797480000 ps |
| CPU time | 44.47 seconds |
| Started | Jul 13 05:50:06 PM PDT 24 |
| Finished | Jul 13 05:51:30 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-f3e7b9ab-245d-44b6-86da-1ef2a29ccc57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242698203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4242698203 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.332940472 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14948200000 ps |
| CPU time | 58.36 seconds |
| Started | Jul 13 05:50:08 PM PDT 24 |
| Finished | Jul 13 05:52:03 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-a6225ed6-48a5-4d23-bebe-d00b443d1a01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332940472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.332940472 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2659943969 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6417620000 ps |
| CPU time | 27.73 seconds |
| Started | Jul 13 05:50:13 PM PDT 24 |
| Finished | Jul 13 05:51:09 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-44c17c82-cfe8-41e8-ad6a-f70d841fd11f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659943969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2659943969 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.119691406 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11952360000 ps |
| CPU time | 52.27 seconds |
| Started | Jul 13 05:50:01 PM PDT 24 |
| Finished | Jul 13 05:51:45 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-da254b87-e8c1-4700-a487-ac8a2b3217ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119691406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.119691406 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.651334514 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4443540000 ps |
| CPU time | 21.43 seconds |
| Started | Jul 13 05:50:00 PM PDT 24 |
| Finished | Jul 13 05:50:43 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-27dbba07-68c0-4e31-82ce-805d73553ab8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651334514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.651334514 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1822274560 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11724820000 ps |
| CPU time | 47.85 seconds |
| Started | Jul 13 05:50:01 PM PDT 24 |
| Finished | Jul 13 05:51:34 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-4009913d-3fe0-4baf-917c-737ceb262088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822274560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1822274560 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2351025176 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11068240000 ps |
| CPU time | 48.29 seconds |
| Started | Jul 13 05:50:01 PM PDT 24 |
| Finished | Jul 13 05:51:38 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-03f6cc4f-5636-4997-aedb-2f91c14bdde4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351025176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2351025176 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2964384494 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13421140000 ps |
| CPU time | 53.65 seconds |
| Started | Jul 13 05:50:00 PM PDT 24 |
| Finished | Jul 13 05:51:45 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-b1bd9116-35b3-421a-a435-b10269bfed70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2964384494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2964384494 |
| Directory | /workspace/9.prim_present_test/latest |
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