| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.1006008213 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.4262598263 |
| /workspace/coverage/default/10.prim_present_test.2735341734 |
| /workspace/coverage/default/11.prim_present_test.1338666329 |
| /workspace/coverage/default/12.prim_present_test.2555130178 |
| /workspace/coverage/default/13.prim_present_test.491007741 |
| /workspace/coverage/default/14.prim_present_test.3567003417 |
| /workspace/coverage/default/15.prim_present_test.3750037908 |
| /workspace/coverage/default/16.prim_present_test.1562580665 |
| /workspace/coverage/default/17.prim_present_test.2334293808 |
| /workspace/coverage/default/18.prim_present_test.2674661899 |
| /workspace/coverage/default/19.prim_present_test.68248700 |
| /workspace/coverage/default/2.prim_present_test.4214606231 |
| /workspace/coverage/default/20.prim_present_test.3876021795 |
| /workspace/coverage/default/21.prim_present_test.1834645883 |
| /workspace/coverage/default/22.prim_present_test.3750200765 |
| /workspace/coverage/default/23.prim_present_test.2440990685 |
| /workspace/coverage/default/24.prim_present_test.680961369 |
| /workspace/coverage/default/25.prim_present_test.244557370 |
| /workspace/coverage/default/26.prim_present_test.1666779229 |
| /workspace/coverage/default/27.prim_present_test.1319677289 |
| /workspace/coverage/default/28.prim_present_test.1682522103 |
| /workspace/coverage/default/29.prim_present_test.1528428774 |
| /workspace/coverage/default/3.prim_present_test.972741175 |
| /workspace/coverage/default/30.prim_present_test.2765553148 |
| /workspace/coverage/default/31.prim_present_test.88400248 |
| /workspace/coverage/default/32.prim_present_test.405968842 |
| /workspace/coverage/default/33.prim_present_test.2268437879 |
| /workspace/coverage/default/34.prim_present_test.777764771 |
| /workspace/coverage/default/35.prim_present_test.398690866 |
| /workspace/coverage/default/36.prim_present_test.3135877468 |
| /workspace/coverage/default/37.prim_present_test.3220992531 |
| /workspace/coverage/default/38.prim_present_test.1192349103 |
| /workspace/coverage/default/39.prim_present_test.1446221084 |
| /workspace/coverage/default/4.prim_present_test.2825652918 |
| /workspace/coverage/default/40.prim_present_test.3070187347 |
| /workspace/coverage/default/41.prim_present_test.2732364877 |
| /workspace/coverage/default/42.prim_present_test.2800865589 |
| /workspace/coverage/default/43.prim_present_test.946753949 |
| /workspace/coverage/default/44.prim_present_test.499023822 |
| /workspace/coverage/default/45.prim_present_test.1922104311 |
| /workspace/coverage/default/46.prim_present_test.1933516216 |
| /workspace/coverage/default/47.prim_present_test.3656990924 |
| /workspace/coverage/default/48.prim_present_test.58779626 |
| /workspace/coverage/default/49.prim_present_test.3196394361 |
| /workspace/coverage/default/5.prim_present_test.703658203 |
| /workspace/coverage/default/6.prim_present_test.666878346 |
| /workspace/coverage/default/7.prim_present_test.959453340 |
| /workspace/coverage/default/8.prim_present_test.910630336 |
| /workspace/coverage/default/9.prim_present_test.381053522 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/47.prim_present_test.3656990924 | Jul 14 06:43:24 PM PDT 24 | Jul 14 06:44:47 PM PDT 24 | 12752160000 ps | ||
| T2 | /workspace/coverage/default/29.prim_present_test.1528428774 | Jul 14 06:43:25 PM PDT 24 | Jul 14 06:44:21 PM PDT 24 | 8329700000 ps | ||
| T3 | /workspace/coverage/default/22.prim_present_test.3750200765 | Jul 14 06:43:19 PM PDT 24 | Jul 14 06:44:35 PM PDT 24 | 11748380000 ps | ||
| T4 | /workspace/coverage/default/45.prim_present_test.1922104311 | Jul 14 06:43:22 PM PDT 24 | Jul 14 06:44:15 PM PDT 24 | 8726500000 ps | ||
| T5 | /workspace/coverage/default/27.prim_present_test.1319677289 | Jul 14 06:43:25 PM PDT 24 | Jul 14 06:44:01 PM PDT 24 | 5057340000 ps | ||
| T6 | /workspace/coverage/default/21.prim_present_test.1834645883 | Jul 14 06:43:23 PM PDT 24 | Jul 14 06:45:12 PM PDT 24 | 14574340000 ps | ||
| T7 | /workspace/coverage/default/49.prim_present_test.3196394361 | Jul 14 06:43:24 PM PDT 24 | Jul 14 06:45:20 PM PDT 24 | 15449780000 ps | ||
| T8 | /workspace/coverage/default/14.prim_present_test.3567003417 | Jul 14 06:43:16 PM PDT 24 | Jul 14 06:44:20 PM PDT 24 | 8909400000 ps | ||
| T9 | /workspace/coverage/default/0.prim_present_test.1006008213 | Jul 14 06:43:22 PM PDT 24 | Jul 14 06:44:27 PM PDT 24 | 8299940000 ps | ||
| T10 | /workspace/coverage/default/18.prim_present_test.2674661899 | Jul 14 06:43:23 PM PDT 24 | Jul 14 06:43:53 PM PDT 24 | 3538340000 ps | ||
| T11 | /workspace/coverage/default/31.prim_present_test.88400248 | Jul 14 06:43:23 PM PDT 24 | Jul 14 06:44:50 PM PDT 24 | 10838840000 ps | ||
| T12 | /workspace/coverage/default/11.prim_present_test.1338666329 | Jul 14 06:43:18 PM PDT 24 | Jul 14 06:44:00 PM PDT 24 | 5650680000 ps | ||
| T13 | /workspace/coverage/default/48.prim_present_test.58779626 | Jul 14 06:43:25 PM PDT 24 | Jul 14 06:43:49 PM PDT 24 | 3228340000 ps | ||
| T14 | /workspace/coverage/default/34.prim_present_test.777764771 | Jul 14 06:43:25 PM PDT 24 | Jul 14 06:44:11 PM PDT 24 | 6276880000 ps | ||
| T15 | /workspace/coverage/default/42.prim_present_test.2800865589 | Jul 14 06:43:27 PM PDT 24 | Jul 14 06:44:22 PM PDT 24 | 8942260000 ps | ||
| T16 | /workspace/coverage/default/25.prim_present_test.244557370 | Jul 14 06:43:22 PM PDT 24 | Jul 14 06:43:53 PM PDT 24 | 4016360000 ps | ||
| T17 | /workspace/coverage/default/30.prim_present_test.2765553148 | Jul 14 06:43:27 PM PDT 24 | Jul 14 06:44:51 PM PDT 24 | 12334900000 ps | ||
| T18 | /workspace/coverage/default/7.prim_present_test.959453340 | Jul 14 06:43:18 PM PDT 24 | Jul 14 06:44:33 PM PDT 24 | 11659100000 ps | ||
| T19 | /workspace/coverage/default/6.prim_present_test.666878346 | Jul 14 06:43:19 PM PDT 24 | Jul 14 06:44:34 PM PDT 24 | 8992480000 ps | ||
| T20 | /workspace/coverage/default/23.prim_present_test.2440990685 | Jul 14 06:43:15 PM PDT 24 | Jul 14 06:44:28 PM PDT 24 | 11002520000 ps | ||
| T21 | /workspace/coverage/default/19.prim_present_test.68248700 | Jul 14 06:43:17 PM PDT 24 | Jul 14 06:44:21 PM PDT 24 | 9056960000 ps | ||
| T22 | /workspace/coverage/default/37.prim_present_test.3220992531 | Jul 14 06:43:23 PM PDT 24 | Jul 14 06:44:12 PM PDT 24 | 6909900000 ps | ||
| T23 | /workspace/coverage/default/17.prim_present_test.2334293808 | Jul 14 06:43:19 PM PDT 24 | Jul 14 06:43:56 PM PDT 24 | 5030680000 ps | ||
| T24 | /workspace/coverage/default/13.prim_present_test.491007741 | Jul 14 06:43:15 PM PDT 24 | Jul 14 06:44:29 PM PDT 24 | 11794260000 ps | ||
| T25 | /workspace/coverage/default/4.prim_present_test.2825652918 | Jul 14 06:43:18 PM PDT 24 | Jul 14 06:44:49 PM PDT 24 | 13483140000 ps | ||
| T26 | /workspace/coverage/default/41.prim_present_test.2732364877 | Jul 14 06:43:28 PM PDT 24 | Jul 14 06:45:09 PM PDT 24 | 13418660000 ps | ||
| T27 | /workspace/coverage/default/10.prim_present_test.2735341734 | Jul 14 06:43:16 PM PDT 24 | Jul 14 06:44:40 PM PDT 24 | 13177480000 ps | ||
| T28 | /workspace/coverage/default/26.prim_present_test.1666779229 | Jul 14 06:43:25 PM PDT 24 | Jul 14 06:44:05 PM PDT 24 | 6089020000 ps | ||
| T29 | /workspace/coverage/default/44.prim_present_test.499023822 | Jul 14 06:43:27 PM PDT 24 | Jul 14 06:43:52 PM PDT 24 | 3629480000 ps | ||
| T30 | /workspace/coverage/default/36.prim_present_test.3135877468 | Jul 14 06:43:23 PM PDT 24 | Jul 14 06:44:32 PM PDT 24 | 9417800000 ps | ||
| T31 | /workspace/coverage/default/15.prim_present_test.3750037908 | Jul 14 06:43:15 PM PDT 24 | Jul 14 06:44:07 PM PDT 24 | 7353820000 ps | ||
| T32 | /workspace/coverage/default/2.prim_present_test.4214606231 | Jul 14 06:43:19 PM PDT 24 | Jul 14 06:43:57 PM PDT 24 | 5336340000 ps | ||
| T33 | /workspace/coverage/default/20.prim_present_test.3876021795 | Jul 14 06:43:23 PM PDT 24 | Jul 14 06:43:58 PM PDT 24 | 4303420000 ps | ||
| T34 | /workspace/coverage/default/35.prim_present_test.398690866 | Jul 14 06:43:23 PM PDT 24 | Jul 14 06:45:18 PM PDT 24 | 15403280000 ps | ||
| T35 | /workspace/coverage/default/9.prim_present_test.381053522 | Jul 14 06:43:18 PM PDT 24 | Jul 14 06:43:59 PM PDT 24 | 5628980000 ps | ||
| T36 | /workspace/coverage/default/3.prim_present_test.972741175 | Jul 14 06:43:16 PM PDT 24 | Jul 14 06:44:52 PM PDT 24 | 13228320000 ps | ||
| T37 | /workspace/coverage/default/33.prim_present_test.2268437879 | Jul 14 06:43:22 PM PDT 24 | Jul 14 06:44:33 PM PDT 24 | 11160620000 ps | ||
| T38 | /workspace/coverage/default/8.prim_present_test.910630336 | Jul 14 06:43:17 PM PDT 24 | Jul 14 06:44:22 PM PDT 24 | 8653960000 ps | ||
| T39 | /workspace/coverage/default/1.prim_present_test.4262598263 | Jul 14 06:43:17 PM PDT 24 | Jul 14 06:44:04 PM PDT 24 | 6407700000 ps | ||
| T40 | /workspace/coverage/default/24.prim_present_test.680961369 | Jul 14 06:43:25 PM PDT 24 | Jul 14 06:44:11 PM PDT 24 | 6026400000 ps | ||
| T41 | /workspace/coverage/default/32.prim_present_test.405968842 | Jul 14 06:43:24 PM PDT 24 | Jul 14 06:44:38 PM PDT 24 | 11772560000 ps | ||
| T42 | /workspace/coverage/default/16.prim_present_test.1562580665 | Jul 14 06:43:18 PM PDT 24 | Jul 14 06:44:34 PM PDT 24 | 10622460000 ps | ||
| T43 | /workspace/coverage/default/28.prim_present_test.1682522103 | Jul 14 06:43:21 PM PDT 24 | Jul 14 06:44:41 PM PDT 24 | 12478740000 ps | ||
| T44 | /workspace/coverage/default/43.prim_present_test.946753949 | Jul 14 06:43:25 PM PDT 24 | Jul 14 06:44:34 PM PDT 24 | 9574040000 ps | ||
| T45 | /workspace/coverage/default/40.prim_present_test.3070187347 | Jul 14 06:43:25 PM PDT 24 | Jul 14 06:43:50 PM PDT 24 | 3690240000 ps | ||
| T46 | /workspace/coverage/default/39.prim_present_test.1446221084 | Jul 14 06:43:27 PM PDT 24 | Jul 14 06:44:05 PM PDT 24 | 4734940000 ps | ||
| T47 | /workspace/coverage/default/5.prim_present_test.703658203 | Jul 14 06:43:16 PM PDT 24 | Jul 14 06:44:43 PM PDT 24 | 13325040000 ps | ||
| T48 | /workspace/coverage/default/38.prim_present_test.1192349103 | Jul 14 06:43:26 PM PDT 24 | Jul 14 06:44:34 PM PDT 24 | 8332180000 ps | ||
| T49 | /workspace/coverage/default/46.prim_present_test.1933516216 | Jul 14 06:43:24 PM PDT 24 | Jul 14 06:44:30 PM PDT 24 | 7843620000 ps | ||
| T50 | /workspace/coverage/default/12.prim_present_test.2555130178 | Jul 14 06:43:17 PM PDT 24 | Jul 14 06:44:00 PM PDT 24 | 6026400000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.1006008213 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8299940000 ps |
| CPU time | 32.14 seconds |
| Started | Jul 14 06:43:22 PM PDT 24 |
| Finished | Jul 14 06:44:27 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-cc18f510-61f2-4828-b6a2-3f646bd22cce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006008213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1006008213 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4262598263 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6407700000 ps |
| CPU time | 23.8 seconds |
| Started | Jul 14 06:43:17 PM PDT 24 |
| Finished | Jul 14 06:44:04 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-49072eda-984e-43a6-996a-d954a7679d4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262598263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4262598263 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2735341734 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13177480000 ps |
| CPU time | 43.74 seconds |
| Started | Jul 14 06:43:16 PM PDT 24 |
| Finished | Jul 14 06:44:40 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-eb4795f7-2c33-4d30-8931-2de2662d317b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735341734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2735341734 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1338666329 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5650680000 ps |
| CPU time | 21.04 seconds |
| Started | Jul 14 06:43:18 PM PDT 24 |
| Finished | Jul 14 06:44:00 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-71502c43-280c-4048-a10e-15ede5f49b70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338666329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1338666329 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2555130178 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6026400000 ps |
| CPU time | 21.33 seconds |
| Started | Jul 14 06:43:17 PM PDT 24 |
| Finished | Jul 14 06:44:00 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-515f2fcc-7e2b-4410-a59e-fa74b93d0ad8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555130178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2555130178 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.491007741 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11794260000 ps |
| CPU time | 38.81 seconds |
| Started | Jul 14 06:43:15 PM PDT 24 |
| Finished | Jul 14 06:44:29 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-9afb6798-94c4-4853-85af-af29f5bd5ca6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491007741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.491007741 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3567003417 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8909400000 ps |
| CPU time | 32.44 seconds |
| Started | Jul 14 06:43:16 PM PDT 24 |
| Finished | Jul 14 06:44:20 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-38f9e5f3-218d-48bd-a1e2-7b31d8ad01bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567003417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3567003417 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3750037908 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7353820000 ps |
| CPU time | 26.57 seconds |
| Started | Jul 14 06:43:15 PM PDT 24 |
| Finished | Jul 14 06:44:07 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-dab650cf-2e61-41d9-a622-eea8b9f276fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750037908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3750037908 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1562580665 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10622460000 ps |
| CPU time | 39.21 seconds |
| Started | Jul 14 06:43:18 PM PDT 24 |
| Finished | Jul 14 06:44:34 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-bbd532cf-8407-4c38-9dc7-41e95cdf6bc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562580665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1562580665 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2334293808 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5030680000 ps |
| CPU time | 18.78 seconds |
| Started | Jul 14 06:43:19 PM PDT 24 |
| Finished | Jul 14 06:43:56 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-118136c7-1f1c-49ef-8bbd-783a01fcba6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334293808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2334293808 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2674661899 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3538340000 ps |
| CPU time | 14.32 seconds |
| Started | Jul 14 06:43:23 PM PDT 24 |
| Finished | Jul 14 06:43:53 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-e0c6c8fa-de44-40e5-b075-f936c920c5a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674661899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2674661899 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.68248700 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9056960000 ps |
| CPU time | 32.74 seconds |
| Started | Jul 14 06:43:17 PM PDT 24 |
| Finished | Jul 14 06:44:21 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-11e28da8-af13-4fb1-963f-5e43afe44f3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68248700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.68248700 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4214606231 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5336340000 ps |
| CPU time | 19.57 seconds |
| Started | Jul 14 06:43:19 PM PDT 24 |
| Finished | Jul 14 06:43:57 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-cdf9e22b-9dad-48a0-841e-0606476976d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214606231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4214606231 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3876021795 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4303420000 ps |
| CPU time | 17.04 seconds |
| Started | Jul 14 06:43:23 PM PDT 24 |
| Finished | Jul 14 06:43:58 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-07021124-9888-47c8-92b1-42fe0a508946 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876021795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3876021795 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1834645883 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14574340000 ps |
| CPU time | 55.32 seconds |
| Started | Jul 14 06:43:23 PM PDT 24 |
| Finished | Jul 14 06:45:12 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-952316f5-c3c3-4f04-b23f-bd6ae1858935 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834645883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1834645883 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3750200765 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11748380000 ps |
| CPU time | 39.86 seconds |
| Started | Jul 14 06:43:19 PM PDT 24 |
| Finished | Jul 14 06:44:35 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-136352f8-c3c3-489c-a6a0-fd0ec403f338 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750200765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3750200765 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2440990685 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11002520000 ps |
| CPU time | 37.57 seconds |
| Started | Jul 14 06:43:15 PM PDT 24 |
| Finished | Jul 14 06:44:28 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-e69acb47-dfa4-4f20-a3da-2d6df3e7e051 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440990685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2440990685 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.680961369 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6026400000 ps |
| CPU time | 23.58 seconds |
| Started | Jul 14 06:43:25 PM PDT 24 |
| Finished | Jul 14 06:44:11 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-42142287-1294-4af1-94d8-e04b511e8b16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680961369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.680961369 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.244557370 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4016360000 ps |
| CPU time | 15.54 seconds |
| Started | Jul 14 06:43:22 PM PDT 24 |
| Finished | Jul 14 06:43:53 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-6b0ebe8e-16b6-44fb-a0aa-f49f47cd4bd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244557370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.244557370 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1666779229 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6089020000 ps |
| CPU time | 21.13 seconds |
| Started | Jul 14 06:43:25 PM PDT 24 |
| Finished | Jul 14 06:44:05 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-a2cefe82-d779-4b14-9550-c14c86ec7731 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666779229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1666779229 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1319677289 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5057340000 ps |
| CPU time | 18.92 seconds |
| Started | Jul 14 06:43:25 PM PDT 24 |
| Finished | Jul 14 06:44:01 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-6914c186-e8f0-42ed-ba33-e97b85165844 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319677289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1319677289 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1682522103 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12478740000 ps |
| CPU time | 42.02 seconds |
| Started | Jul 14 06:43:21 PM PDT 24 |
| Finished | Jul 14 06:44:41 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c48c5ede-4006-41aa-ba4a-aec2ce6f5401 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682522103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1682522103 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1528428774 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8329700000 ps |
| CPU time | 29.43 seconds |
| Started | Jul 14 06:43:25 PM PDT 24 |
| Finished | Jul 14 06:44:21 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-841d805e-cf96-4104-aed5-9a1f18e0ae68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528428774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1528428774 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.972741175 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13228320000 ps |
| CPU time | 49.4 seconds |
| Started | Jul 14 06:43:16 PM PDT 24 |
| Finished | Jul 14 06:44:52 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-f9dddd92-b7dc-4ab3-91e7-5af24c0ae7b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=972741175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.972741175 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2765553148 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12334900000 ps |
| CPU time | 44.74 seconds |
| Started | Jul 14 06:43:27 PM PDT 24 |
| Finished | Jul 14 06:44:51 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-8314b768-b630-4724-9c22-be1c0b54f8c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765553148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2765553148 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.88400248 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10838840000 ps |
| CPU time | 43.91 seconds |
| Started | Jul 14 06:43:23 PM PDT 24 |
| Finished | Jul 14 06:44:50 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-2de78c2d-c632-4cb1-a2b3-a67b2dda6cf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88400248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.88400248 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.405968842 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11772560000 ps |
| CPU time | 38.51 seconds |
| Started | Jul 14 06:43:24 PM PDT 24 |
| Finished | Jul 14 06:44:38 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-597d652d-da70-445c-a9aa-a22985ee4dbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405968842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.405968842 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2268437879 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11160620000 ps |
| CPU time | 37.18 seconds |
| Started | Jul 14 06:43:22 PM PDT 24 |
| Finished | Jul 14 06:44:33 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-bf4064c6-f937-4e56-af3f-5e36cee5f3e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268437879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2268437879 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.777764771 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6276880000 ps |
| CPU time | 23.72 seconds |
| Started | Jul 14 06:43:25 PM PDT 24 |
| Finished | Jul 14 06:44:11 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-c1cf071b-1123-431f-ac11-0e02b352fc89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777764771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.777764771 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.398690866 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 15403280000 ps |
| CPU time | 59.86 seconds |
| Started | Jul 14 06:43:23 PM PDT 24 |
| Finished | Jul 14 06:45:18 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-5c2c268c-e091-4fb3-8157-07883f5d9fb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398690866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.398690866 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3135877468 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9417800000 ps |
| CPU time | 35.46 seconds |
| Started | Jul 14 06:43:23 PM PDT 24 |
| Finished | Jul 14 06:44:32 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-c0185bce-58d6-48b4-81aa-bd64ccfc1858 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135877468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3135877468 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3220992531 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6909900000 ps |
| CPU time | 25.62 seconds |
| Started | Jul 14 06:43:23 PM PDT 24 |
| Finished | Jul 14 06:44:12 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-9f4274bf-4b92-4538-9cad-60760565b771 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220992531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3220992531 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1192349103 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8332180000 ps |
| CPU time | 34.42 seconds |
| Started | Jul 14 06:43:26 PM PDT 24 |
| Finished | Jul 14 06:44:34 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-cf093786-a30e-42e6-9ca7-ca0e2a00bc96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192349103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1192349103 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1446221084 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4734940000 ps |
| CPU time | 18.67 seconds |
| Started | Jul 14 06:43:27 PM PDT 24 |
| Finished | Jul 14 06:44:05 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-48216b94-cc01-4ad8-973a-5ed41f371608 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1446221084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1446221084 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2825652918 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13483140000 ps |
| CPU time | 47.26 seconds |
| Started | Jul 14 06:43:18 PM PDT 24 |
| Finished | Jul 14 06:44:49 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-e1ce8848-2bc1-43e1-acb2-81c1b8dde728 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825652918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2825652918 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3070187347 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3690240000 ps |
| CPU time | 12.84 seconds |
| Started | Jul 14 06:43:25 PM PDT 24 |
| Finished | Jul 14 06:43:50 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-b7a709d7-15aa-4e90-9ad5-56df5398202b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070187347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3070187347 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2732364877 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13418660000 ps |
| CPU time | 51.3 seconds |
| Started | Jul 14 06:43:28 PM PDT 24 |
| Finished | Jul 14 06:45:09 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-26c945a4-2038-4247-b61f-625504ccae8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732364877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2732364877 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2800865589 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8942260000 ps |
| CPU time | 29.62 seconds |
| Started | Jul 14 06:43:27 PM PDT 24 |
| Finished | Jul 14 06:44:22 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-93327fd9-381e-487a-b465-929fb07a60e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800865589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2800865589 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.946753949 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 9574040000 ps |
| CPU time | 36.07 seconds |
| Started | Jul 14 06:43:25 PM PDT 24 |
| Finished | Jul 14 06:44:34 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-140c9b27-8222-45e2-9379-1cc5623555e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946753949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.946753949 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.499023822 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3629480000 ps |
| CPU time | 13.35 seconds |
| Started | Jul 14 06:43:27 PM PDT 24 |
| Finished | Jul 14 06:43:52 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-fe87b64e-c355-4995-ac13-dcda30818135 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499023822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.499023822 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1922104311 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8726500000 ps |
| CPU time | 28 seconds |
| Started | Jul 14 06:43:22 PM PDT 24 |
| Finished | Jul 14 06:44:15 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-0f718c10-ea52-475d-a459-749e6370628a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922104311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1922104311 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1933516216 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7843620000 ps |
| CPU time | 33.25 seconds |
| Started | Jul 14 06:43:24 PM PDT 24 |
| Finished | Jul 14 06:44:30 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-6cfba208-8e4e-4f05-aa99-db6175637e4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933516216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1933516216 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3656990924 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12752160000 ps |
| CPU time | 43.52 seconds |
| Started | Jul 14 06:43:24 PM PDT 24 |
| Finished | Jul 14 06:44:47 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-3a5374ef-9c42-4d53-9a28-5ce952377083 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656990924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3656990924 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.58779626 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3228340000 ps |
| CPU time | 12.26 seconds |
| Started | Jul 14 06:43:25 PM PDT 24 |
| Finished | Jul 14 06:43:49 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-0f8dece1-9a30-4ed6-9f54-eaf42f3c0575 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58779626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.58779626 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3196394361 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15449780000 ps |
| CPU time | 58.98 seconds |
| Started | Jul 14 06:43:24 PM PDT 24 |
| Finished | Jul 14 06:45:20 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-050dcb73-8601-4a77-9e75-9b287d0e62ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196394361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3196394361 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.703658203 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13325040000 ps |
| CPU time | 45.03 seconds |
| Started | Jul 14 06:43:16 PM PDT 24 |
| Finished | Jul 14 06:44:43 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-289efa24-9c4f-4891-9df6-6cf6925c0751 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703658203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.703658203 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.666878346 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8992480000 ps |
| CPU time | 37.55 seconds |
| Started | Jul 14 06:43:19 PM PDT 24 |
| Finished | Jul 14 06:44:34 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-612ecfe8-a8e9-4e58-adfa-cbdac6ec43a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666878346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.666878346 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.959453340 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11659100000 ps |
| CPU time | 39.07 seconds |
| Started | Jul 14 06:43:18 PM PDT 24 |
| Finished | Jul 14 06:44:33 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-3a233918-6eb2-4c15-8725-845838655114 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959453340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.959453340 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.910630336 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8653960000 ps |
| CPU time | 33.34 seconds |
| Started | Jul 14 06:43:17 PM PDT 24 |
| Finished | Jul 14 06:44:22 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-82b41698-193b-4d4f-8076-37ba05970ade |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910630336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.910630336 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.381053522 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5628980000 ps |
| CPU time | 20.77 seconds |
| Started | Jul 14 06:43:18 PM PDT 24 |
| Finished | Jul 14 06:43:59 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-104bc8a3-77dd-4222-9d5f-69dc97771422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381053522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.381053522 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |