| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.438430826 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.801095856 |
| /workspace/coverage/default/10.prim_present_test.2439446761 |
| /workspace/coverage/default/11.prim_present_test.3429831962 |
| /workspace/coverage/default/12.prim_present_test.983523626 |
| /workspace/coverage/default/13.prim_present_test.146643786 |
| /workspace/coverage/default/14.prim_present_test.134635249 |
| /workspace/coverage/default/15.prim_present_test.3995926194 |
| /workspace/coverage/default/16.prim_present_test.3277472160 |
| /workspace/coverage/default/17.prim_present_test.3680442577 |
| /workspace/coverage/default/18.prim_present_test.223963533 |
| /workspace/coverage/default/19.prim_present_test.193013175 |
| /workspace/coverage/default/2.prim_present_test.3071005863 |
| /workspace/coverage/default/20.prim_present_test.3693754209 |
| /workspace/coverage/default/21.prim_present_test.2056361288 |
| /workspace/coverage/default/22.prim_present_test.2748155980 |
| /workspace/coverage/default/23.prim_present_test.3400297575 |
| /workspace/coverage/default/24.prim_present_test.36768897 |
| /workspace/coverage/default/25.prim_present_test.1423335647 |
| /workspace/coverage/default/26.prim_present_test.2264253685 |
| /workspace/coverage/default/27.prim_present_test.1002914573 |
| /workspace/coverage/default/28.prim_present_test.1604350024 |
| /workspace/coverage/default/29.prim_present_test.4124799018 |
| /workspace/coverage/default/3.prim_present_test.3075281864 |
| /workspace/coverage/default/30.prim_present_test.1004418714 |
| /workspace/coverage/default/31.prim_present_test.1277091589 |
| /workspace/coverage/default/32.prim_present_test.1304583872 |
| /workspace/coverage/default/33.prim_present_test.4256503002 |
| /workspace/coverage/default/34.prim_present_test.1027866848 |
| /workspace/coverage/default/35.prim_present_test.3705379309 |
| /workspace/coverage/default/36.prim_present_test.2473507807 |
| /workspace/coverage/default/37.prim_present_test.3679157281 |
| /workspace/coverage/default/38.prim_present_test.2334257572 |
| /workspace/coverage/default/39.prim_present_test.113400247 |
| /workspace/coverage/default/4.prim_present_test.3991263790 |
| /workspace/coverage/default/40.prim_present_test.909484759 |
| /workspace/coverage/default/41.prim_present_test.2585659928 |
| /workspace/coverage/default/42.prim_present_test.2713146134 |
| /workspace/coverage/default/43.prim_present_test.2284842196 |
| /workspace/coverage/default/44.prim_present_test.1687714327 |
| /workspace/coverage/default/45.prim_present_test.4294447620 |
| /workspace/coverage/default/46.prim_present_test.1728376290 |
| /workspace/coverage/default/47.prim_present_test.1039416619 |
| /workspace/coverage/default/48.prim_present_test.2434221102 |
| /workspace/coverage/default/49.prim_present_test.3446325249 |
| /workspace/coverage/default/5.prim_present_test.3271626798 |
| /workspace/coverage/default/6.prim_present_test.374388039 |
| /workspace/coverage/default/7.prim_present_test.3687751378 |
| /workspace/coverage/default/8.prim_present_test.3757746297 |
| /workspace/coverage/default/9.prim_present_test.339723947 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_present_test.438430826 | Jul 15 05:50:41 PM PDT 24 | Jul 15 05:51:44 PM PDT 24 | 10641680000 ps | ||
| T2 | /workspace/coverage/default/32.prim_present_test.1304583872 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:51:33 PM PDT 24 | 6161560000 ps | ||
| T3 | /workspace/coverage/default/16.prim_present_test.3277472160 | Jul 15 05:50:43 PM PDT 24 | Jul 15 05:52:34 PM PDT 24 | 15369800000 ps | ||
| T4 | /workspace/coverage/default/25.prim_present_test.1423335647 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:51:41 PM PDT 24 | 8430760000 ps | ||
| T5 | /workspace/coverage/default/21.prim_present_test.2056361288 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:52:09 PM PDT 24 | 13516000000 ps | ||
| T6 | /workspace/coverage/default/34.prim_present_test.1027866848 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:51:33 PM PDT 24 | 6289280000 ps | ||
| T7 | /workspace/coverage/default/6.prim_present_test.374388039 | Jul 15 05:50:39 PM PDT 24 | Jul 15 05:51:29 PM PDT 24 | 7056220000 ps | ||
| T8 | /workspace/coverage/default/9.prim_present_test.339723947 | Jul 15 05:50:42 PM PDT 24 | Jul 15 05:51:44 PM PDT 24 | 8089140000 ps | ||
| T9 | /workspace/coverage/default/41.prim_present_test.2585659928 | Jul 15 05:50:47 PM PDT 24 | Jul 15 05:52:37 PM PDT 24 | 13660460000 ps | ||
| T10 | /workspace/coverage/default/44.prim_present_test.1687714327 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:52:02 PM PDT 24 | 13400060000 ps | ||
| T11 | /workspace/coverage/default/3.prim_present_test.3075281864 | Jul 15 05:50:41 PM PDT 24 | Jul 15 05:51:45 PM PDT 24 | 7485260000 ps | ||
| T12 | /workspace/coverage/default/37.prim_present_test.3679157281 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:51:53 PM PDT 24 | 9768720000 ps | ||
| T13 | /workspace/coverage/default/26.prim_present_test.2264253685 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:51:14 PM PDT 24 | 4094480000 ps | ||
| T14 | /workspace/coverage/default/31.prim_present_test.1277091589 | Jul 15 05:50:50 PM PDT 24 | Jul 15 05:52:15 PM PDT 24 | 13618300000 ps | ||
| T15 | /workspace/coverage/default/36.prim_present_test.2473507807 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:52:00 PM PDT 24 | 9730280000 ps | ||
| T16 | /workspace/coverage/default/1.prim_present_test.801095856 | Jul 15 05:50:39 PM PDT 24 | Jul 15 05:51:38 PM PDT 24 | 9831960000 ps | ||
| T17 | /workspace/coverage/default/19.prim_present_test.193013175 | Jul 15 05:50:47 PM PDT 24 | Jul 15 05:52:02 PM PDT 24 | 12538260000 ps | ||
| T18 | /workspace/coverage/default/45.prim_present_test.4294447620 | Jul 15 05:50:51 PM PDT 24 | Jul 15 05:52:07 PM PDT 24 | 9028440000 ps | ||
| T19 | /workspace/coverage/default/24.prim_present_test.36768897 | Jul 15 05:50:49 PM PDT 24 | Jul 15 05:52:05 PM PDT 24 | 10275880000 ps | ||
| T20 | /workspace/coverage/default/7.prim_present_test.3687751378 | Jul 15 05:50:39 PM PDT 24 | Jul 15 05:51:18 PM PDT 24 | 5188160000 ps | ||
| T21 | /workspace/coverage/default/23.prim_present_test.3400297575 | Jul 15 05:50:47 PM PDT 24 | Jul 15 05:52:18 PM PDT 24 | 11214560000 ps | ||
| T22 | /workspace/coverage/default/8.prim_present_test.3757746297 | Jul 15 05:50:42 PM PDT 24 | Jul 15 05:51:39 PM PDT 24 | 7464800000 ps | ||
| T23 | /workspace/coverage/default/29.prim_present_test.4124799018 | Jul 15 05:50:50 PM PDT 24 | Jul 15 05:51:47 PM PDT 24 | 7826880000 ps | ||
| T24 | /workspace/coverage/default/4.prim_present_test.3991263790 | Jul 15 05:50:43 PM PDT 24 | Jul 15 05:51:42 PM PDT 24 | 8997440000 ps | ||
| T25 | /workspace/coverage/default/22.prim_present_test.2748155980 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:52:46 PM PDT 24 | 15403280000 ps | ||
| T26 | /workspace/coverage/default/20.prim_present_test.3693754209 | Jul 15 05:50:49 PM PDT 24 | Jul 15 05:52:19 PM PDT 24 | 12582280000 ps | ||
| T27 | /workspace/coverage/default/39.prim_present_test.113400247 | Jul 15 05:50:49 PM PDT 24 | Jul 15 05:52:15 PM PDT 24 | 12192920000 ps | ||
| T28 | /workspace/coverage/default/28.prim_present_test.1604350024 | Jul 15 05:50:47 PM PDT 24 | Jul 15 05:52:15 PM PDT 24 | 11696300000 ps | ||
| T29 | /workspace/coverage/default/14.prim_present_test.134635249 | Jul 15 05:50:42 PM PDT 24 | Jul 15 05:51:38 PM PDT 24 | 7340180000 ps | ||
| T30 | /workspace/coverage/default/40.prim_present_test.909484759 | Jul 15 05:50:52 PM PDT 24 | Jul 15 05:51:39 PM PDT 24 | 6615400000 ps | ||
| T31 | /workspace/coverage/default/15.prim_present_test.3995926194 | Jul 15 05:50:39 PM PDT 24 | Jul 15 05:52:22 PM PDT 24 | 15432420000 ps | ||
| T32 | /workspace/coverage/default/2.prim_present_test.3071005863 | Jul 15 05:50:42 PM PDT 24 | Jul 15 05:51:25 PM PDT 24 | 5335720000 ps | ||
| T33 | /workspace/coverage/default/48.prim_present_test.2434221102 | Jul 15 05:50:47 PM PDT 24 | Jul 15 05:51:49 PM PDT 24 | 7183320000 ps | ||
| T34 | /workspace/coverage/default/12.prim_present_test.983523626 | Jul 15 05:50:40 PM PDT 24 | Jul 15 05:51:39 PM PDT 24 | 8175940000 ps | ||
| T35 | /workspace/coverage/default/38.prim_present_test.2334257572 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:52:25 PM PDT 24 | 13267380000 ps | ||
| T36 | /workspace/coverage/default/11.prim_present_test.3429831962 | Jul 15 05:50:39 PM PDT 24 | Jul 15 05:51:29 PM PDT 24 | 6763580000 ps | ||
| T37 | /workspace/coverage/default/35.prim_present_test.3705379309 | Jul 15 05:50:49 PM PDT 24 | Jul 15 05:51:40 PM PDT 24 | 5906740000 ps | ||
| T38 | /workspace/coverage/default/30.prim_present_test.1004418714 | Jul 15 05:50:45 PM PDT 24 | Jul 15 05:51:30 PM PDT 24 | 5640760000 ps | ||
| T39 | /workspace/coverage/default/43.prim_present_test.2284842196 | Jul 15 05:50:52 PM PDT 24 | Jul 15 05:52:00 PM PDT 24 | 9552340000 ps | ||
| T40 | /workspace/coverage/default/33.prim_present_test.4256503002 | Jul 15 05:50:47 PM PDT 24 | Jul 15 05:51:27 PM PDT 24 | 5748020000 ps | ||
| T41 | /workspace/coverage/default/10.prim_present_test.2439446761 | Jul 15 05:50:43 PM PDT 24 | Jul 15 05:52:09 PM PDT 24 | 11414820000 ps | ||
| T42 | /workspace/coverage/default/46.prim_present_test.1728376290 | Jul 15 05:50:47 PM PDT 24 | Jul 15 05:52:21 PM PDT 24 | 12693880000 ps | ||
| T43 | /workspace/coverage/default/17.prim_present_test.3680442577 | Jul 15 05:50:42 PM PDT 24 | Jul 15 05:52:25 PM PDT 24 | 13544520000 ps | ||
| T44 | /workspace/coverage/default/27.prim_present_test.1002914573 | Jul 15 05:50:52 PM PDT 24 | Jul 15 05:52:31 PM PDT 24 | 14539000000 ps | ||
| T45 | /workspace/coverage/default/5.prim_present_test.3271626798 | Jul 15 05:50:42 PM PDT 24 | Jul 15 05:51:25 PM PDT 24 | 5592400000 ps | ||
| T46 | /workspace/coverage/default/42.prim_present_test.2713146134 | Jul 15 05:50:50 PM PDT 24 | Jul 15 05:51:55 PM PDT 24 | 10050200000 ps | ||
| T47 | /workspace/coverage/default/13.prim_present_test.146643786 | Jul 15 05:50:40 PM PDT 24 | Jul 15 05:51:32 PM PDT 24 | 8365040000 ps | ||
| T48 | /workspace/coverage/default/49.prim_present_test.3446325249 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:52:29 PM PDT 24 | 15176980000 ps | ||
| T49 | /workspace/coverage/default/18.prim_present_test.223963533 | Jul 15 05:50:51 PM PDT 24 | Jul 15 05:51:20 PM PDT 24 | 4615900000 ps | ||
| T50 | /workspace/coverage/default/47.prim_present_test.1039416619 | Jul 15 05:50:48 PM PDT 24 | Jul 15 05:52:19 PM PDT 24 | 11895320000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.438430826 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10641680000 ps |
| CPU time | 33.75 seconds |
| Started | Jul 15 05:50:41 PM PDT 24 |
| Finished | Jul 15 05:51:44 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-185dacd1-b91d-4ab0-b5fd-24f811ec0954 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438430826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.438430826 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.801095856 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9831960000 ps |
| CPU time | 31.53 seconds |
| Started | Jul 15 05:50:39 PM PDT 24 |
| Finished | Jul 15 05:51:38 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-a8d9cdb7-1ed0-4bb5-a226-a407933ab790 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801095856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.801095856 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2439446761 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11414820000 ps |
| CPU time | 43.65 seconds |
| Started | Jul 15 05:50:43 PM PDT 24 |
| Finished | Jul 15 05:52:09 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-56f7e583-6d42-46b8-bdd3-e3efafd3f198 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439446761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2439446761 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3429831962 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6763580000 ps |
| CPU time | 25.68 seconds |
| Started | Jul 15 05:50:39 PM PDT 24 |
| Finished | Jul 15 05:51:29 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-4fdbbb05-2d79-488d-a28c-a88d5c1e319b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429831962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3429831962 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.983523626 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8175940000 ps |
| CPU time | 30.6 seconds |
| Started | Jul 15 05:50:40 PM PDT 24 |
| Finished | Jul 15 05:51:39 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-2545c4bd-0d60-47df-86ca-177ed291753d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983523626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.983523626 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.146643786 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8365040000 ps |
| CPU time | 27.64 seconds |
| Started | Jul 15 05:50:40 PM PDT 24 |
| Finished | Jul 15 05:51:32 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-a85863bd-8433-44c9-811e-2134821b3a7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146643786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.146643786 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.134635249 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7340180000 ps |
| CPU time | 29.19 seconds |
| Started | Jul 15 05:50:42 PM PDT 24 |
| Finished | Jul 15 05:51:38 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-c2efb100-9181-4834-9d37-7574ab6cfac0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=134635249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.134635249 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3995926194 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15432420000 ps |
| CPU time | 54.52 seconds |
| Started | Jul 15 05:50:39 PM PDT 24 |
| Finished | Jul 15 05:52:22 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-8b7420fc-4942-45d4-92db-9bd673c94159 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995926194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3995926194 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3277472160 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 15369800000 ps |
| CPU time | 57 seconds |
| Started | Jul 15 05:50:43 PM PDT 24 |
| Finished | Jul 15 05:52:34 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-6c0bca1f-0b27-4132-aace-c1b51726eec1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277472160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3277472160 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3680442577 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13544520000 ps |
| CPU time | 52.6 seconds |
| Started | Jul 15 05:50:42 PM PDT 24 |
| Finished | Jul 15 05:52:25 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-5fc21010-041e-4c28-bfed-5bf157f57dc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680442577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3680442577 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.223963533 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4615900000 ps |
| CPU time | 14.76 seconds |
| Started | Jul 15 05:50:51 PM PDT 24 |
| Finished | Jul 15 05:51:20 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-5423124f-2e9e-49de-9eb6-c9300ddcd0a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223963533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.223963533 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.193013175 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12538260000 ps |
| CPU time | 39.91 seconds |
| Started | Jul 15 05:50:47 PM PDT 24 |
| Finished | Jul 15 05:52:02 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-d29ddd83-036e-4e5f-88c8-d9904e3957e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193013175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.193013175 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3071005863 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5335720000 ps |
| CPU time | 20.86 seconds |
| Started | Jul 15 05:50:42 PM PDT 24 |
| Finished | Jul 15 05:51:25 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-e8c381b2-609f-4cee-9836-a539d9fe22c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071005863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3071005863 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3693754209 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12582280000 ps |
| CPU time | 46.89 seconds |
| Started | Jul 15 05:50:49 PM PDT 24 |
| Finished | Jul 15 05:52:19 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-8cf7df48-c6ac-4dbd-8669-c23c8317ddfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693754209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3693754209 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2056361288 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13516000000 ps |
| CPU time | 43.62 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:52:09 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-6f50c692-e525-48bf-b116-0c6c3a79b3fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056361288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2056361288 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2748155980 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 15403280000 ps |
| CPU time | 60.03 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:52:46 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-59c31cb2-5a97-47da-bfa9-83ea87c4607c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748155980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2748155980 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3400297575 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11214560000 ps |
| CPU time | 45.63 seconds |
| Started | Jul 15 05:50:47 PM PDT 24 |
| Finished | Jul 15 05:52:18 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-32974c62-6671-4403-93af-fbd474138631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400297575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3400297575 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.36768897 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10275880000 ps |
| CPU time | 39.46 seconds |
| Started | Jul 15 05:50:49 PM PDT 24 |
| Finished | Jul 15 05:52:05 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-5742a886-6c98-4e7f-8167-c2ef33d6e1b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36768897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.36768897 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1423335647 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8430760000 ps |
| CPU time | 28.47 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:51:41 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-ffe82848-8408-4354-afeb-1721f83cbdec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423335647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1423335647 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2264253685 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4094480000 ps |
| CPU time | 13.85 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:51:14 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-7e508580-318b-47bc-a749-a085bc6a9a0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264253685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2264253685 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1002914573 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14539000000 ps |
| CPU time | 51.81 seconds |
| Started | Jul 15 05:50:52 PM PDT 24 |
| Finished | Jul 15 05:52:31 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-a33c0cfc-1be9-4e26-b5d5-6ff9e02d17ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002914573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1002914573 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1604350024 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11696300000 ps |
| CPU time | 45.28 seconds |
| Started | Jul 15 05:50:47 PM PDT 24 |
| Finished | Jul 15 05:52:15 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-e5ee6472-c9f6-4f4e-9d92-b203ce344c65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604350024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1604350024 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4124799018 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7826880000 ps |
| CPU time | 29.94 seconds |
| Started | Jul 15 05:50:50 PM PDT 24 |
| Finished | Jul 15 05:51:47 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-a8db952d-04ee-4258-abe5-1b65c5567d36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4124799018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4124799018 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3075281864 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7485260000 ps |
| CPU time | 32.99 seconds |
| Started | Jul 15 05:50:41 PM PDT 24 |
| Finished | Jul 15 05:51:45 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-def2d7aa-3b52-44aa-8994-40bef932c951 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3075281864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3075281864 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1004418714 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5640760000 ps |
| CPU time | 22.35 seconds |
| Started | Jul 15 05:50:45 PM PDT 24 |
| Finished | Jul 15 05:51:30 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-23526c9c-a6ea-4a10-8fb2-a2015751097e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004418714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1004418714 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1277091589 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13618300000 ps |
| CPU time | 45.02 seconds |
| Started | Jul 15 05:50:50 PM PDT 24 |
| Finished | Jul 15 05:52:15 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-f6a82222-1a29-4e81-9a23-740d4e15878f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277091589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1277091589 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1304583872 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6161560000 ps |
| CPU time | 23.24 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:51:33 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-2ce0075f-1d21-4f91-baaf-cfac1d5e2e0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304583872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1304583872 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.4256503002 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5748020000 ps |
| CPU time | 20.94 seconds |
| Started | Jul 15 05:50:47 PM PDT 24 |
| Finished | Jul 15 05:51:27 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-79813e96-2b0a-49f9-8b71-0698fbcba3fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4256503002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.4256503002 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1027866848 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6289280000 ps |
| CPU time | 23.25 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:51:33 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-60638a33-5825-4375-9211-8a150e866a9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027866848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1027866848 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3705379309 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5906740000 ps |
| CPU time | 24.95 seconds |
| Started | Jul 15 05:50:49 PM PDT 24 |
| Finished | Jul 15 05:51:40 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-4f976cfc-e846-4197-92c5-5ec9b3124ba2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705379309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3705379309 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2473507807 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9730280000 ps |
| CPU time | 38.14 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:52:00 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-c365db21-f26e-4e08-a263-d0ce5e789696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473507807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2473507807 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3679157281 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9768720000 ps |
| CPU time | 33.94 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:51:53 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-aac127c9-7c08-4e5a-a14b-a0eb97f0608e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679157281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3679157281 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2334257572 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13267380000 ps |
| CPU time | 50.59 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:52:25 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-8c06be07-0644-4821-89ae-255f8e1f8d62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334257572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2334257572 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.113400247 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12192920000 ps |
| CPU time | 45.09 seconds |
| Started | Jul 15 05:50:49 PM PDT 24 |
| Finished | Jul 15 05:52:15 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-bf5ee97a-a7ca-4f61-9839-7b8311bc29f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113400247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.113400247 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3991263790 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8997440000 ps |
| CPU time | 31.18 seconds |
| Started | Jul 15 05:50:43 PM PDT 24 |
| Finished | Jul 15 05:51:42 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-9a7f6c57-0f69-4a57-a3f8-8d378f4438ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3991263790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3991263790 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.909484759 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6615400000 ps |
| CPU time | 24.75 seconds |
| Started | Jul 15 05:50:52 PM PDT 24 |
| Finished | Jul 15 05:51:39 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-b0269a6e-4de6-47d0-9178-8fd901464d30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909484759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.909484759 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2585659928 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13660460000 ps |
| CPU time | 55.25 seconds |
| Started | Jul 15 05:50:47 PM PDT 24 |
| Finished | Jul 15 05:52:37 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-a95c4baf-bc9b-4c0b-91e2-7f8e39431123 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585659928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2585659928 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2713146134 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10050200000 ps |
| CPU time | 34.31 seconds |
| Started | Jul 15 05:50:50 PM PDT 24 |
| Finished | Jul 15 05:51:55 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-21d65879-3378-4252-9662-44a56c98a55f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713146134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2713146134 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2284842196 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9552340000 ps |
| CPU time | 35.58 seconds |
| Started | Jul 15 05:50:52 PM PDT 24 |
| Finished | Jul 15 05:52:00 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-bcc3cf4a-49e5-4189-a501-94f0d25a75de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2284842196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2284842196 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1687714327 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13400060000 ps |
| CPU time | 38.66 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:52:02 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-4ad58163-5a1a-4ab5-93c0-5ca939b5c8a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1687714327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1687714327 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4294447620 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9028440000 ps |
| CPU time | 39.59 seconds |
| Started | Jul 15 05:50:51 PM PDT 24 |
| Finished | Jul 15 05:52:07 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-a07d0342-f43d-4c09-a3fb-1e906ec242ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294447620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4294447620 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1728376290 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12693880000 ps |
| CPU time | 48.22 seconds |
| Started | Jul 15 05:50:47 PM PDT 24 |
| Finished | Jul 15 05:52:21 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-7b416822-c274-47a8-8576-ee8c8f8b3028 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728376290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1728376290 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1039416619 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11895320000 ps |
| CPU time | 47.56 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:52:19 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-86b5eca8-bade-4c4b-bab3-8858098fedc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039416619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1039416619 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2434221102 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7183320000 ps |
| CPU time | 30.65 seconds |
| Started | Jul 15 05:50:47 PM PDT 24 |
| Finished | Jul 15 05:51:49 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-2d272736-2c7e-4dfa-86d3-e3fb328913d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2434221102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2434221102 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3446325249 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 15176980000 ps |
| CPU time | 53.39 seconds |
| Started | Jul 15 05:50:48 PM PDT 24 |
| Finished | Jul 15 05:52:29 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-a28ad3f3-cc2d-447c-9451-e17414aaf49f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446325249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3446325249 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3271626798 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5592400000 ps |
| CPU time | 22.21 seconds |
| Started | Jul 15 05:50:42 PM PDT 24 |
| Finished | Jul 15 05:51:25 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-5f7b6e1c-164a-46a4-a539-e691def3dadd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271626798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3271626798 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.374388039 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7056220000 ps |
| CPU time | 26.76 seconds |
| Started | Jul 15 05:50:39 PM PDT 24 |
| Finished | Jul 15 05:51:29 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-0bff44d8-1f21-4d7f-bc94-23a01eba90e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=374388039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.374388039 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3687751378 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5188160000 ps |
| CPU time | 19.94 seconds |
| Started | Jul 15 05:50:39 PM PDT 24 |
| Finished | Jul 15 05:51:18 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-a921d363-5ecd-4ed5-a298-43d9aa90eb72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687751378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3687751378 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3757746297 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7464800000 ps |
| CPU time | 29.42 seconds |
| Started | Jul 15 05:50:42 PM PDT 24 |
| Finished | Jul 15 05:51:39 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-f625f1b8-7df3-4c85-a2ba-1d7221a9f6d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757746297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3757746297 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.339723947 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8089140000 ps |
| CPU time | 31.94 seconds |
| Started | Jul 15 05:50:42 PM PDT 24 |
| Finished | Jul 15 05:51:44 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-25b04d82-40eb-491c-ad7a-ca1c30cb341e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339723947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.339723947 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |