| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.1485463252 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2018327387 |
| /workspace/coverage/default/10.prim_present_test.4037425433 |
| /workspace/coverage/default/11.prim_present_test.1701161223 |
| /workspace/coverage/default/12.prim_present_test.1652232619 |
| /workspace/coverage/default/13.prim_present_test.1936259508 |
| /workspace/coverage/default/14.prim_present_test.366569132 |
| /workspace/coverage/default/15.prim_present_test.942964615 |
| /workspace/coverage/default/16.prim_present_test.3219710385 |
| /workspace/coverage/default/17.prim_present_test.1154066041 |
| /workspace/coverage/default/18.prim_present_test.1345697 |
| /workspace/coverage/default/19.prim_present_test.3127212312 |
| /workspace/coverage/default/2.prim_present_test.1175879543 |
| /workspace/coverage/default/20.prim_present_test.983460560 |
| /workspace/coverage/default/21.prim_present_test.3561431882 |
| /workspace/coverage/default/22.prim_present_test.2166224159 |
| /workspace/coverage/default/23.prim_present_test.1795253563 |
| /workspace/coverage/default/24.prim_present_test.1285824504 |
| /workspace/coverage/default/25.prim_present_test.979283941 |
| /workspace/coverage/default/26.prim_present_test.4016425501 |
| /workspace/coverage/default/27.prim_present_test.1237587149 |
| /workspace/coverage/default/28.prim_present_test.833520113 |
| /workspace/coverage/default/29.prim_present_test.1900279751 |
| /workspace/coverage/default/3.prim_present_test.1626026888 |
| /workspace/coverage/default/30.prim_present_test.4062967557 |
| /workspace/coverage/default/31.prim_present_test.1975634529 |
| /workspace/coverage/default/32.prim_present_test.2439421729 |
| /workspace/coverage/default/33.prim_present_test.1796500767 |
| /workspace/coverage/default/34.prim_present_test.1117725264 |
| /workspace/coverage/default/35.prim_present_test.2426876452 |
| /workspace/coverage/default/36.prim_present_test.519834372 |
| /workspace/coverage/default/37.prim_present_test.2776704860 |
| /workspace/coverage/default/38.prim_present_test.3180125642 |
| /workspace/coverage/default/39.prim_present_test.3445289431 |
| /workspace/coverage/default/4.prim_present_test.669743298 |
| /workspace/coverage/default/40.prim_present_test.189224243 |
| /workspace/coverage/default/41.prim_present_test.3404801809 |
| /workspace/coverage/default/42.prim_present_test.542670934 |
| /workspace/coverage/default/43.prim_present_test.2091881399 |
| /workspace/coverage/default/44.prim_present_test.3498365476 |
| /workspace/coverage/default/45.prim_present_test.934504761 |
| /workspace/coverage/default/46.prim_present_test.2083358920 |
| /workspace/coverage/default/47.prim_present_test.2588242762 |
| /workspace/coverage/default/48.prim_present_test.1475363347 |
| /workspace/coverage/default/49.prim_present_test.607037810 |
| /workspace/coverage/default/5.prim_present_test.3685002403 |
| /workspace/coverage/default/6.prim_present_test.425142051 |
| /workspace/coverage/default/7.prim_present_test.1604717 |
| /workspace/coverage/default/8.prim_present_test.1874076052 |
| /workspace/coverage/default/9.prim_present_test.2768008306 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/39.prim_present_test.3445289431 | Jul 16 06:36:16 PM PDT 24 | Jul 16 06:38:04 PM PDT 24 | 12773860000 ps | ||
| T2 | /workspace/coverage/default/18.prim_present_test.1345697 | Jul 16 06:36:16 PM PDT 24 | Jul 16 06:38:02 PM PDT 24 | 15339420000 ps | ||
| T3 | /workspace/coverage/default/28.prim_present_test.833520113 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:37:03 PM PDT 24 | 6157220000 ps | ||
| T4 | /workspace/coverage/default/43.prim_present_test.2091881399 | Jul 16 06:36:27 PM PDT 24 | Jul 16 06:38:17 PM PDT 24 | 15193720000 ps | ||
| T5 | /workspace/coverage/default/15.prim_present_test.942964615 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:38:06 PM PDT 24 | 15274940000 ps | ||
| T6 | /workspace/coverage/default/1.prim_present_test.1485463252 | Jul 16 06:36:01 PM PDT 24 | Jul 16 06:36:32 PM PDT 24 | 4878160000 ps | ||
| T7 | /workspace/coverage/default/8.prim_present_test.1874076052 | Jul 16 06:36:01 PM PDT 24 | Jul 16 06:37:29 PM PDT 24 | 13554440000 ps | ||
| T8 | /workspace/coverage/default/32.prim_present_test.2439421729 | Jul 16 06:36:16 PM PDT 24 | Jul 16 06:37:43 PM PDT 24 | 13429820000 ps | ||
| T9 | /workspace/coverage/default/21.prim_present_test.3561431882 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:37:33 PM PDT 24 | 11532620000 ps | ||
| T10 | /workspace/coverage/default/17.prim_present_test.1154066041 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:36:50 PM PDT 24 | 4469580000 ps | ||
| T11 | /workspace/coverage/default/27.prim_present_test.1237587149 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:37:38 PM PDT 24 | 13959920000 ps | ||
| T12 | /workspace/coverage/default/14.prim_present_test.366569132 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:37:16 PM PDT 24 | 9073700000 ps | ||
| T13 | /workspace/coverage/default/35.prim_present_test.2426876452 | Jul 16 06:36:13 PM PDT 24 | Jul 16 06:37:53 PM PDT 24 | 13556920000 ps | ||
| T14 | /workspace/coverage/default/22.prim_present_test.2166224159 | Jul 16 06:36:14 PM PDT 24 | Jul 16 06:37:09 PM PDT 24 | 7546640000 ps | ||
| T15 | /workspace/coverage/default/7.prim_present_test.1604717 | Jul 16 06:36:00 PM PDT 24 | Jul 16 06:37:08 PM PDT 24 | 9843120000 ps | ||
| T16 | /workspace/coverage/default/9.prim_present_test.2768008306 | Jul 16 06:36:01 PM PDT 24 | Jul 16 06:37:28 PM PDT 24 | 13028680000 ps | ||
| T17 | /workspace/coverage/default/36.prim_present_test.519834372 | Jul 16 06:36:21 PM PDT 24 | Jul 16 06:37:46 PM PDT 24 | 12444020000 ps | ||
| T18 | /workspace/coverage/default/20.prim_present_test.983460560 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:37:22 PM PDT 24 | 9247300000 ps | ||
| T19 | /workspace/coverage/default/29.prim_present_test.1900279751 | Jul 16 06:36:16 PM PDT 24 | Jul 16 06:36:45 PM PDT 24 | 4446640000 ps | ||
| T20 | /workspace/coverage/default/13.prim_present_test.1936259508 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:36:54 PM PDT 24 | 5185680000 ps | ||
| T21 | /workspace/coverage/default/0.prim_present_test.2018327387 | Jul 16 06:36:01 PM PDT 24 | Jul 16 06:37:00 PM PDT 24 | 10564180000 ps | ||
| T22 | /workspace/coverage/default/2.prim_present_test.1175879543 | Jul 16 06:36:03 PM PDT 24 | Jul 16 06:36:43 PM PDT 24 | 5188780000 ps | ||
| T23 | /workspace/coverage/default/31.prim_present_test.1975634529 | Jul 16 06:36:14 PM PDT 24 | Jul 16 06:37:28 PM PDT 24 | 10254800000 ps | ||
| T24 | /workspace/coverage/default/34.prim_present_test.1117725264 | Jul 16 06:36:16 PM PDT 24 | Jul 16 06:37:40 PM PDT 24 | 9420280000 ps | ||
| T25 | /workspace/coverage/default/47.prim_present_test.2588242762 | Jul 16 06:36:26 PM PDT 24 | Jul 16 06:37:48 PM PDT 24 | 11532620000 ps | ||
| T26 | /workspace/coverage/default/46.prim_present_test.2083358920 | Jul 16 06:36:26 PM PDT 24 | Jul 16 06:36:52 PM PDT 24 | 3987840000 ps | ||
| T27 | /workspace/coverage/default/23.prim_present_test.1795253563 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:37:30 PM PDT 24 | 9940460000 ps | ||
| T28 | /workspace/coverage/default/26.prim_present_test.4016425501 | Jul 16 06:36:14 PM PDT 24 | Jul 16 06:37:27 PM PDT 24 | 10166760000 ps | ||
| T29 | /workspace/coverage/default/6.prim_present_test.425142051 | Jul 16 06:36:01 PM PDT 24 | Jul 16 06:37:31 PM PDT 24 | 15134200000 ps | ||
| T30 | /workspace/coverage/default/24.prim_present_test.1285824504 | Jul 16 06:36:16 PM PDT 24 | Jul 16 06:37:54 PM PDT 24 | 14928360000 ps | ||
| T31 | /workspace/coverage/default/10.prim_present_test.4037425433 | Jul 16 06:36:00 PM PDT 24 | Jul 16 06:36:43 PM PDT 24 | 6772880000 ps | ||
| T32 | /workspace/coverage/default/3.prim_present_test.1626026888 | Jul 16 06:35:59 PM PDT 24 | Jul 16 06:36:22 PM PDT 24 | 4061620000 ps | ||
| T33 | /workspace/coverage/default/5.prim_present_test.3685002403 | Jul 16 06:36:02 PM PDT 24 | Jul 16 06:37:37 PM PDT 24 | 14082060000 ps | ||
| T34 | /workspace/coverage/default/19.prim_present_test.3127212312 | Jul 16 06:36:17 PM PDT 24 | Jul 16 06:36:47 PM PDT 24 | 4880020000 ps | ||
| T35 | /workspace/coverage/default/41.prim_present_test.3404801809 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:37:00 PM PDT 24 | 7263920000 ps | ||
| T36 | /workspace/coverage/default/25.prim_present_test.979283941 | Jul 16 06:36:13 PM PDT 24 | Jul 16 06:36:48 PM PDT 24 | 3649320000 ps | ||
| T37 | /workspace/coverage/default/44.prim_present_test.3498365476 | Jul 16 06:36:28 PM PDT 24 | Jul 16 06:37:55 PM PDT 24 | 13367820000 ps | ||
| T38 | /workspace/coverage/default/42.prim_present_test.542670934 | Jul 16 06:36:27 PM PDT 24 | Jul 16 06:37:32 PM PDT 24 | 8743860000 ps | ||
| T39 | /workspace/coverage/default/33.prim_present_test.1796500767 | Jul 16 06:36:14 PM PDT 24 | Jul 16 06:36:56 PM PDT 24 | 5049280000 ps | ||
| T40 | /workspace/coverage/default/40.prim_present_test.189224243 | Jul 16 06:36:14 PM PDT 24 | Jul 16 06:37:00 PM PDT 24 | 6639580000 ps | ||
| T41 | /workspace/coverage/default/16.prim_present_test.3219710385 | Jul 16 06:36:15 PM PDT 24 | Jul 16 06:38:01 PM PDT 24 | 14184360000 ps | ||
| T42 | /workspace/coverage/default/30.prim_present_test.4062967557 | Jul 16 06:36:17 PM PDT 24 | Jul 16 06:37:51 PM PDT 24 | 13417420000 ps | ||
| T43 | /workspace/coverage/default/4.prim_present_test.669743298 | Jul 16 06:36:00 PM PDT 24 | Jul 16 06:36:50 PM PDT 24 | 7692340000 ps | ||
| T44 | /workspace/coverage/default/11.prim_present_test.1701161223 | Jul 16 06:36:04 PM PDT 24 | Jul 16 06:37:14 PM PDT 24 | 10574100000 ps | ||
| T45 | /workspace/coverage/default/45.prim_present_test.934504761 | Jul 16 06:36:30 PM PDT 24 | Jul 16 06:37:26 PM PDT 24 | 7293680000 ps | ||
| T46 | /workspace/coverage/default/48.prim_present_test.1475363347 | Jul 16 06:36:29 PM PDT 24 | Jul 16 06:38:05 PM PDT 24 | 15020120000 ps | ||
| T47 | /workspace/coverage/default/37.prim_present_test.2776704860 | Jul 16 06:36:14 PM PDT 24 | Jul 16 06:36:45 PM PDT 24 | 4200500000 ps | ||
| T48 | /workspace/coverage/default/49.prim_present_test.607037810 | Jul 16 06:36:27 PM PDT 24 | Jul 16 06:37:09 PM PDT 24 | 6173340000 ps | ||
| T49 | /workspace/coverage/default/38.prim_present_test.3180125642 | Jul 16 06:36:13 PM PDT 24 | Jul 16 06:36:59 PM PDT 24 | 7082260000 ps | ||
| T50 | /workspace/coverage/default/12.prim_present_test.1652232619 | Jul 16 06:36:00 PM PDT 24 | Jul 16 06:37:16 PM PDT 24 | 13103080000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.1485463252 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4878160000 ps |
| CPU time | 16.05 seconds |
| Started | Jul 16 06:36:01 PM PDT 24 |
| Finished | Jul 16 06:36:32 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-c920cd84-7e50-4c55-8f8f-490acf5178fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1485463252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1485463252 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2018327387 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10564180000 ps |
| CPU time | 30.89 seconds |
| Started | Jul 16 06:36:01 PM PDT 24 |
| Finished | Jul 16 06:37:00 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-5b2cebd8-7432-4e61-a339-0b493149053a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018327387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2018327387 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.4037425433 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6772880000 ps |
| CPU time | 22.4 seconds |
| Started | Jul 16 06:36:00 PM PDT 24 |
| Finished | Jul 16 06:36:43 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-15aa94d3-ce84-4a10-bcbe-8ed37d5ec120 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037425433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.4037425433 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1701161223 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10574100000 ps |
| CPU time | 36.96 seconds |
| Started | Jul 16 06:36:04 PM PDT 24 |
| Finished | Jul 16 06:37:14 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-ee2fca1d-7b83-4299-b95e-6bebc19c7c98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701161223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1701161223 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1652232619 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13103080000 ps |
| CPU time | 39.98 seconds |
| Started | Jul 16 06:36:00 PM PDT 24 |
| Finished | Jul 16 06:37:16 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-0fcab711-a657-4d64-889c-6934c5b3f904 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652232619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1652232619 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1936259508 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5185680000 ps |
| CPU time | 19.89 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:36:54 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-5bc8eb2a-aad3-48b8-90b0-a8212c557d88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936259508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1936259508 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.366569132 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9073700000 ps |
| CPU time | 32.07 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:37:16 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-8c6b51de-2f1d-4f0a-b5c2-c3bd309c5427 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366569132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.366569132 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.942964615 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 15274940000 ps |
| CPU time | 57.3 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:38:06 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-ea1627b7-84b9-4776-bf16-74ae987d2449 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=942964615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.942964615 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3219710385 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14184360000 ps |
| CPU time | 55.23 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:38:01 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e7190510-2a26-44fb-9568-a647058249d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219710385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3219710385 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1154066041 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4469580000 ps |
| CPU time | 17.43 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:36:50 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-2c5e5539-7bbd-45a3-8563-8fc56780a7ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154066041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1154066041 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1345697 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15339420000 ps |
| CPU time | 55.73 seconds |
| Started | Jul 16 06:36:16 PM PDT 24 |
| Finished | Jul 16 06:38:02 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-807b9712-c6d5-436a-839e-2f8faf766be6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1345697 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3127212312 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4880020000 ps |
| CPU time | 15.71 seconds |
| Started | Jul 16 06:36:17 PM PDT 24 |
| Finished | Jul 16 06:36:47 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-168fb17d-c462-42bc-a681-6f912f9e329b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127212312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3127212312 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1175879543 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5188780000 ps |
| CPU time | 20.93 seconds |
| Started | Jul 16 06:36:03 PM PDT 24 |
| Finished | Jul 16 06:36:43 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-ad226590-882e-4aaf-8295-55e7fc1595dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1175879543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1175879543 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.983460560 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9247300000 ps |
| CPU time | 34.91 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:37:22 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-0d526deb-aa13-4c09-ac49-6a11446cafe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983460560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.983460560 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3561431882 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11532620000 ps |
| CPU time | 40.45 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:37:33 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-a15cf15a-4918-41ec-8d2f-69abb6861f2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561431882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3561431882 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2166224159 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7546640000 ps |
| CPU time | 28.73 seconds |
| Started | Jul 16 06:36:14 PM PDT 24 |
| Finished | Jul 16 06:37:09 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-9ca8f1f9-a54e-41c6-9468-41e3eca444b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166224159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2166224159 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1795253563 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9940460000 ps |
| CPU time | 38.04 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:37:30 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-056f4630-a2fa-4ea8-9346-19bab956e0cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795253563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1795253563 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1285824504 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14928360000 ps |
| CPU time | 50.91 seconds |
| Started | Jul 16 06:36:16 PM PDT 24 |
| Finished | Jul 16 06:37:54 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-04d5bfb6-e4e1-43de-a213-964412e8a1bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285824504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1285824504 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.979283941 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3649320000 ps |
| CPU time | 16.93 seconds |
| Started | Jul 16 06:36:13 PM PDT 24 |
| Finished | Jul 16 06:36:48 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-13262d46-a2d0-4031-a018-b536a575067d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979283941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.979283941 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.4016425501 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10166760000 ps |
| CPU time | 37.86 seconds |
| Started | Jul 16 06:36:14 PM PDT 24 |
| Finished | Jul 16 06:37:27 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-b9316fea-5e7c-4572-be26-dfefdf100f31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016425501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.4016425501 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1237587149 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13959920000 ps |
| CPU time | 43.8 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:37:38 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-220ff362-06ab-4735-b17f-0098bd4519f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237587149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1237587149 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.833520113 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6157220000 ps |
| CPU time | 23.97 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:37:03 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-b88e3994-1290-41c9-ad7c-a79e4510191c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833520113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.833520113 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1900279751 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4446640000 ps |
| CPU time | 14.98 seconds |
| Started | Jul 16 06:36:16 PM PDT 24 |
| Finished | Jul 16 06:36:45 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-765f1615-5169-49dd-b01e-875e970703d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900279751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1900279751 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1626026888 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4061620000 ps |
| CPU time | 12.06 seconds |
| Started | Jul 16 06:35:59 PM PDT 24 |
| Finished | Jul 16 06:36:22 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-ca7f3c09-8073-4b33-91da-4d85a1aab152 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626026888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1626026888 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4062967557 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13417420000 ps |
| CPU time | 49.08 seconds |
| Started | Jul 16 06:36:17 PM PDT 24 |
| Finished | Jul 16 06:37:51 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-f64c9766-ad16-49b8-9a6f-bff0c520113e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062967557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4062967557 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1975634529 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10254800000 ps |
| CPU time | 38.61 seconds |
| Started | Jul 16 06:36:14 PM PDT 24 |
| Finished | Jul 16 06:37:28 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-79ceadc6-9acf-4f10-b4e1-936917f50bdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975634529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1975634529 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2439421729 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13429820000 ps |
| CPU time | 45.63 seconds |
| Started | Jul 16 06:36:16 PM PDT 24 |
| Finished | Jul 16 06:37:43 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-4170e525-b418-4b37-86c0-727d18b7af0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439421729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2439421729 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1796500767 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5049280000 ps |
| CPU time | 21.18 seconds |
| Started | Jul 16 06:36:14 PM PDT 24 |
| Finished | Jul 16 06:36:56 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-f60a01b0-71af-47d0-ad75-0716295310cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796500767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1796500767 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1117725264 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9420280000 ps |
| CPU time | 41.31 seconds |
| Started | Jul 16 06:36:16 PM PDT 24 |
| Finished | Jul 16 06:37:40 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-e21f74bb-0818-4b6a-bfdf-17e90b6ece7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117725264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1117725264 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2426876452 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13556920000 ps |
| CPU time | 51.56 seconds |
| Started | Jul 16 06:36:13 PM PDT 24 |
| Finished | Jul 16 06:37:53 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-5394de2d-52f9-4087-8b3e-b87fedbe1e47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426876452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2426876452 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.519834372 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12444020000 ps |
| CPU time | 44.28 seconds |
| Started | Jul 16 06:36:21 PM PDT 24 |
| Finished | Jul 16 06:37:46 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-3ed2016d-7516-4469-944b-55b75f3b8d2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519834372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.519834372 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2776704860 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4200500000 ps |
| CPU time | 15.89 seconds |
| Started | Jul 16 06:36:14 PM PDT 24 |
| Finished | Jul 16 06:36:45 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-07805bf5-b812-4fcd-8e28-2133934cfb72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776704860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2776704860 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3180125642 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7082260000 ps |
| CPU time | 23.85 seconds |
| Started | Jul 16 06:36:13 PM PDT 24 |
| Finished | Jul 16 06:36:59 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-7fc13bf3-db50-4fee-ad11-352c4b3b35b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180125642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3180125642 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3445289431 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12773860000 ps |
| CPU time | 53.03 seconds |
| Started | Jul 16 06:36:16 PM PDT 24 |
| Finished | Jul 16 06:38:04 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-52d52037-ece0-488e-935d-65d89a67843c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445289431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3445289431 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.669743298 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7692340000 ps |
| CPU time | 26.22 seconds |
| Started | Jul 16 06:36:00 PM PDT 24 |
| Finished | Jul 16 06:36:50 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-b48f44b2-cc72-4570-bc6a-4b3e0376af9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669743298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.669743298 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.189224243 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6639580000 ps |
| CPU time | 23.7 seconds |
| Started | Jul 16 06:36:14 PM PDT 24 |
| Finished | Jul 16 06:37:00 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-3ca0f1be-7144-4ec0-83ad-410a68ceef2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189224243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.189224243 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3404801809 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7263920000 ps |
| CPU time | 23.43 seconds |
| Started | Jul 16 06:36:15 PM PDT 24 |
| Finished | Jul 16 06:37:00 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-d0c3699f-857a-4f7c-af53-9d4b3b5fcce4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404801809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3404801809 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.542670934 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8743860000 ps |
| CPU time | 33.35 seconds |
| Started | Jul 16 06:36:27 PM PDT 24 |
| Finished | Jul 16 06:37:32 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-ea5b4e45-9ef9-4996-afe3-c603578a911a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542670934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.542670934 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2091881399 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15193720000 ps |
| CPU time | 58.3 seconds |
| Started | Jul 16 06:36:27 PM PDT 24 |
| Finished | Jul 16 06:38:17 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-8bca9660-96a0-426f-b416-05a868fd2775 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091881399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2091881399 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3498365476 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13367820000 ps |
| CPU time | 46.27 seconds |
| Started | Jul 16 06:36:28 PM PDT 24 |
| Finished | Jul 16 06:37:55 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-7777f949-499b-427e-9b15-115d846ef74b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498365476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3498365476 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.934504761 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7293680000 ps |
| CPU time | 28.78 seconds |
| Started | Jul 16 06:36:30 PM PDT 24 |
| Finished | Jul 16 06:37:26 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-b1298d21-5a5a-468b-b2da-5a2999301e7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934504761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.934504761 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2083358920 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3987840000 ps |
| CPU time | 13.52 seconds |
| Started | Jul 16 06:36:26 PM PDT 24 |
| Finished | Jul 16 06:36:52 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-9ce7ee32-ca36-4fb1-93cd-7532a6c89f16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083358920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2083358920 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2588242762 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11532620000 ps |
| CPU time | 43.95 seconds |
| Started | Jul 16 06:36:26 PM PDT 24 |
| Finished | Jul 16 06:37:48 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-3c169637-08b9-48ce-a321-459e9ba74846 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588242762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2588242762 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1475363347 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15020120000 ps |
| CPU time | 51.25 seconds |
| Started | Jul 16 06:36:29 PM PDT 24 |
| Finished | Jul 16 06:38:05 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-35e4e7de-bd6c-46c8-86d5-c4c00a8142a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475363347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1475363347 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.607037810 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6173340000 ps |
| CPU time | 21.89 seconds |
| Started | Jul 16 06:36:27 PM PDT 24 |
| Finished | Jul 16 06:37:09 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-51527d62-149b-444e-941e-5ab2f9fc7aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607037810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.607037810 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3685002403 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14082060000 ps |
| CPU time | 50 seconds |
| Started | Jul 16 06:36:02 PM PDT 24 |
| Finished | Jul 16 06:37:37 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-9adddc6d-a385-4e51-bebd-a791fc70cffc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685002403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3685002403 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.425142051 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 15134200000 ps |
| CPU time | 47.55 seconds |
| Started | Jul 16 06:36:01 PM PDT 24 |
| Finished | Jul 16 06:37:31 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-ad46f150-715e-4c7b-bbc5-f205bc51ae03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425142051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.425142051 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1604717 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9843120000 ps |
| CPU time | 35.22 seconds |
| Started | Jul 16 06:36:00 PM PDT 24 |
| Finished | Jul 16 06:37:08 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-10eb1891-1471-4043-8290-c0094b6400b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1604717 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1874076052 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13554440000 ps |
| CPU time | 45.7 seconds |
| Started | Jul 16 06:36:01 PM PDT 24 |
| Finished | Jul 16 06:37:29 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-e91f4b6c-6cb5-4a3d-8c39-1fd406c2c829 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874076052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1874076052 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2768008306 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13028680000 ps |
| CPU time | 45.51 seconds |
| Started | Jul 16 06:36:01 PM PDT 24 |
| Finished | Jul 16 06:37:28 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-0090c6be-c718-4456-bfbd-31b6caa9d03f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768008306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2768008306 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |