| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2434873282 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.3703875394 |
| /workspace/coverage/default/10.prim_present_test.885240058 |
| /workspace/coverage/default/11.prim_present_test.2931882637 |
| /workspace/coverage/default/12.prim_present_test.3493062284 |
| /workspace/coverage/default/13.prim_present_test.2084267698 |
| /workspace/coverage/default/14.prim_present_test.1710870550 |
| /workspace/coverage/default/15.prim_present_test.2058920245 |
| /workspace/coverage/default/16.prim_present_test.3886737040 |
| /workspace/coverage/default/17.prim_present_test.2179250532 |
| /workspace/coverage/default/18.prim_present_test.3542003002 |
| /workspace/coverage/default/19.prim_present_test.1755207770 |
| /workspace/coverage/default/2.prim_present_test.1293133042 |
| /workspace/coverage/default/20.prim_present_test.1580771736 |
| /workspace/coverage/default/21.prim_present_test.2276440679 |
| /workspace/coverage/default/22.prim_present_test.3136292550 |
| /workspace/coverage/default/23.prim_present_test.157358645 |
| /workspace/coverage/default/24.prim_present_test.3217843047 |
| /workspace/coverage/default/25.prim_present_test.667764504 |
| /workspace/coverage/default/26.prim_present_test.854557665 |
| /workspace/coverage/default/27.prim_present_test.1711509729 |
| /workspace/coverage/default/28.prim_present_test.54328332 |
| /workspace/coverage/default/29.prim_present_test.1546238821 |
| /workspace/coverage/default/3.prim_present_test.330573991 |
| /workspace/coverage/default/30.prim_present_test.1864555736 |
| /workspace/coverage/default/31.prim_present_test.2982993493 |
| /workspace/coverage/default/32.prim_present_test.3601922768 |
| /workspace/coverage/default/33.prim_present_test.3027295211 |
| /workspace/coverage/default/34.prim_present_test.244702244 |
| /workspace/coverage/default/35.prim_present_test.2050285603 |
| /workspace/coverage/default/36.prim_present_test.3121575106 |
| /workspace/coverage/default/37.prim_present_test.58260392 |
| /workspace/coverage/default/38.prim_present_test.4216596317 |
| /workspace/coverage/default/39.prim_present_test.100279524 |
| /workspace/coverage/default/4.prim_present_test.3039871726 |
| /workspace/coverage/default/40.prim_present_test.2393346440 |
| /workspace/coverage/default/41.prim_present_test.2553543396 |
| /workspace/coverage/default/42.prim_present_test.4164959951 |
| /workspace/coverage/default/43.prim_present_test.2362078298 |
| /workspace/coverage/default/44.prim_present_test.3873096932 |
| /workspace/coverage/default/45.prim_present_test.18887451 |
| /workspace/coverage/default/46.prim_present_test.2032590003 |
| /workspace/coverage/default/47.prim_present_test.391650216 |
| /workspace/coverage/default/48.prim_present_test.761808963 |
| /workspace/coverage/default/49.prim_present_test.160016058 |
| /workspace/coverage/default/5.prim_present_test.1279478027 |
| /workspace/coverage/default/6.prim_present_test.2992886330 |
| /workspace/coverage/default/7.prim_present_test.1653003334 |
| /workspace/coverage/default/8.prim_present_test.3911616696 |
| /workspace/coverage/default/9.prim_present_test.1771642642 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/8.prim_present_test.3911616696 | Jul 17 07:04:57 PM PDT 24 | Jul 17 07:05:25 PM PDT 24 | 3842760000 ps | ||
| T2 | /workspace/coverage/default/47.prim_present_test.391650216 | Jul 17 07:05:27 PM PDT 24 | Jul 17 07:05:54 PM PDT 24 | 4504300000 ps | ||
| T3 | /workspace/coverage/default/3.prim_present_test.330573991 | Jul 17 07:04:58 PM PDT 24 | Jul 17 07:05:56 PM PDT 24 | 8910640000 ps | ||
| T4 | /workspace/coverage/default/11.prim_present_test.2931882637 | Jul 17 07:04:59 PM PDT 24 | Jul 17 07:06:34 PM PDT 24 | 14680980000 ps | ||
| T5 | /workspace/coverage/default/26.prim_present_test.854557665 | Jul 17 07:04:49 PM PDT 24 | Jul 17 07:05:31 PM PDT 24 | 4671080000 ps | ||
| T6 | /workspace/coverage/default/38.prim_present_test.4216596317 | Jul 17 07:04:55 PM PDT 24 | Jul 17 07:05:22 PM PDT 24 | 4485080000 ps | ||
| T7 | /workspace/coverage/default/27.prim_present_test.1711509729 | Jul 17 07:04:47 PM PDT 24 | Jul 17 07:05:12 PM PDT 24 | 3510440000 ps | ||
| T8 | /workspace/coverage/default/13.prim_present_test.2084267698 | Jul 17 07:04:59 PM PDT 24 | Jul 17 07:05:51 PM PDT 24 | 6888200000 ps | ||
| T9 | /workspace/coverage/default/0.prim_present_test.2434873282 | Jul 17 07:04:47 PM PDT 24 | Jul 17 07:05:22 PM PDT 24 | 4189340000 ps | ||
| T10 | /workspace/coverage/default/34.prim_present_test.244702244 | Jul 17 07:04:49 PM PDT 24 | Jul 17 07:06:33 PM PDT 24 | 13919000000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.100279524 | Jul 17 07:04:58 PM PDT 24 | Jul 17 07:05:21 PM PDT 24 | 3211600000 ps | ||
| T12 | /workspace/coverage/default/4.prim_present_test.3039871726 | Jul 17 07:04:53 PM PDT 24 | Jul 17 07:05:20 PM PDT 24 | 3399460000 ps | ||
| T13 | /workspace/coverage/default/12.prim_present_test.3493062284 | Jul 17 07:04:52 PM PDT 24 | Jul 17 07:06:01 PM PDT 24 | 9531880000 ps | ||
| T14 | /workspace/coverage/default/49.prim_present_test.160016058 | Jul 17 07:05:28 PM PDT 24 | Jul 17 07:06:14 PM PDT 24 | 6324620000 ps | ||
| T15 | /workspace/coverage/default/44.prim_present_test.3873096932 | Jul 17 07:05:28 PM PDT 24 | Jul 17 07:06:46 PM PDT 24 | 13424860000 ps | ||
| T16 | /workspace/coverage/default/10.prim_present_test.885240058 | Jul 17 07:04:46 PM PDT 24 | Jul 17 07:05:27 PM PDT 24 | 5973700000 ps | ||
| T17 | /workspace/coverage/default/33.prim_present_test.3027295211 | Jul 17 07:04:49 PM PDT 24 | Jul 17 07:05:47 PM PDT 24 | 9666420000 ps | ||
| T18 | /workspace/coverage/default/32.prim_present_test.3601922768 | Jul 17 07:04:47 PM PDT 24 | Jul 17 07:06:15 PM PDT 24 | 11397460000 ps | ||
| T19 | /workspace/coverage/default/37.prim_present_test.58260392 | Jul 17 07:04:52 PM PDT 24 | Jul 17 07:06:32 PM PDT 24 | 14928980000 ps | ||
| T20 | /workspace/coverage/default/18.prim_present_test.3542003002 | Jul 17 07:04:57 PM PDT 24 | Jul 17 07:06:22 PM PDT 24 | 12842060000 ps | ||
| T21 | /workspace/coverage/default/20.prim_present_test.1580771736 | Jul 17 07:05:00 PM PDT 24 | Jul 17 07:06:27 PM PDT 24 | 13359140000 ps | ||
| T22 | /workspace/coverage/default/24.prim_present_test.3217843047 | Jul 17 07:04:58 PM PDT 24 | Jul 17 07:05:54 PM PDT 24 | 7323440000 ps | ||
| T23 | /workspace/coverage/default/43.prim_present_test.2362078298 | Jul 17 07:05:27 PM PDT 24 | Jul 17 07:05:49 PM PDT 24 | 3437900000 ps | ||
| T24 | /workspace/coverage/default/48.prim_present_test.761808963 | Jul 17 07:05:30 PM PDT 24 | Jul 17 07:06:29 PM PDT 24 | 8651480000 ps | ||
| T25 | /workspace/coverage/default/30.prim_present_test.1864555736 | Jul 17 07:04:49 PM PDT 24 | Jul 17 07:05:56 PM PDT 24 | 8820740000 ps | ||
| T26 | /workspace/coverage/default/23.prim_present_test.157358645 | Jul 17 07:04:50 PM PDT 24 | Jul 17 07:06:10 PM PDT 24 | 11360880000 ps | ||
| T27 | /workspace/coverage/default/9.prim_present_test.1771642642 | Jul 17 07:04:58 PM PDT 24 | Jul 17 07:06:34 PM PDT 24 | 15429940000 ps | ||
| T28 | /workspace/coverage/default/41.prim_present_test.2553543396 | Jul 17 07:04:59 PM PDT 24 | Jul 17 07:05:34 PM PDT 24 | 5377880000 ps | ||
| T29 | /workspace/coverage/default/6.prim_present_test.2992886330 | Jul 17 07:04:53 PM PDT 24 | Jul 17 07:06:26 PM PDT 24 | 13573660000 ps | ||
| T30 | /workspace/coverage/default/45.prim_present_test.18887451 | Jul 17 07:05:29 PM PDT 24 | Jul 17 07:06:10 PM PDT 24 | 5260700000 ps | ||
| T31 | /workspace/coverage/default/29.prim_present_test.1546238821 | Jul 17 07:04:49 PM PDT 24 | Jul 17 07:06:07 PM PDT 24 | 9534360000 ps | ||
| T32 | /workspace/coverage/default/21.prim_present_test.2276440679 | Jul 17 07:04:48 PM PDT 24 | Jul 17 07:05:20 PM PDT 24 | 4708280000 ps | ||
| T33 | /workspace/coverage/default/36.prim_present_test.3121575106 | Jul 17 07:04:52 PM PDT 24 | Jul 17 07:05:19 PM PDT 24 | 3161380000 ps | ||
| T34 | /workspace/coverage/default/19.prim_present_test.1755207770 | Jul 17 07:04:59 PM PDT 24 | Jul 17 07:06:22 PM PDT 24 | 12255540000 ps | ||
| T35 | /workspace/coverage/default/16.prim_present_test.3886737040 | Jul 17 07:04:53 PM PDT 24 | Jul 17 07:06:24 PM PDT 24 | 13343020000 ps | ||
| T36 | /workspace/coverage/default/46.prim_present_test.2032590003 | Jul 17 07:05:28 PM PDT 24 | Jul 17 07:06:12 PM PDT 24 | 6364300000 ps | ||
| T37 | /workspace/coverage/default/40.prim_present_test.2393346440 | Jul 17 07:04:52 PM PDT 24 | Jul 17 07:05:41 PM PDT 24 | 6453580000 ps | ||
| T38 | /workspace/coverage/default/7.prim_present_test.1653003334 | Jul 17 07:04:46 PM PDT 24 | Jul 17 07:06:15 PM PDT 24 | 15269980000 ps | ||
| T39 | /workspace/coverage/default/2.prim_present_test.1293133042 | Jul 17 07:04:48 PM PDT 24 | Jul 17 07:06:09 PM PDT 24 | 12277240000 ps | ||
| T40 | /workspace/coverage/default/42.prim_present_test.4164959951 | Jul 17 07:04:51 PM PDT 24 | Jul 17 07:06:21 PM PDT 24 | 13038600000 ps | ||
| T41 | /workspace/coverage/default/17.prim_present_test.2179250532 | Jul 17 07:05:00 PM PDT 24 | Jul 17 07:05:48 PM PDT 24 | 6326480000 ps | ||
| T42 | /workspace/coverage/default/25.prim_present_test.667764504 | Jul 17 07:04:47 PM PDT 24 | Jul 17 07:05:28 PM PDT 24 | 5650680000 ps | ||
| T43 | /workspace/coverage/default/1.prim_present_test.3703875394 | Jul 17 07:04:59 PM PDT 24 | Jul 17 07:05:43 PM PDT 24 | 6915480000 ps | ||
| T44 | /workspace/coverage/default/35.prim_present_test.2050285603 | Jul 17 07:04:47 PM PDT 24 | Jul 17 07:06:29 PM PDT 24 | 14248840000 ps | ||
| T45 | /workspace/coverage/default/15.prim_present_test.2058920245 | Jul 17 07:04:58 PM PDT 24 | Jul 17 07:05:43 PM PDT 24 | 5871400000 ps | ||
| T46 | /workspace/coverage/default/14.prim_present_test.1710870550 | Jul 17 07:04:59 PM PDT 24 | Jul 17 07:06:12 PM PDT 24 | 10310600000 ps | ||
| T47 | /workspace/coverage/default/5.prim_present_test.1279478027 | Jul 17 07:04:53 PM PDT 24 | Jul 17 07:05:30 PM PDT 24 | 4840960000 ps | ||
| T48 | /workspace/coverage/default/22.prim_present_test.3136292550 | Jul 17 07:04:53 PM PDT 24 | Jul 17 07:05:45 PM PDT 24 | 7034520000 ps | ||
| T49 | /workspace/coverage/default/31.prim_present_test.2982993493 | Jul 17 07:04:47 PM PDT 24 | Jul 17 07:06:14 PM PDT 24 | 11303840000 ps | ||
| T50 | /workspace/coverage/default/28.prim_present_test.54328332 | Jul 17 07:04:48 PM PDT 24 | Jul 17 07:06:24 PM PDT 24 | 13202280000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2434873282 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4189340000 ps |
| CPU time | 16.16 seconds |
| Started | Jul 17 07:04:47 PM PDT 24 |
| Finished | Jul 17 07:05:22 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-00b37c8b-9fc4-43e5-9bf9-89810cd31118 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2434873282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2434873282 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3703875394 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6915480000 ps |
| CPU time | 22.89 seconds |
| Started | Jul 17 07:04:59 PM PDT 24 |
| Finished | Jul 17 07:05:43 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-b31a12bd-ca2c-4b52-8d95-1802704bdd68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703875394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3703875394 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.885240058 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5973700000 ps |
| CPU time | 20.53 seconds |
| Started | Jul 17 07:04:46 PM PDT 24 |
| Finished | Jul 17 07:05:27 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-cfa5df82-4c51-4ffe-a53f-e8a16249b347 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885240058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.885240058 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2931882637 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14680980000 ps |
| CPU time | 49.05 seconds |
| Started | Jul 17 07:04:59 PM PDT 24 |
| Finished | Jul 17 07:06:34 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-c1bf62a8-cbf9-4d58-be28-173ad0c29d30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2931882637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2931882637 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3493062284 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9531880000 ps |
| CPU time | 34.08 seconds |
| Started | Jul 17 07:04:52 PM PDT 24 |
| Finished | Jul 17 07:06:01 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-2490997d-eb6c-4172-872c-d848846d74ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493062284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3493062284 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2084267698 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6888200000 ps |
| CPU time | 25.75 seconds |
| Started | Jul 17 07:04:59 PM PDT 24 |
| Finished | Jul 17 07:05:51 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-b1c71bd1-8d62-4bf1-bbd9-0754f629c9ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084267698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2084267698 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1710870550 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10310600000 ps |
| CPU time | 36.66 seconds |
| Started | Jul 17 07:04:59 PM PDT 24 |
| Finished | Jul 17 07:06:12 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-a37a0fe5-4182-44d1-bc98-5316c457711b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710870550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1710870550 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2058920245 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5871400000 ps |
| CPU time | 22.14 seconds |
| Started | Jul 17 07:04:58 PM PDT 24 |
| Finished | Jul 17 07:05:43 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-fc70af8f-8c8f-4229-92cf-452b0e80586f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058920245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2058920245 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3886737040 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13343020000 ps |
| CPU time | 46.41 seconds |
| Started | Jul 17 07:04:53 PM PDT 24 |
| Finished | Jul 17 07:06:24 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-840f06f8-da66-4a7b-8510-06cf23884320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886737040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3886737040 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2179250532 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6326480000 ps |
| CPU time | 24.25 seconds |
| Started | Jul 17 07:05:00 PM PDT 24 |
| Finished | Jul 17 07:05:48 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-cb99a453-e946-4a3f-a3b4-ff4e11a562ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179250532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2179250532 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3542003002 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12842060000 ps |
| CPU time | 43.23 seconds |
| Started | Jul 17 07:04:57 PM PDT 24 |
| Finished | Jul 17 07:06:22 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-7a54199d-51ee-4367-b7f4-d25304ee4249 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542003002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3542003002 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1755207770 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12255540000 ps |
| CPU time | 42.46 seconds |
| Started | Jul 17 07:04:59 PM PDT 24 |
| Finished | Jul 17 07:06:22 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-6369ea25-bf8a-47a4-9ad2-95b27ce7ec2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755207770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1755207770 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1293133042 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12277240000 ps |
| CPU time | 41.07 seconds |
| Started | Jul 17 07:04:48 PM PDT 24 |
| Finished | Jul 17 07:06:09 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-6ce3649d-059e-4cbb-af6c-bcef8153a90d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293133042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1293133042 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1580771736 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13359140000 ps |
| CPU time | 44.63 seconds |
| Started | Jul 17 07:05:00 PM PDT 24 |
| Finished | Jul 17 07:06:27 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-791be755-7c07-4b49-9e9e-ff3f643f973b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580771736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1580771736 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2276440679 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4708280000 ps |
| CPU time | 15.32 seconds |
| Started | Jul 17 07:04:48 PM PDT 24 |
| Finished | Jul 17 07:05:20 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-9fa94ce6-a7a8-41f5-90b5-e75dfa1be538 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276440679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2276440679 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3136292550 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7034520000 ps |
| CPU time | 25.43 seconds |
| Started | Jul 17 07:04:53 PM PDT 24 |
| Finished | Jul 17 07:05:45 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-8e771861-f19d-4fd1-bf7a-eb09ac14a369 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136292550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3136292550 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.157358645 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11360880000 ps |
| CPU time | 40.21 seconds |
| Started | Jul 17 07:04:50 PM PDT 24 |
| Finished | Jul 17 07:06:10 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-e8621542-b3bc-4f29-8b8d-1ded1d6c945b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157358645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.157358645 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3217843047 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7323440000 ps |
| CPU time | 27.58 seconds |
| Started | Jul 17 07:04:58 PM PDT 24 |
| Finished | Jul 17 07:05:54 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-a98a5f68-f60c-4e17-a529-b71217461140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217843047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3217843047 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.667764504 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5650680000 ps |
| CPU time | 19.89 seconds |
| Started | Jul 17 07:04:47 PM PDT 24 |
| Finished | Jul 17 07:05:28 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-9bbe6fd3-738e-4dec-a561-a29b79215b99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=667764504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.667764504 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.854557665 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4671080000 ps |
| CPU time | 19.05 seconds |
| Started | Jul 17 07:04:49 PM PDT 24 |
| Finished | Jul 17 07:05:31 PM PDT 24 |
| Peak memory | 143556 kb |
| Host | smart-1e0601c5-b8d3-49d9-b1b1-0de906fc5300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854557665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.854557665 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1711509729 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3510440000 ps |
| CPU time | 11.8 seconds |
| Started | Jul 17 07:04:47 PM PDT 24 |
| Finished | Jul 17 07:05:12 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-e9c49c58-6475-4d43-9b62-3e485989554e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711509729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1711509729 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.54328332 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13202280000 ps |
| CPU time | 49.83 seconds |
| Started | Jul 17 07:04:48 PM PDT 24 |
| Finished | Jul 17 07:06:24 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-16ffd72e-e31c-469b-a84c-0ff3fd5a8fc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54328332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.54328332 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1546238821 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9534360000 ps |
| CPU time | 37.48 seconds |
| Started | Jul 17 07:04:49 PM PDT 24 |
| Finished | Jul 17 07:06:07 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-81cec5ee-ba38-463a-87f7-da6e6e4bdad9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1546238821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1546238821 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.330573991 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8910640000 ps |
| CPU time | 30.23 seconds |
| Started | Jul 17 07:04:58 PM PDT 24 |
| Finished | Jul 17 07:05:56 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-344cc3e5-54be-440d-a771-5d38b3bde12b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330573991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.330573991 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1864555736 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8820740000 ps |
| CPU time | 33.5 seconds |
| Started | Jul 17 07:04:49 PM PDT 24 |
| Finished | Jul 17 07:05:56 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-45053ab4-013c-4a70-a36f-98c8b1bbfda1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864555736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1864555736 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2982993493 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11303840000 ps |
| CPU time | 42.51 seconds |
| Started | Jul 17 07:04:47 PM PDT 24 |
| Finished | Jul 17 07:06:14 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-8f41737d-2286-4023-a9a1-9eefe6a25ef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982993493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2982993493 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3601922768 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11397460000 ps |
| CPU time | 42.66 seconds |
| Started | Jul 17 07:04:47 PM PDT 24 |
| Finished | Jul 17 07:06:15 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-ce18652f-a144-4450-9779-38de64a79e91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601922768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3601922768 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3027295211 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9666420000 ps |
| CPU time | 28.76 seconds |
| Started | Jul 17 07:04:49 PM PDT 24 |
| Finished | Jul 17 07:05:47 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-83e28f6f-14cc-47ef-b1f5-26b89f079c35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027295211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3027295211 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.244702244 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13919000000 ps |
| CPU time | 51.27 seconds |
| Started | Jul 17 07:04:49 PM PDT 24 |
| Finished | Jul 17 07:06:33 PM PDT 24 |
| Peak memory | 143548 kb |
| Host | smart-2e28fa56-f26b-4708-bf89-f765d11be730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244702244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.244702244 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2050285603 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14248840000 ps |
| CPU time | 50.38 seconds |
| Started | Jul 17 07:04:47 PM PDT 24 |
| Finished | Jul 17 07:06:29 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-c32538b0-f0fe-4df1-999f-568336cbfe97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050285603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2050285603 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3121575106 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3161380000 ps |
| CPU time | 12.15 seconds |
| Started | Jul 17 07:04:52 PM PDT 24 |
| Finished | Jul 17 07:05:19 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-91fb4cd2-9b65-4656-b8c8-d8cb49dc4b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121575106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3121575106 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.58260392 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14928980000 ps |
| CPU time | 50.6 seconds |
| Started | Jul 17 07:04:52 PM PDT 24 |
| Finished | Jul 17 07:06:32 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-ab60af90-19d7-4316-a12e-e9f84d622945 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58260392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.58260392 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.4216596317 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4485080000 ps |
| CPU time | 14.03 seconds |
| Started | Jul 17 07:04:55 PM PDT 24 |
| Finished | Jul 17 07:05:22 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-6432249f-5303-4e54-9f12-8f42aad18af1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216596317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.4216596317 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.100279524 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3211600000 ps |
| CPU time | 11.73 seconds |
| Started | Jul 17 07:04:58 PM PDT 24 |
| Finished | Jul 17 07:05:21 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-a5b08885-148c-47ab-b623-157b513f893a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100279524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.100279524 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3039871726 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3399460000 ps |
| CPU time | 12.65 seconds |
| Started | Jul 17 07:04:53 PM PDT 24 |
| Finished | Jul 17 07:05:20 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-b4969537-813f-48e0-b12e-34247d114efd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039871726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3039871726 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2393346440 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6453580000 ps |
| CPU time | 23.8 seconds |
| Started | Jul 17 07:04:52 PM PDT 24 |
| Finished | Jul 17 07:05:41 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-672b9856-605a-40ca-8865-12963841c6c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393346440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2393346440 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2553543396 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5377880000 ps |
| CPU time | 18.14 seconds |
| Started | Jul 17 07:04:59 PM PDT 24 |
| Finished | Jul 17 07:05:34 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-04b254cb-386c-40ed-a073-a46b7ebbbaa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2553543396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2553543396 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4164959951 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13038600000 ps |
| CPU time | 45.09 seconds |
| Started | Jul 17 07:04:51 PM PDT 24 |
| Finished | Jul 17 07:06:21 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-a1d9c3bf-b58f-4a4c-b1db-8ef80f37e5c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164959951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4164959951 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2362078298 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3437900000 ps |
| CPU time | 11 seconds |
| Started | Jul 17 07:05:27 PM PDT 24 |
| Finished | Jul 17 07:05:49 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-4aad525e-3b9f-46a2-8747-5787299d658b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362078298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2362078298 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3873096932 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13424860000 ps |
| CPU time | 41.04 seconds |
| Started | Jul 17 07:05:28 PM PDT 24 |
| Finished | Jul 17 07:06:46 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-661102cd-6ec0-4f7f-b7fd-e8f864a498d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873096932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3873096932 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.18887451 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5260700000 ps |
| CPU time | 19.52 seconds |
| Started | Jul 17 07:05:29 PM PDT 24 |
| Finished | Jul 17 07:06:10 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-dd15d6ca-f2de-416e-a952-65add4fcd6f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18887451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.18887451 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2032590003 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6364300000 ps |
| CPU time | 22.51 seconds |
| Started | Jul 17 07:05:28 PM PDT 24 |
| Finished | Jul 17 07:06:12 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-b156d52d-49fc-420a-9b6e-c0eb1b817ef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032590003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2032590003 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.391650216 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4504300000 ps |
| CPU time | 13.86 seconds |
| Started | Jul 17 07:05:27 PM PDT 24 |
| Finished | Jul 17 07:05:54 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-8db7f1d4-a868-46c9-9c19-1f4d51850437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391650216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.391650216 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.761808963 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8651480000 ps |
| CPU time | 28.91 seconds |
| Started | Jul 17 07:05:30 PM PDT 24 |
| Finished | Jul 17 07:06:29 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-7eabe75d-aaf5-4cc6-8114-c5fac67c85d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761808963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.761808963 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.160016058 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6324620000 ps |
| CPU time | 22.57 seconds |
| Started | Jul 17 07:05:28 PM PDT 24 |
| Finished | Jul 17 07:06:14 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-3139894b-5478-448e-a370-b340fed86910 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160016058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.160016058 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1279478027 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4840960000 ps |
| CPU time | 17.57 seconds |
| Started | Jul 17 07:04:53 PM PDT 24 |
| Finished | Jul 17 07:05:30 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-bc14cdd7-b28a-429c-8d18-b8582cb660f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279478027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1279478027 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2992886330 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13573660000 ps |
| CPU time | 47.1 seconds |
| Started | Jul 17 07:04:53 PM PDT 24 |
| Finished | Jul 17 07:06:26 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-94ab934c-5f2c-4531-a9b6-61110dbea12e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992886330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2992886330 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1653003334 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 15269980000 ps |
| CPU time | 46.67 seconds |
| Started | Jul 17 07:04:46 PM PDT 24 |
| Finished | Jul 17 07:06:15 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-cc3ef620-395a-4d93-8b96-0334e225d145 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653003334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1653003334 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3911616696 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3842760000 ps |
| CPU time | 13.9 seconds |
| Started | Jul 17 07:04:57 PM PDT 24 |
| Finished | Jul 17 07:05:25 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-657c9a4d-7d1c-4b99-b836-8272674c0300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911616696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3911616696 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1771642642 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 15429940000 ps |
| CPU time | 50.68 seconds |
| Started | Jul 17 07:04:58 PM PDT 24 |
| Finished | Jul 17 07:06:34 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-ea8a0feb-d67a-4ef9-a3fa-36e35909c244 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771642642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1771642642 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |