| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.2049504560 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.698933409 |
| /workspace/coverage/default/1.prim_present_test.2193137573 |
| /workspace/coverage/default/11.prim_present_test.1584297389 |
| /workspace/coverage/default/12.prim_present_test.2268324928 |
| /workspace/coverage/default/13.prim_present_test.1315319678 |
| /workspace/coverage/default/14.prim_present_test.280433808 |
| /workspace/coverage/default/15.prim_present_test.2270550197 |
| /workspace/coverage/default/16.prim_present_test.2776010233 |
| /workspace/coverage/default/17.prim_present_test.3790151 |
| /workspace/coverage/default/18.prim_present_test.1688246976 |
| /workspace/coverage/default/19.prim_present_test.1527497328 |
| /workspace/coverage/default/2.prim_present_test.4163891356 |
| /workspace/coverage/default/20.prim_present_test.1051817877 |
| /workspace/coverage/default/21.prim_present_test.298012235 |
| /workspace/coverage/default/22.prim_present_test.428038258 |
| /workspace/coverage/default/23.prim_present_test.3437202636 |
| /workspace/coverage/default/24.prim_present_test.2686263848 |
| /workspace/coverage/default/25.prim_present_test.935399845 |
| /workspace/coverage/default/26.prim_present_test.2028408417 |
| /workspace/coverage/default/27.prim_present_test.3567657060 |
| /workspace/coverage/default/28.prim_present_test.2858699362 |
| /workspace/coverage/default/29.prim_present_test.3769067585 |
| /workspace/coverage/default/3.prim_present_test.1023857671 |
| /workspace/coverage/default/30.prim_present_test.4102597730 |
| /workspace/coverage/default/31.prim_present_test.3073962519 |
| /workspace/coverage/default/32.prim_present_test.1585823775 |
| /workspace/coverage/default/33.prim_present_test.905824252 |
| /workspace/coverage/default/34.prim_present_test.457471213 |
| /workspace/coverage/default/35.prim_present_test.3898997594 |
| /workspace/coverage/default/36.prim_present_test.2978472127 |
| /workspace/coverage/default/37.prim_present_test.1447834905 |
| /workspace/coverage/default/38.prim_present_test.2782438806 |
| /workspace/coverage/default/39.prim_present_test.559656570 |
| /workspace/coverage/default/4.prim_present_test.3856822822 |
| /workspace/coverage/default/40.prim_present_test.2769471833 |
| /workspace/coverage/default/41.prim_present_test.1663817176 |
| /workspace/coverage/default/42.prim_present_test.224810473 |
| /workspace/coverage/default/43.prim_present_test.86347445 |
| /workspace/coverage/default/44.prim_present_test.3792568424 |
| /workspace/coverage/default/45.prim_present_test.3470685545 |
| /workspace/coverage/default/46.prim_present_test.3332182834 |
| /workspace/coverage/default/47.prim_present_test.15000524 |
| /workspace/coverage/default/48.prim_present_test.3215672748 |
| /workspace/coverage/default/49.prim_present_test.1538196642 |
| /workspace/coverage/default/5.prim_present_test.1596475991 |
| /workspace/coverage/default/6.prim_present_test.3202112584 |
| /workspace/coverage/default/7.prim_present_test.118170852 |
| /workspace/coverage/default/8.prim_present_test.1132347185 |
| /workspace/coverage/default/9.prim_present_test.694181446 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_present_test.4163891356 | Jul 18 04:28:49 PM PDT 24 | Jul 18 04:30:06 PM PDT 24 | 12148900000 ps | ||
| T2 | /workspace/coverage/default/15.prim_present_test.2270550197 | Jul 18 04:30:23 PM PDT 24 | Jul 18 04:32:02 PM PDT 24 | 13687120000 ps | ||
| T3 | /workspace/coverage/default/3.prim_present_test.1023857671 | Jul 18 04:28:53 PM PDT 24 | Jul 18 04:30:27 PM PDT 24 | 13611480000 ps | ||
| T4 | /workspace/coverage/default/38.prim_present_test.2782438806 | Jul 18 04:30:08 PM PDT 24 | Jul 18 04:31:22 PM PDT 24 | 13200420000 ps | ||
| T5 | /workspace/coverage/default/16.prim_present_test.2776010233 | Jul 18 04:30:11 PM PDT 24 | Jul 18 04:31:32 PM PDT 24 | 12734800000 ps | ||
| T6 | /workspace/coverage/default/27.prim_present_test.3567657060 | Jul 18 04:30:18 PM PDT 24 | Jul 18 04:31:12 PM PDT 24 | 8535540000 ps | ||
| T7 | /workspace/coverage/default/8.prim_present_test.1132347185 | Jul 18 04:28:54 PM PDT 24 | Jul 18 04:29:58 PM PDT 24 | 9022240000 ps | ||
| T8 | /workspace/coverage/default/10.prim_present_test.2049504560 | Jul 18 04:28:54 PM PDT 24 | Jul 18 04:30:16 PM PDT 24 | 13579860000 ps | ||
| T9 | /workspace/coverage/default/32.prim_present_test.1585823775 | Jul 18 04:30:02 PM PDT 24 | Jul 18 04:31:30 PM PDT 24 | 14366640000 ps | ||
| T10 | /workspace/coverage/default/46.prim_present_test.3332182834 | Jul 18 04:30:16 PM PDT 24 | Jul 18 04:30:47 PM PDT 24 | 4772140000 ps | ||
| T11 | /workspace/coverage/default/34.prim_present_test.457471213 | Jul 18 04:30:06 PM PDT 24 | Jul 18 04:31:44 PM PDT 24 | 11886020000 ps | ||
| T12 | /workspace/coverage/default/7.prim_present_test.118170852 | Jul 18 04:28:52 PM PDT 24 | Jul 18 04:29:22 PM PDT 24 | 4542740000 ps | ||
| T13 | /workspace/coverage/default/48.prim_present_test.3215672748 | Jul 18 04:30:12 PM PDT 24 | Jul 18 04:31:40 PM PDT 24 | 11719240000 ps | ||
| T14 | /workspace/coverage/default/6.prim_present_test.3202112584 | Jul 18 04:28:51 PM PDT 24 | Jul 18 04:29:20 PM PDT 24 | 5679200000 ps | ||
| T15 | /workspace/coverage/default/25.prim_present_test.935399845 | Jul 18 04:30:14 PM PDT 24 | Jul 18 04:31:37 PM PDT 24 | 13269860000 ps | ||
| T16 | /workspace/coverage/default/28.prim_present_test.2858699362 | Jul 18 04:30:31 PM PDT 24 | Jul 18 04:31:42 PM PDT 24 | 13294040000 ps | ||
| T17 | /workspace/coverage/default/47.prim_present_test.15000524 | Jul 18 04:30:43 PM PDT 24 | Jul 18 04:31:56 PM PDT 24 | 11678320000 ps | ||
| T18 | /workspace/coverage/default/14.prim_present_test.280433808 | Jul 18 04:30:17 PM PDT 24 | Jul 18 04:31:51 PM PDT 24 | 15200540000 ps | ||
| T19 | /workspace/coverage/default/17.prim_present_test.3790151 | Jul 18 04:30:06 PM PDT 24 | Jul 18 04:31:24 PM PDT 24 | 8954660000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.2268324928 | Jul 18 04:29:45 PM PDT 24 | Jul 18 04:30:42 PM PDT 24 | 7971340000 ps | ||
| T21 | /workspace/coverage/default/35.prim_present_test.3898997594 | Jul 18 04:30:09 PM PDT 24 | Jul 18 04:31:02 PM PDT 24 | 8526240000 ps | ||
| T22 | /workspace/coverage/default/13.prim_present_test.1315319678 | Jul 18 04:30:24 PM PDT 24 | Jul 18 04:31:51 PM PDT 24 | 12381400000 ps | ||
| T23 | /workspace/coverage/default/29.prim_present_test.3769067585 | Jul 18 04:29:59 PM PDT 24 | Jul 18 04:30:58 PM PDT 24 | 8907540000 ps | ||
| T24 | /workspace/coverage/default/20.prim_present_test.1051817877 | Jul 18 04:30:07 PM PDT 24 | Jul 18 04:31:06 PM PDT 24 | 8881500000 ps | ||
| T25 | /workspace/coverage/default/0.prim_present_test.698933409 | Jul 18 04:28:46 PM PDT 24 | Jul 18 04:29:44 PM PDT 24 | 9081760000 ps | ||
| T26 | /workspace/coverage/default/31.prim_present_test.3073962519 | Jul 18 04:30:56 PM PDT 24 | Jul 18 04:32:12 PM PDT 24 | 11231920000 ps | ||
| T27 | /workspace/coverage/default/45.prim_present_test.3470685545 | Jul 18 04:30:12 PM PDT 24 | Jul 18 04:30:46 PM PDT 24 | 4439200000 ps | ||
| T28 | /workspace/coverage/default/18.prim_present_test.1688246976 | Jul 18 04:30:06 PM PDT 24 | Jul 18 04:31:10 PM PDT 24 | 10130800000 ps | ||
| T29 | /workspace/coverage/default/33.prim_present_test.905824252 | Jul 18 04:30:15 PM PDT 24 | Jul 18 04:31:22 PM PDT 24 | 10221940000 ps | ||
| T30 | /workspace/coverage/default/22.prim_present_test.428038258 | Jul 18 04:30:05 PM PDT 24 | Jul 18 04:30:38 PM PDT 24 | 5509320000 ps | ||
| T31 | /workspace/coverage/default/11.prim_present_test.1584297389 | Jul 18 04:28:51 PM PDT 24 | Jul 18 04:29:42 PM PDT 24 | 8877160000 ps | ||
| T32 | /workspace/coverage/default/1.prim_present_test.2193137573 | Jul 18 04:28:46 PM PDT 24 | Jul 18 04:29:31 PM PDT 24 | 6089640000 ps | ||
| T33 | /workspace/coverage/default/30.prim_present_test.4102597730 | Jul 18 04:30:03 PM PDT 24 | Jul 18 04:30:50 PM PDT 24 | 6172100000 ps | ||
| T34 | /workspace/coverage/default/42.prim_present_test.224810473 | Jul 18 04:30:17 PM PDT 24 | Jul 18 04:31:22 PM PDT 24 | 9448180000 ps | ||
| T35 | /workspace/coverage/default/44.prim_present_test.3792568424 | Jul 18 04:30:11 PM PDT 24 | Jul 18 04:31:09 PM PDT 24 | 7885160000 ps | ||
| T36 | /workspace/coverage/default/43.prim_present_test.86347445 | Jul 18 04:30:15 PM PDT 24 | Jul 18 04:30:38 PM PDT 24 | 4058520000 ps | ||
| T37 | /workspace/coverage/default/4.prim_present_test.3856822822 | Jul 18 04:28:45 PM PDT 24 | Jul 18 04:30:10 PM PDT 24 | 14144060000 ps | ||
| T38 | /workspace/coverage/default/24.prim_present_test.2686263848 | Jul 18 04:30:21 PM PDT 24 | Jul 18 04:30:52 PM PDT 24 | 4781440000 ps | ||
| T39 | /workspace/coverage/default/26.prim_present_test.2028408417 | Jul 18 04:30:18 PM PDT 24 | Jul 18 04:30:57 PM PDT 24 | 6849140000 ps | ||
| T40 | /workspace/coverage/default/36.prim_present_test.2978472127 | Jul 18 04:30:06 PM PDT 24 | Jul 18 04:31:27 PM PDT 24 | 9353940000 ps | ||
| T41 | /workspace/coverage/default/21.prim_present_test.298012235 | Jul 18 04:30:02 PM PDT 24 | Jul 18 04:30:27 PM PDT 24 | 3875000000 ps | ||
| T42 | /workspace/coverage/default/9.prim_present_test.694181446 | Jul 18 04:28:52 PM PDT 24 | Jul 18 04:29:17 PM PDT 24 | 3928320000 ps | ||
| T43 | /workspace/coverage/default/49.prim_present_test.1538196642 | Jul 18 04:30:09 PM PDT 24 | Jul 18 04:31:03 PM PDT 24 | 8347060000 ps | ||
| T44 | /workspace/coverage/default/5.prim_present_test.1596475991 | Jul 18 04:28:53 PM PDT 24 | Jul 18 04:30:22 PM PDT 24 | 13827860000 ps | ||
| T45 | /workspace/coverage/default/37.prim_present_test.1447834905 | Jul 18 04:30:05 PM PDT 24 | Jul 18 04:31:20 PM PDT 24 | 12060860000 ps | ||
| T46 | /workspace/coverage/default/40.prim_present_test.2769471833 | Jul 18 04:30:12 PM PDT 24 | Jul 18 04:31:10 PM PDT 24 | 7484640000 ps | ||
| T47 | /workspace/coverage/default/19.prim_present_test.1527497328 | Jul 18 04:30:06 PM PDT 24 | Jul 18 04:31:03 PM PDT 24 | 6410800000 ps | ||
| T48 | /workspace/coverage/default/41.prim_present_test.1663817176 | Jul 18 04:30:06 PM PDT 24 | Jul 18 04:31:04 PM PDT 24 | 6456060000 ps | ||
| T49 | /workspace/coverage/default/23.prim_present_test.3437202636 | Jul 18 04:30:12 PM PDT 24 | Jul 18 04:30:50 PM PDT 24 | 5088340000 ps | ||
| T50 | /workspace/coverage/default/39.prim_present_test.559656570 | Jul 18 04:30:03 PM PDT 24 | Jul 18 04:31:10 PM PDT 24 | 8919320000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.2049504560 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13579860000 ps |
| CPU time | 44.04 seconds |
| Started | Jul 18 04:28:54 PM PDT 24 |
| Finished | Jul 18 04:30:16 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-de5b4fb2-22e4-4312-bf4a-5177cddbc701 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049504560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2049504560 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.698933409 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9081760000 ps |
| CPU time | 30.48 seconds |
| Started | Jul 18 04:28:46 PM PDT 24 |
| Finished | Jul 18 04:29:44 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-bc3bc46c-5751-4f5f-b640-1a235a177692 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698933409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.698933409 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2193137573 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6089640000 ps |
| CPU time | 23.09 seconds |
| Started | Jul 18 04:28:46 PM PDT 24 |
| Finished | Jul 18 04:29:31 PM PDT 24 |
| Peak memory | 144548 kb |
| Host | smart-4881ae98-d14e-45ec-ad62-cc4bbd7ee323 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193137573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2193137573 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1584297389 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8877160000 ps |
| CPU time | 27.25 seconds |
| Started | Jul 18 04:28:51 PM PDT 24 |
| Finished | Jul 18 04:29:42 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-bf4d55ae-3cf9-4801-830a-077bc2133f64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584297389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1584297389 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2268324928 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7971340000 ps |
| CPU time | 29.15 seconds |
| Started | Jul 18 04:29:45 PM PDT 24 |
| Finished | Jul 18 04:30:42 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-df5d69d9-3402-464d-9c0e-4b3f8c71c656 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268324928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2268324928 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1315319678 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12381400000 ps |
| CPU time | 45.96 seconds |
| Started | Jul 18 04:30:24 PM PDT 24 |
| Finished | Jul 18 04:31:51 PM PDT 24 |
| Peak memory | 144612 kb |
| Host | smart-48aba940-dc3a-40fa-af9d-875af0aa895c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315319678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1315319678 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.280433808 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15200540000 ps |
| CPU time | 49.17 seconds |
| Started | Jul 18 04:30:17 PM PDT 24 |
| Finished | Jul 18 04:31:51 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-a6914551-e0a5-4dfd-9870-b0e7f717cc04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280433808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.280433808 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2270550197 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13687120000 ps |
| CPU time | 50.92 seconds |
| Started | Jul 18 04:30:23 PM PDT 24 |
| Finished | Jul 18 04:32:02 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-53566e3c-8911-463d-bb88-ad49197f3d44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270550197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2270550197 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2776010233 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12734800000 ps |
| CPU time | 40.3 seconds |
| Started | Jul 18 04:30:11 PM PDT 24 |
| Finished | Jul 18 04:31:32 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-083dacd7-f495-46bf-9745-a1f84c350e30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776010233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2776010233 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3790151 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8954660000 ps |
| CPU time | 38.14 seconds |
| Started | Jul 18 04:30:06 PM PDT 24 |
| Finished | Jul 18 04:31:24 PM PDT 24 |
| Peak memory | 142524 kb |
| Host | smart-6d5a1ac2-5a92-4889-94be-a13284dc791e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3790151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3790151 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1688246976 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10130800000 ps |
| CPU time | 33.38 seconds |
| Started | Jul 18 04:30:06 PM PDT 24 |
| Finished | Jul 18 04:31:10 PM PDT 24 |
| Peak memory | 144548 kb |
| Host | smart-a8457734-b3e8-4229-8269-8450f80f360c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1688246976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1688246976 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1527497328 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6410800000 ps |
| CPU time | 27.53 seconds |
| Started | Jul 18 04:30:06 PM PDT 24 |
| Finished | Jul 18 04:31:03 PM PDT 24 |
| Peak memory | 142528 kb |
| Host | smart-77a3ebb5-ea55-43a9-b91f-7f8dd84ab1ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527497328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1527497328 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4163891356 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12148900000 ps |
| CPU time | 40.73 seconds |
| Started | Jul 18 04:28:49 PM PDT 24 |
| Finished | Jul 18 04:30:06 PM PDT 24 |
| Peak memory | 144512 kb |
| Host | smart-ebe585a1-4e1c-4046-b49a-e3e50b50d5b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163891356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4163891356 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1051817877 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8881500000 ps |
| CPU time | 30.97 seconds |
| Started | Jul 18 04:30:07 PM PDT 24 |
| Finished | Jul 18 04:31:06 PM PDT 24 |
| Peak memory | 144484 kb |
| Host | smart-271c54d6-93cd-4c80-97cb-8e432428c797 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051817877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1051817877 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.298012235 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3875000000 ps |
| CPU time | 12.6 seconds |
| Started | Jul 18 04:30:02 PM PDT 24 |
| Finished | Jul 18 04:30:27 PM PDT 24 |
| Peak memory | 144360 kb |
| Host | smart-d3ad30bc-28b9-4b2a-847d-022342f93210 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=298012235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.298012235 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.428038258 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5509320000 ps |
| CPU time | 17.39 seconds |
| Started | Jul 18 04:30:05 PM PDT 24 |
| Finished | Jul 18 04:30:38 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-7d7792e8-a4db-4df3-933f-ffb1bcc8018b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=428038258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.428038258 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3437202636 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5088340000 ps |
| CPU time | 19.43 seconds |
| Started | Jul 18 04:30:12 PM PDT 24 |
| Finished | Jul 18 04:30:50 PM PDT 24 |
| Peak memory | 144808 kb |
| Host | smart-a08a9d35-86d4-44b7-b77b-c2c04621c32c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437202636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3437202636 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2686263848 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4781440000 ps |
| CPU time | 16.06 seconds |
| Started | Jul 18 04:30:21 PM PDT 24 |
| Finished | Jul 18 04:30:52 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-549db5ca-0b54-4def-9779-f63c05c86458 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686263848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2686263848 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.935399845 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13269860000 ps |
| CPU time | 44.47 seconds |
| Started | Jul 18 04:30:14 PM PDT 24 |
| Finished | Jul 18 04:31:37 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-271f4fc6-9ccc-435b-bddf-c3bf29849a48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935399845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.935399845 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2028408417 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6849140000 ps |
| CPU time | 21.08 seconds |
| Started | Jul 18 04:30:18 PM PDT 24 |
| Finished | Jul 18 04:30:57 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-313928ef-f3cd-481d-88e6-b29994c85166 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028408417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2028408417 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3567657060 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8535540000 ps |
| CPU time | 28.02 seconds |
| Started | Jul 18 04:30:18 PM PDT 24 |
| Finished | Jul 18 04:31:12 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-8bdae448-3b47-4564-ba8c-0b321d688bbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567657060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3567657060 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2858699362 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13294040000 ps |
| CPU time | 38.03 seconds |
| Started | Jul 18 04:30:31 PM PDT 24 |
| Finished | Jul 18 04:31:42 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-b8a6c3e9-0491-41cc-8cbf-251c523153b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858699362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2858699362 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3769067585 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8907540000 ps |
| CPU time | 30.4 seconds |
| Started | Jul 18 04:29:59 PM PDT 24 |
| Finished | Jul 18 04:30:58 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-89de8d4e-5a6e-4f78-8c3f-8ed4ba3144ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769067585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3769067585 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1023857671 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13611480000 ps |
| CPU time | 48.82 seconds |
| Started | Jul 18 04:28:53 PM PDT 24 |
| Finished | Jul 18 04:30:27 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-2690ebaa-53f9-4795-a567-4272002b2495 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023857671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1023857671 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4102597730 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6172100000 ps |
| CPU time | 25.25 seconds |
| Started | Jul 18 04:30:03 PM PDT 24 |
| Finished | Jul 18 04:30:50 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-0838193c-b72f-41e3-acce-82163976949c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102597730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4102597730 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3073962519 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11231920000 ps |
| CPU time | 40.04 seconds |
| Started | Jul 18 04:30:56 PM PDT 24 |
| Finished | Jul 18 04:32:12 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-56c291ce-5296-48a2-b6d5-7a86db990920 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073962519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3073962519 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1585823775 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 14366640000 ps |
| CPU time | 46.45 seconds |
| Started | Jul 18 04:30:02 PM PDT 24 |
| Finished | Jul 18 04:31:30 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-f5a26910-0abd-4a04-a151-d0d9ee4fb3df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585823775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1585823775 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.905824252 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10221940000 ps |
| CPU time | 35.06 seconds |
| Started | Jul 18 04:30:15 PM PDT 24 |
| Finished | Jul 18 04:31:22 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-c1790e66-45a7-44c8-8d48-3a9e21cf010a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905824252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.905824252 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.457471213 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11886020000 ps |
| CPU time | 48.94 seconds |
| Started | Jul 18 04:30:06 PM PDT 24 |
| Finished | Jul 18 04:31:44 PM PDT 24 |
| Peak memory | 142596 kb |
| Host | smart-12fe66e3-5d86-4058-84c5-d874fdcacf03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457471213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.457471213 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3898997594 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8526240000 ps |
| CPU time | 27.88 seconds |
| Started | Jul 18 04:30:09 PM PDT 24 |
| Finished | Jul 18 04:31:02 PM PDT 24 |
| Peak memory | 144456 kb |
| Host | smart-264b5c07-9424-4290-9880-18c6e2b64cf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898997594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3898997594 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2978472127 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9353940000 ps |
| CPU time | 39.34 seconds |
| Started | Jul 18 04:30:06 PM PDT 24 |
| Finished | Jul 18 04:31:27 PM PDT 24 |
| Peak memory | 142176 kb |
| Host | smart-2885a23f-6057-490e-8446-78d58fe0318e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978472127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2978472127 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1447834905 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12060860000 ps |
| CPU time | 39.32 seconds |
| Started | Jul 18 04:30:05 PM PDT 24 |
| Finished | Jul 18 04:31:20 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-75c04831-2211-453c-89bc-6a2cff9a5e47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447834905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1447834905 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2782438806 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13200420000 ps |
| CPU time | 39.11 seconds |
| Started | Jul 18 04:30:08 PM PDT 24 |
| Finished | Jul 18 04:31:22 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-5d327326-2ebf-4867-ab7c-2ec2bab04db2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782438806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2782438806 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.559656570 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8919320000 ps |
| CPU time | 35.31 seconds |
| Started | Jul 18 04:30:03 PM PDT 24 |
| Finished | Jul 18 04:31:10 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-cb14e274-f527-49be-8ea8-23404707ce06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559656570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.559656570 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3856822822 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 14144060000 ps |
| CPU time | 44.98 seconds |
| Started | Jul 18 04:28:45 PM PDT 24 |
| Finished | Jul 18 04:30:10 PM PDT 24 |
| Peak memory | 144508 kb |
| Host | smart-5215bc69-a07b-4ee1-93b7-d91dd2746b8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856822822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3856822822 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2769471833 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7484640000 ps |
| CPU time | 29.27 seconds |
| Started | Jul 18 04:30:12 PM PDT 24 |
| Finished | Jul 18 04:31:10 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-401b0af8-eaa2-44d6-bb9d-d3ef752437e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769471833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2769471833 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1663817176 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6456060000 ps |
| CPU time | 27.93 seconds |
| Started | Jul 18 04:30:06 PM PDT 24 |
| Finished | Jul 18 04:31:04 PM PDT 24 |
| Peak memory | 142052 kb |
| Host | smart-c2464c65-7204-4163-9d6a-900fdcbc573c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663817176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1663817176 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.224810473 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9448180000 ps |
| CPU time | 34.29 seconds |
| Started | Jul 18 04:30:17 PM PDT 24 |
| Finished | Jul 18 04:31:22 PM PDT 24 |
| Peak memory | 144476 kb |
| Host | smart-7815fb79-b882-4275-b090-1c858778a4ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=224810473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.224810473 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.86347445 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4058520000 ps |
| CPU time | 12.52 seconds |
| Started | Jul 18 04:30:15 PM PDT 24 |
| Finished | Jul 18 04:30:38 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-665d0436-2c64-4514-9460-24bf6b920dcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86347445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.86347445 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3792568424 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7885160000 ps |
| CPU time | 29.37 seconds |
| Started | Jul 18 04:30:11 PM PDT 24 |
| Finished | Jul 18 04:31:09 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-e7f85bd4-7498-4c7f-b9f4-44a1e374b626 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792568424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3792568424 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3470685545 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4439200000 ps |
| CPU time | 16.97 seconds |
| Started | Jul 18 04:30:12 PM PDT 24 |
| Finished | Jul 18 04:30:46 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-ec9b8523-152c-4163-9de7-f0be81851807 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470685545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3470685545 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3332182834 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4772140000 ps |
| CPU time | 16.32 seconds |
| Started | Jul 18 04:30:16 PM PDT 24 |
| Finished | Jul 18 04:30:47 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-5bc5f5ba-ddf8-4f1d-94af-2c42d4d2947f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332182834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3332182834 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.15000524 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11678320000 ps |
| CPU time | 38.29 seconds |
| Started | Jul 18 04:30:43 PM PDT 24 |
| Finished | Jul 18 04:31:56 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-99aab5bf-039e-4f49-979c-8a1c0d02b60e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15000524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.15000524 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3215672748 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11719240000 ps |
| CPU time | 45.1 seconds |
| Started | Jul 18 04:30:12 PM PDT 24 |
| Finished | Jul 18 04:31:40 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-eb51196f-d4f5-40d7-ae03-5c8e7fe31a6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215672748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3215672748 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1538196642 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8347060000 ps |
| CPU time | 28.06 seconds |
| Started | Jul 18 04:30:09 PM PDT 24 |
| Finished | Jul 18 04:31:03 PM PDT 24 |
| Peak memory | 143992 kb |
| Host | smart-4ef07463-679a-4c0b-ae9f-a2316700533d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538196642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1538196642 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1596475991 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13827860000 ps |
| CPU time | 47.33 seconds |
| Started | Jul 18 04:28:53 PM PDT 24 |
| Finished | Jul 18 04:30:22 PM PDT 24 |
| Peak memory | 144516 kb |
| Host | smart-8add61ef-f4a8-404f-abf6-c27a70b81704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596475991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1596475991 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3202112584 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5679200000 ps |
| CPU time | 15.36 seconds |
| Started | Jul 18 04:28:51 PM PDT 24 |
| Finished | Jul 18 04:29:20 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-f8c7b58f-6bdb-4c91-81f7-7d76a0584f24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202112584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3202112584 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.118170852 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4542740000 ps |
| CPU time | 15.35 seconds |
| Started | Jul 18 04:28:52 PM PDT 24 |
| Finished | Jul 18 04:29:22 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-768ff1e7-5aa2-4182-8b76-9d45921e07f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118170852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.118170852 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1132347185 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9022240000 ps |
| CPU time | 33.23 seconds |
| Started | Jul 18 04:28:54 PM PDT 24 |
| Finished | Jul 18 04:29:58 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-7fbb030b-59be-4bf3-999f-f44a6b82ae6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132347185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1132347185 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.694181446 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3928320000 ps |
| CPU time | 13.28 seconds |
| Started | Jul 18 04:28:52 PM PDT 24 |
| Finished | Jul 18 04:29:17 PM PDT 24 |
| Peak memory | 144400 kb |
| Host | smart-49cc3f71-8c5f-4f94-a9e6-62da6e2346f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694181446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.694181446 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |