| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3969225260 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.1725100908 |
| /workspace/coverage/default/10.prim_present_test.2463531835 |
| /workspace/coverage/default/11.prim_present_test.2898165619 |
| /workspace/coverage/default/12.prim_present_test.1097211500 |
| /workspace/coverage/default/13.prim_present_test.1801696829 |
| /workspace/coverage/default/14.prim_present_test.1492194399 |
| /workspace/coverage/default/15.prim_present_test.3003884351 |
| /workspace/coverage/default/16.prim_present_test.1970757584 |
| /workspace/coverage/default/17.prim_present_test.3588733986 |
| /workspace/coverage/default/18.prim_present_test.2461494029 |
| /workspace/coverage/default/19.prim_present_test.2201774228 |
| /workspace/coverage/default/2.prim_present_test.2028542213 |
| /workspace/coverage/default/20.prim_present_test.1373381278 |
| /workspace/coverage/default/21.prim_present_test.3222332405 |
| /workspace/coverage/default/22.prim_present_test.1494431095 |
| /workspace/coverage/default/23.prim_present_test.2429194675 |
| /workspace/coverage/default/24.prim_present_test.76575276 |
| /workspace/coverage/default/25.prim_present_test.1770094032 |
| /workspace/coverage/default/26.prim_present_test.2399774400 |
| /workspace/coverage/default/27.prim_present_test.3190075891 |
| /workspace/coverage/default/28.prim_present_test.4013664093 |
| /workspace/coverage/default/29.prim_present_test.2920998442 |
| /workspace/coverage/default/3.prim_present_test.3188088504 |
| /workspace/coverage/default/30.prim_present_test.2535302643 |
| /workspace/coverage/default/31.prim_present_test.4176866054 |
| /workspace/coverage/default/32.prim_present_test.2760540681 |
| /workspace/coverage/default/33.prim_present_test.3451139259 |
| /workspace/coverage/default/34.prim_present_test.374309745 |
| /workspace/coverage/default/35.prim_present_test.4288731805 |
| /workspace/coverage/default/36.prim_present_test.3150737948 |
| /workspace/coverage/default/37.prim_present_test.2762958947 |
| /workspace/coverage/default/38.prim_present_test.2836240338 |
| /workspace/coverage/default/39.prim_present_test.3350670050 |
| /workspace/coverage/default/4.prim_present_test.1834850498 |
| /workspace/coverage/default/40.prim_present_test.1489077868 |
| /workspace/coverage/default/41.prim_present_test.3559769083 |
| /workspace/coverage/default/42.prim_present_test.1120621382 |
| /workspace/coverage/default/43.prim_present_test.1045943452 |
| /workspace/coverage/default/44.prim_present_test.1289805270 |
| /workspace/coverage/default/45.prim_present_test.2797801060 |
| /workspace/coverage/default/46.prim_present_test.2447993489 |
| /workspace/coverage/default/47.prim_present_test.3258057213 |
| /workspace/coverage/default/48.prim_present_test.640970231 |
| /workspace/coverage/default/49.prim_present_test.4292294289 |
| /workspace/coverage/default/5.prim_present_test.330513481 |
| /workspace/coverage/default/6.prim_present_test.187650959 |
| /workspace/coverage/default/7.prim_present_test.1640848699 |
| /workspace/coverage/default/8.prim_present_test.1508446508 |
| /workspace/coverage/default/9.prim_present_test.1560150174 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/26.prim_present_test.2399774400 | Jul 19 04:58:26 PM PDT 24 | Jul 19 05:00:02 PM PDT 24 | 14412520000 ps | ||
| T2 | /workspace/coverage/default/43.prim_present_test.1045943452 | Jul 19 04:58:28 PM PDT 24 | Jul 19 04:59:59 PM PDT 24 | 12074500000 ps | ||
| T3 | /workspace/coverage/default/30.prim_present_test.2535302643 | Jul 19 04:58:28 PM PDT 24 | Jul 19 04:59:08 PM PDT 24 | 5578760000 ps | ||
| T4 | /workspace/coverage/default/0.prim_present_test.3969225260 | Jul 19 04:58:10 PM PDT 24 | Jul 19 04:59:44 PM PDT 24 | 12917080000 ps | ||
| T5 | /workspace/coverage/default/24.prim_present_test.76575276 | Jul 19 04:58:27 PM PDT 24 | Jul 19 04:59:45 PM PDT 24 | 12858180000 ps | ||
| T6 | /workspace/coverage/default/18.prim_present_test.2461494029 | Jul 19 04:58:19 PM PDT 24 | Jul 19 04:59:23 PM PDT 24 | 9260320000 ps | ||
| T7 | /workspace/coverage/default/39.prim_present_test.3350670050 | Jul 19 04:58:26 PM PDT 24 | Jul 19 05:00:13 PM PDT 24 | 15115600000 ps | ||
| T8 | /workspace/coverage/default/19.prim_present_test.2201774228 | Jul 19 04:58:19 PM PDT 24 | Jul 19 04:59:39 PM PDT 24 | 10613160000 ps | ||
| T9 | /workspace/coverage/default/36.prim_present_test.3150737948 | Jul 19 04:58:27 PM PDT 24 | Jul 19 04:59:42 PM PDT 24 | 10742740000 ps | ||
| T10 | /workspace/coverage/default/22.prim_present_test.1494431095 | Jul 19 04:58:17 PM PDT 24 | Jul 19 04:59:13 PM PDT 24 | 6457920000 ps | ||
| T11 | /workspace/coverage/default/46.prim_present_test.2447993489 | Jul 19 04:58:34 PM PDT 24 | Jul 19 05:00:23 PM PDT 24 | 15051740000 ps | ||
| T12 | /workspace/coverage/default/41.prim_present_test.3559769083 | Jul 19 04:58:27 PM PDT 24 | Jul 19 04:59:05 PM PDT 24 | 5603560000 ps | ||
| T13 | /workspace/coverage/default/4.prim_present_test.1834850498 | Jul 19 04:58:10 PM PDT 24 | Jul 19 04:58:56 PM PDT 24 | 5036260000 ps | ||
| T14 | /workspace/coverage/default/11.prim_present_test.2898165619 | Jul 19 04:58:16 PM PDT 24 | Jul 19 04:59:47 PM PDT 24 | 13090680000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.187650959 | Jul 19 04:58:11 PM PDT 24 | Jul 19 05:00:11 PM PDT 24 | 15061660000 ps | ||
| T16 | /workspace/coverage/default/38.prim_present_test.2836240338 | Jul 19 04:58:26 PM PDT 24 | Jul 19 04:59:26 PM PDT 24 | 7074200000 ps | ||
| T17 | /workspace/coverage/default/40.prim_present_test.1489077868 | Jul 19 04:58:27 PM PDT 24 | Jul 19 04:58:55 PM PDT 24 | 3431080000 ps | ||
| T18 | /workspace/coverage/default/37.prim_present_test.2762958947 | Jul 19 04:58:28 PM PDT 24 | Jul 19 04:59:19 PM PDT 24 | 8089140000 ps | ||
| T19 | /workspace/coverage/default/28.prim_present_test.4013664093 | Jul 19 04:58:27 PM PDT 24 | Jul 19 04:58:59 PM PDT 24 | 4102540000 ps | ||
| T20 | /workspace/coverage/default/1.prim_present_test.1725100908 | Jul 19 04:58:09 PM PDT 24 | Jul 19 04:59:09 PM PDT 24 | 8617380000 ps | ||
| T21 | /workspace/coverage/default/47.prim_present_test.3258057213 | Jul 19 04:58:34 PM PDT 24 | Jul 19 05:00:28 PM PDT 24 | 14351760000 ps | ||
| T22 | /workspace/coverage/default/13.prim_present_test.1801696829 | Jul 19 04:58:18 PM PDT 24 | Jul 19 04:58:54 PM PDT 24 | 4688440000 ps | ||
| T23 | /workspace/coverage/default/25.prim_present_test.1770094032 | Jul 19 04:58:26 PM PDT 24 | Jul 19 04:59:11 PM PDT 24 | 6369260000 ps | ||
| T24 | /workspace/coverage/default/15.prim_present_test.3003884351 | Jul 19 04:58:16 PM PDT 24 | Jul 19 04:59:08 PM PDT 24 | 10280840000 ps | ||
| T25 | /workspace/coverage/default/7.prim_present_test.1640848699 | Jul 19 04:58:17 PM PDT 24 | Jul 19 04:59:58 PM PDT 24 | 14364780000 ps | ||
| T26 | /workspace/coverage/default/20.prim_present_test.1373381278 | Jul 19 04:58:17 PM PDT 24 | Jul 19 04:59:40 PM PDT 24 | 14302160000 ps | ||
| T27 | /workspace/coverage/default/17.prim_present_test.3588733986 | Jul 19 04:58:18 PM PDT 24 | Jul 19 04:58:55 PM PDT 24 | 4746100000 ps | ||
| T28 | /workspace/coverage/default/27.prim_present_test.3190075891 | Jul 19 04:58:29 PM PDT 24 | Jul 19 05:00:34 PM PDT 24 | 14797540000 ps | ||
| T29 | /workspace/coverage/default/3.prim_present_test.3188088504 | Jul 19 04:58:09 PM PDT 24 | Jul 19 04:59:11 PM PDT 24 | 8343960000 ps | ||
| T30 | /workspace/coverage/default/42.prim_present_test.1120621382 | Jul 19 04:58:26 PM PDT 24 | Jul 19 04:59:14 PM PDT 24 | 6496360000 ps | ||
| T31 | /workspace/coverage/default/34.prim_present_test.374309745 | Jul 19 04:58:26 PM PDT 24 | Jul 19 05:00:11 PM PDT 24 | 14429260000 ps | ||
| T32 | /workspace/coverage/default/16.prim_present_test.1970757584 | Jul 19 04:58:17 PM PDT 24 | Jul 19 04:59:27 PM PDT 24 | 9896440000 ps | ||
| T33 | /workspace/coverage/default/21.prim_present_test.3222332405 | Jul 19 04:58:18 PM PDT 24 | Jul 19 04:59:36 PM PDT 24 | 12171220000 ps | ||
| T34 | /workspace/coverage/default/48.prim_present_test.640970231 | Jul 19 04:58:36 PM PDT 24 | Jul 19 05:00:27 PM PDT 24 | 14878140000 ps | ||
| T35 | /workspace/coverage/default/10.prim_present_test.2463531835 | Jul 19 04:58:18 PM PDT 24 | Jul 19 04:59:52 PM PDT 24 | 13420520000 ps | ||
| T36 | /workspace/coverage/default/35.prim_present_test.4288731805 | Jul 19 04:58:29 PM PDT 24 | Jul 19 04:59:31 PM PDT 24 | 7239740000 ps | ||
| T37 | /workspace/coverage/default/44.prim_present_test.1289805270 | Jul 19 04:58:25 PM PDT 24 | Jul 19 04:59:08 PM PDT 24 | 6133040000 ps | ||
| T38 | /workspace/coverage/default/33.prim_present_test.3451139259 | Jul 19 04:58:26 PM PDT 24 | Jul 19 04:59:27 PM PDT 24 | 8264600000 ps | ||
| T39 | /workspace/coverage/default/32.prim_present_test.2760540681 | Jul 19 04:58:24 PM PDT 24 | Jul 19 05:00:03 PM PDT 24 | 12762700000 ps | ||
| T40 | /workspace/coverage/default/2.prim_present_test.2028542213 | Jul 19 04:58:12 PM PDT 24 | Jul 19 04:59:38 PM PDT 24 | 12030480000 ps | ||
| T41 | /workspace/coverage/default/45.prim_present_test.2797801060 | Jul 19 04:58:34 PM PDT 24 | Jul 19 04:59:43 PM PDT 24 | 8634120000 ps | ||
| T42 | /workspace/coverage/default/31.prim_present_test.4176866054 | Jul 19 04:58:25 PM PDT 24 | Jul 19 04:59:39 PM PDT 24 | 12630020000 ps | ||
| T43 | /workspace/coverage/default/9.prim_present_test.1560150174 | Jul 19 04:58:17 PM PDT 24 | Jul 19 04:59:32 PM PDT 24 | 12694500000 ps | ||
| T44 | /workspace/coverage/default/8.prim_present_test.1508446508 | Jul 19 04:58:18 PM PDT 24 | Jul 19 04:59:33 PM PDT 24 | 10145060000 ps | ||
| T45 | /workspace/coverage/default/12.prim_present_test.1097211500 | Jul 19 04:58:16 PM PDT 24 | Jul 19 04:58:36 PM PDT 24 | 3739840000 ps | ||
| T46 | /workspace/coverage/default/14.prim_present_test.1492194399 | Jul 19 04:58:17 PM PDT 24 | Jul 19 04:59:20 PM PDT 24 | 8210040000 ps | ||
| T47 | /workspace/coverage/default/23.prim_present_test.2429194675 | Jul 19 04:58:16 PM PDT 24 | Jul 19 04:59:03 PM PDT 24 | 7476580000 ps | ||
| T48 | /workspace/coverage/default/29.prim_present_test.2920998442 | Jul 19 04:58:28 PM PDT 24 | Jul 19 04:59:21 PM PDT 24 | 6800160000 ps | ||
| T49 | /workspace/coverage/default/5.prim_present_test.330513481 | Jul 19 04:58:11 PM PDT 24 | Jul 19 04:58:39 PM PDT 24 | 3303360000 ps | ||
| T50 | /workspace/coverage/default/49.prim_present_test.4292294289 | Jul 19 04:58:36 PM PDT 24 | Jul 19 04:59:15 PM PDT 24 | 4897380000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3969225260 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12917080000 ps |
| CPU time | 49.05 seconds |
| Started | Jul 19 04:58:10 PM PDT 24 |
| Finished | Jul 19 04:59:44 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-d924aacb-9028-40a7-b127-ecda27ada57f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969225260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3969225260 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1725100908 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8617380000 ps |
| CPU time | 31.74 seconds |
| Started | Jul 19 04:58:09 PM PDT 24 |
| Finished | Jul 19 04:59:09 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-9955fbd6-88dc-498f-ad11-3c016942ab78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725100908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1725100908 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2463531835 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13420520000 ps |
| CPU time | 50.01 seconds |
| Started | Jul 19 04:58:18 PM PDT 24 |
| Finished | Jul 19 04:59:52 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-d61ab733-a600-4dbc-9dd8-fc40c080a288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463531835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2463531835 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2898165619 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13090680000 ps |
| CPU time | 48.26 seconds |
| Started | Jul 19 04:58:16 PM PDT 24 |
| Finished | Jul 19 04:59:47 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-96bda95d-3d25-4917-9bd4-90d60613874a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898165619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2898165619 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1097211500 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3739840000 ps |
| CPU time | 10.23 seconds |
| Started | Jul 19 04:58:16 PM PDT 24 |
| Finished | Jul 19 04:58:36 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-9678fecf-02dd-4c85-bc9f-f88552a637ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097211500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1097211500 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1801696829 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4688440000 ps |
| CPU time | 18.1 seconds |
| Started | Jul 19 04:58:18 PM PDT 24 |
| Finished | Jul 19 04:58:54 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-98c29745-c554-4b54-8a45-7e6dbf567093 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1801696829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1801696829 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1492194399 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8210040000 ps |
| CPU time | 31.17 seconds |
| Started | Jul 19 04:58:17 PM PDT 24 |
| Finished | Jul 19 04:59:20 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-fbd3c120-178c-45bb-b044-eb587618b54f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492194399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1492194399 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3003884351 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10280840000 ps |
| CPU time | 28.12 seconds |
| Started | Jul 19 04:58:16 PM PDT 24 |
| Finished | Jul 19 04:59:08 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-197dfea3-5de9-40b5-9a58-2f2c2e2137cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003884351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3003884351 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1970757584 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9896440000 ps |
| CPU time | 35.54 seconds |
| Started | Jul 19 04:58:17 PM PDT 24 |
| Finished | Jul 19 04:59:27 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-1a48f3c5-ee50-4106-a22f-983c43c2a291 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970757584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1970757584 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3588733986 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4746100000 ps |
| CPU time | 18.61 seconds |
| Started | Jul 19 04:58:18 PM PDT 24 |
| Finished | Jul 19 04:58:55 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-127ab160-a71a-44a7-8b10-cd0867b385ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588733986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3588733986 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2461494029 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9260320000 ps |
| CPU time | 33.8 seconds |
| Started | Jul 19 04:58:19 PM PDT 24 |
| Finished | Jul 19 04:59:23 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-da7789d8-68e4-46e5-a6e3-ed78c8575c59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461494029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2461494029 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2201774228 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10613160000 ps |
| CPU time | 41.68 seconds |
| Started | Jul 19 04:58:19 PM PDT 24 |
| Finished | Jul 19 04:59:39 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-27bd43f8-9479-4b5b-8b2d-1e07033788d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201774228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2201774228 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2028542213 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12030480000 ps |
| CPU time | 44.49 seconds |
| Started | Jul 19 04:58:12 PM PDT 24 |
| Finished | Jul 19 04:59:38 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a08e9a42-05be-42b2-a926-e2348eaecc23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028542213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2028542213 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1373381278 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14302160000 ps |
| CPU time | 44.45 seconds |
| Started | Jul 19 04:58:17 PM PDT 24 |
| Finished | Jul 19 04:59:40 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-8ed30e24-4d47-4511-a825-1ecab65b0f58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373381278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1373381278 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3222332405 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12171220000 ps |
| CPU time | 41.38 seconds |
| Started | Jul 19 04:58:18 PM PDT 24 |
| Finished | Jul 19 04:59:36 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-0906c618-a77b-4561-868c-8c3d84003198 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222332405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3222332405 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1494431095 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6457920000 ps |
| CPU time | 26.99 seconds |
| Started | Jul 19 04:58:17 PM PDT 24 |
| Finished | Jul 19 04:59:13 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-7b0abb46-fab8-486a-8cd9-225f2a6d101a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494431095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1494431095 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2429194675 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7476580000 ps |
| CPU time | 24.71 seconds |
| Started | Jul 19 04:58:16 PM PDT 24 |
| Finished | Jul 19 04:59:03 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-1fd327d9-3bf6-43ff-b1cb-1004c6777708 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429194675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2429194675 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.76575276 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12858180000 ps |
| CPU time | 41.88 seconds |
| Started | Jul 19 04:58:27 PM PDT 24 |
| Finished | Jul 19 04:59:45 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-017d2321-3d78-4b25-9e1e-330244131337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76575276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.76575276 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1770094032 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6369260000 ps |
| CPU time | 23 seconds |
| Started | Jul 19 04:58:26 PM PDT 24 |
| Finished | Jul 19 04:59:11 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-1f928c8d-304e-4657-913c-4dd9d0771ced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770094032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1770094032 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2399774400 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14412520000 ps |
| CPU time | 50.07 seconds |
| Started | Jul 19 04:58:26 PM PDT 24 |
| Finished | Jul 19 05:00:02 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-faae8289-e228-40bb-a14c-54e6c96673ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399774400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2399774400 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3190075891 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14797540000 ps |
| CPU time | 62.27 seconds |
| Started | Jul 19 04:58:29 PM PDT 24 |
| Finished | Jul 19 05:00:34 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-4e74b2db-fd1f-4e8e-b4ea-8cc936617c22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190075891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3190075891 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.4013664093 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4102540000 ps |
| CPU time | 16.53 seconds |
| Started | Jul 19 04:58:27 PM PDT 24 |
| Finished | Jul 19 04:58:59 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-b900105c-21da-46f8-a43f-4d0eec447e45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013664093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.4013664093 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2920998442 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6800160000 ps |
| CPU time | 26.97 seconds |
| Started | Jul 19 04:58:28 PM PDT 24 |
| Finished | Jul 19 04:59:21 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-d02daddf-29c6-403a-88a0-bb80858533fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2920998442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2920998442 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3188088504 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8343960000 ps |
| CPU time | 31.63 seconds |
| Started | Jul 19 04:58:09 PM PDT 24 |
| Finished | Jul 19 04:59:11 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-b907046a-bea9-4a11-b77f-4bfd24209488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188088504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3188088504 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2535302643 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5578760000 ps |
| CPU time | 20.06 seconds |
| Started | Jul 19 04:58:28 PM PDT 24 |
| Finished | Jul 19 04:59:08 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-81efd58a-becd-444d-b937-d28f98f17db7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535302643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2535302643 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.4176866054 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12630020000 ps |
| CPU time | 39.11 seconds |
| Started | Jul 19 04:58:25 PM PDT 24 |
| Finished | Jul 19 04:59:39 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-29fd84af-d24a-4143-bfad-7fded951af59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4176866054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4176866054 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2760540681 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12762700000 ps |
| CPU time | 52.96 seconds |
| Started | Jul 19 04:58:24 PM PDT 24 |
| Finished | Jul 19 05:00:03 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-df803e9d-786f-4be2-9ec9-a88aa87ab712 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760540681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2760540681 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3451139259 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8264600000 ps |
| CPU time | 31.29 seconds |
| Started | Jul 19 04:58:26 PM PDT 24 |
| Finished | Jul 19 04:59:27 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-1736c2a0-8de6-4feb-a7fa-859a9f77ac39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451139259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3451139259 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.374309745 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14429260000 ps |
| CPU time | 54.93 seconds |
| Started | Jul 19 04:58:26 PM PDT 24 |
| Finished | Jul 19 05:00:11 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-5fa489d5-5adf-4349-a4cf-bad1b01d3eeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=374309745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.374309745 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4288731805 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7239740000 ps |
| CPU time | 30.44 seconds |
| Started | Jul 19 04:58:29 PM PDT 24 |
| Finished | Jul 19 04:59:31 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-dfb6f366-4a6f-4121-8403-32fa31ec5ecc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288731805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4288731805 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3150737948 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10742740000 ps |
| CPU time | 39.1 seconds |
| Started | Jul 19 04:58:27 PM PDT 24 |
| Finished | Jul 19 04:59:42 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-0f56d158-0837-4dd2-ab9c-17e2fd8d90eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150737948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3150737948 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2762958947 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8089140000 ps |
| CPU time | 26.95 seconds |
| Started | Jul 19 04:58:28 PM PDT 24 |
| Finished | Jul 19 04:59:19 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-c94b91df-cc6e-41f3-9b4c-bab9874a8d17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762958947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2762958947 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2836240338 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7074200000 ps |
| CPU time | 30.84 seconds |
| Started | Jul 19 04:58:26 PM PDT 24 |
| Finished | Jul 19 04:59:26 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-ebaf5574-941d-4dda-a2b8-fe5bc71f7718 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836240338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2836240338 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3350670050 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15115600000 ps |
| CPU time | 54.4 seconds |
| Started | Jul 19 04:58:26 PM PDT 24 |
| Finished | Jul 19 05:00:13 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-eb710c0f-8ffd-489b-ad99-e5090651dbd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350670050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3350670050 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1834850498 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5036260000 ps |
| CPU time | 22.03 seconds |
| Started | Jul 19 04:58:10 PM PDT 24 |
| Finished | Jul 19 04:58:56 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-9c515754-56bf-41a3-a2be-74c6fb71a813 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834850498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1834850498 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1489077868 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3431080000 ps |
| CPU time | 13.97 seconds |
| Started | Jul 19 04:58:27 PM PDT 24 |
| Finished | Jul 19 04:58:55 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-668b1c4a-b3ec-4f0e-9b5d-7dc4865c8e76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489077868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1489077868 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3559769083 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5603560000 ps |
| CPU time | 19.56 seconds |
| Started | Jul 19 04:58:27 PM PDT 24 |
| Finished | Jul 19 04:59:05 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-225b1cdc-19d8-4eaf-9d07-41837f603261 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559769083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3559769083 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1120621382 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6496360000 ps |
| CPU time | 24.52 seconds |
| Started | Jul 19 04:58:26 PM PDT 24 |
| Finished | Jul 19 04:59:14 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ab46874f-5cf3-44c5-a8c6-6ab2345d251b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120621382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1120621382 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1045943452 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12074500000 ps |
| CPU time | 46.74 seconds |
| Started | Jul 19 04:58:28 PM PDT 24 |
| Finished | Jul 19 04:59:59 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-e43da04b-21be-4cd3-a2b6-d25760a7bb7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045943452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1045943452 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1289805270 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6133040000 ps |
| CPU time | 22.23 seconds |
| Started | Jul 19 04:58:25 PM PDT 24 |
| Finished | Jul 19 04:59:08 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-81674d25-c48b-43da-b615-26c6af409147 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289805270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1289805270 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2797801060 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8634120000 ps |
| CPU time | 34.85 seconds |
| Started | Jul 19 04:58:34 PM PDT 24 |
| Finished | Jul 19 04:59:43 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-28f5050b-f686-44ae-a0f2-a46cb6846ebe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797801060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2797801060 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2447993489 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 15051740000 ps |
| CPU time | 57.19 seconds |
| Started | Jul 19 04:58:34 PM PDT 24 |
| Finished | Jul 19 05:00:23 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-89137a13-67f0-410a-b0bc-243bd8040362 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447993489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2447993489 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3258057213 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14351760000 ps |
| CPU time | 58.67 seconds |
| Started | Jul 19 04:58:34 PM PDT 24 |
| Finished | Jul 19 05:00:28 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-b5204e18-a13a-45de-9d71-7026eea5686c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3258057213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3258057213 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.640970231 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 14878140000 ps |
| CPU time | 57.94 seconds |
| Started | Jul 19 04:58:36 PM PDT 24 |
| Finished | Jul 19 05:00:27 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-37b28ce0-83c4-4c57-9c5f-8fe32e17cb41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640970231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.640970231 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.4292294289 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4897380000 ps |
| CPU time | 19.37 seconds |
| Started | Jul 19 04:58:36 PM PDT 24 |
| Finished | Jul 19 04:59:15 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-3660174d-c525-4ed6-bf28-5dc48d684c8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292294289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4292294289 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.330513481 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3303360000 ps |
| CPU time | 13.45 seconds |
| Started | Jul 19 04:58:11 PM PDT 24 |
| Finished | Jul 19 04:58:39 PM PDT 24 |
| Peak memory | 144196 kb |
| Host | smart-13dd0b27-e6cf-4ea6-883d-5ebbde843ee3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330513481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.330513481 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.187650959 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15061660000 ps |
| CPU time | 60.68 seconds |
| Started | Jul 19 04:58:11 PM PDT 24 |
| Finished | Jul 19 05:00:11 PM PDT 24 |
| Peak memory | 144360 kb |
| Host | smart-12174d32-2485-454c-9662-df2e372e5860 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187650959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.187650959 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1640848699 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 14364780000 ps |
| CPU time | 53.19 seconds |
| Started | Jul 19 04:58:17 PM PDT 24 |
| Finished | Jul 19 04:59:58 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-411883b3-ede0-43cb-9e2f-c663a95221ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640848699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1640848699 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1508446508 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10145060000 ps |
| CPU time | 38.78 seconds |
| Started | Jul 19 04:58:18 PM PDT 24 |
| Finished | Jul 19 04:59:33 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-314aebe2-bd27-420f-ba6e-7d039cf908b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1508446508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1508446508 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1560150174 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12694500000 ps |
| CPU time | 39.67 seconds |
| Started | Jul 19 04:58:17 PM PDT 24 |
| Finished | Jul 19 04:59:32 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-8d00b0c7-e324-4bfb-bc8f-e877120d1724 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560150174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1560150174 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |