| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.2786732552 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3932180071 |
| /workspace/coverage/default/1.prim_present_test.2562668993 |
| /workspace/coverage/default/10.prim_present_test.963787851 |
| /workspace/coverage/default/12.prim_present_test.1487207320 |
| /workspace/coverage/default/13.prim_present_test.521413439 |
| /workspace/coverage/default/14.prim_present_test.2267335447 |
| /workspace/coverage/default/15.prim_present_test.4264902528 |
| /workspace/coverage/default/16.prim_present_test.2917030074 |
| /workspace/coverage/default/17.prim_present_test.533364964 |
| /workspace/coverage/default/18.prim_present_test.2956381339 |
| /workspace/coverage/default/19.prim_present_test.542075995 |
| /workspace/coverage/default/2.prim_present_test.2605857845 |
| /workspace/coverage/default/20.prim_present_test.2059217508 |
| /workspace/coverage/default/21.prim_present_test.3544365893 |
| /workspace/coverage/default/22.prim_present_test.3365692442 |
| /workspace/coverage/default/23.prim_present_test.3640191721 |
| /workspace/coverage/default/24.prim_present_test.2148879469 |
| /workspace/coverage/default/25.prim_present_test.1716782728 |
| /workspace/coverage/default/26.prim_present_test.916011837 |
| /workspace/coverage/default/27.prim_present_test.3589827636 |
| /workspace/coverage/default/28.prim_present_test.414657746 |
| /workspace/coverage/default/29.prim_present_test.119482111 |
| /workspace/coverage/default/3.prim_present_test.4036587906 |
| /workspace/coverage/default/30.prim_present_test.2182486171 |
| /workspace/coverage/default/31.prim_present_test.2635247888 |
| /workspace/coverage/default/32.prim_present_test.2007452584 |
| /workspace/coverage/default/33.prim_present_test.1428378755 |
| /workspace/coverage/default/34.prim_present_test.4174245383 |
| /workspace/coverage/default/35.prim_present_test.2512141998 |
| /workspace/coverage/default/36.prim_present_test.4177946310 |
| /workspace/coverage/default/37.prim_present_test.1652128073 |
| /workspace/coverage/default/38.prim_present_test.695524978 |
| /workspace/coverage/default/39.prim_present_test.3932954744 |
| /workspace/coverage/default/4.prim_present_test.169030442 |
| /workspace/coverage/default/40.prim_present_test.718627499 |
| /workspace/coverage/default/41.prim_present_test.1060387630 |
| /workspace/coverage/default/42.prim_present_test.213791010 |
| /workspace/coverage/default/43.prim_present_test.3780373615 |
| /workspace/coverage/default/44.prim_present_test.121088473 |
| /workspace/coverage/default/45.prim_present_test.3588054514 |
| /workspace/coverage/default/46.prim_present_test.2742679281 |
| /workspace/coverage/default/47.prim_present_test.1824009080 |
| /workspace/coverage/default/48.prim_present_test.2761739746 |
| /workspace/coverage/default/49.prim_present_test.1939367270 |
| /workspace/coverage/default/5.prim_present_test.3699165130 |
| /workspace/coverage/default/6.prim_present_test.2803682290 |
| /workspace/coverage/default/7.prim_present_test.2723226476 |
| /workspace/coverage/default/8.prim_present_test.3691091164 |
| /workspace/coverage/default/9.prim_present_test.4004584129 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/24.prim_present_test.2148879469 | Jul 20 04:24:30 PM PDT 24 | Jul 20 04:25:19 PM PDT 24 | 7219280000 ps | ||
| T2 | /workspace/coverage/default/11.prim_present_test.2786732552 | Jul 20 04:22:12 PM PDT 24 | Jul 20 04:22:50 PM PDT 24 | 5940840000 ps | ||
| T3 | /workspace/coverage/default/46.prim_present_test.2742679281 | Jul 20 04:23:00 PM PDT 24 | Jul 20 04:23:41 PM PDT 24 | 6607960000 ps | ||
| T4 | /workspace/coverage/default/37.prim_present_test.1652128073 | Jul 20 04:23:53 PM PDT 24 | Jul 20 04:24:59 PM PDT 24 | 8882120000 ps | ||
| T5 | /workspace/coverage/default/5.prim_present_test.3699165130 | Jul 20 04:21:26 PM PDT 24 | Jul 20 04:23:15 PM PDT 24 | 14811180000 ps | ||
| T6 | /workspace/coverage/default/38.prim_present_test.695524978 | Jul 20 04:19:51 PM PDT 24 | Jul 20 04:21:26 PM PDT 24 | 15225340000 ps | ||
| T7 | /workspace/coverage/default/41.prim_present_test.1060387630 | Jul 20 04:23:39 PM PDT 24 | Jul 20 04:24:01 PM PDT 24 | 4301560000 ps | ||
| T8 | /workspace/coverage/default/49.prim_present_test.1939367270 | Jul 20 04:24:22 PM PDT 24 | Jul 20 04:25:43 PM PDT 24 | 13957440000 ps | ||
| T9 | /workspace/coverage/default/45.prim_present_test.3588054514 | Jul 20 04:22:37 PM PDT 24 | Jul 20 04:23:11 PM PDT 24 | 4808720000 ps | ||
| T10 | /workspace/coverage/default/33.prim_present_test.1428378755 | Jul 20 04:23:57 PM PDT 24 | Jul 20 04:25:11 PM PDT 24 | 10817760000 ps | ||
| T11 | /workspace/coverage/default/27.prim_present_test.3589827636 | Jul 20 04:19:11 PM PDT 24 | Jul 20 04:20:43 PM PDT 24 | 13029920000 ps | ||
| T12 | /workspace/coverage/default/16.prim_present_test.2917030074 | Jul 20 04:23:53 PM PDT 24 | Jul 20 04:24:28 PM PDT 24 | 4869480000 ps | ||
| T13 | /workspace/coverage/default/3.prim_present_test.4036587906 | Jul 20 04:24:44 PM PDT 24 | Jul 20 04:25:50 PM PDT 24 | 10481720000 ps | ||
| T14 | /workspace/coverage/default/2.prim_present_test.2605857845 | Jul 20 04:20:05 PM PDT 24 | Jul 20 04:21:31 PM PDT 24 | 11406140000 ps | ||
| T15 | /workspace/coverage/default/15.prim_present_test.4264902528 | Jul 20 04:20:46 PM PDT 24 | Jul 20 04:22:33 PM PDT 24 | 14268060000 ps | ||
| T16 | /workspace/coverage/default/30.prim_present_test.2182486171 | Jul 20 04:23:38 PM PDT 24 | Jul 20 04:25:13 PM PDT 24 | 14373460000 ps | ||
| T17 | /workspace/coverage/default/34.prim_present_test.4174245383 | Jul 20 04:23:53 PM PDT 24 | Jul 20 04:25:02 PM PDT 24 | 9123300000 ps | ||
| T18 | /workspace/coverage/default/31.prim_present_test.2635247888 | Jul 20 04:19:58 PM PDT 24 | Jul 20 04:21:08 PM PDT 24 | 10040900000 ps | ||
| T19 | /workspace/coverage/default/23.prim_present_test.3640191721 | Jul 20 04:24:22 PM PDT 24 | Jul 20 04:25:33 PM PDT 24 | 11545640000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.1487207320 | Jul 20 04:19:48 PM PDT 24 | Jul 20 04:20:32 PM PDT 24 | 6027640000 ps | ||
| T21 | /workspace/coverage/default/26.prim_present_test.916011837 | Jul 20 04:24:29 PM PDT 24 | Jul 20 04:24:56 PM PDT 24 | 3876240000 ps | ||
| T22 | /workspace/coverage/default/0.prim_present_test.3932180071 | Jul 20 04:22:00 PM PDT 24 | Jul 20 04:23:01 PM PDT 24 | 8378060000 ps | ||
| T23 | /workspace/coverage/default/32.prim_present_test.2007452584 | Jul 20 04:23:25 PM PDT 24 | Jul 20 04:23:46 PM PDT 24 | 3770220000 ps | ||
| T24 | /workspace/coverage/default/48.prim_present_test.2761739746 | Jul 20 04:24:21 PM PDT 24 | Jul 20 04:25:27 PM PDT 24 | 10575960000 ps | ||
| T25 | /workspace/coverage/default/39.prim_present_test.3932954744 | Jul 20 04:19:55 PM PDT 24 | Jul 20 04:20:46 PM PDT 24 | 7161620000 ps | ||
| T26 | /workspace/coverage/default/10.prim_present_test.963787851 | Jul 20 04:24:11 PM PDT 24 | Jul 20 04:24:51 PM PDT 24 | 7486500000 ps | ||
| T27 | /workspace/coverage/default/40.prim_present_test.718627499 | Jul 20 04:23:53 PM PDT 24 | Jul 20 04:24:24 PM PDT 24 | 3986600000 ps | ||
| T28 | /workspace/coverage/default/25.prim_present_test.1716782728 | Jul 20 04:21:41 PM PDT 24 | Jul 20 04:22:18 PM PDT 24 | 5135460000 ps | ||
| T29 | /workspace/coverage/default/29.prim_present_test.119482111 | Jul 20 04:23:37 PM PDT 24 | Jul 20 04:24:30 PM PDT 24 | 7690480000 ps | ||
| T30 | /workspace/coverage/default/20.prim_present_test.2059217508 | Jul 20 04:24:21 PM PDT 24 | Jul 20 04:24:55 PM PDT 24 | 5598600000 ps | ||
| T31 | /workspace/coverage/default/21.prim_present_test.3544365893 | Jul 20 04:20:38 PM PDT 24 | Jul 20 04:21:21 PM PDT 24 | 6436220000 ps | ||
| T32 | /workspace/coverage/default/35.prim_present_test.2512141998 | Jul 20 04:23:53 PM PDT 24 | Jul 20 04:25:26 PM PDT 24 | 12856320000 ps | ||
| T33 | /workspace/coverage/default/43.prim_present_test.3780373615 | Jul 20 04:20:32 PM PDT 24 | Jul 20 04:21:57 PM PDT 24 | 12670940000 ps | ||
| T34 | /workspace/coverage/default/18.prim_present_test.2956381339 | Jul 20 04:23:31 PM PDT 24 | Jul 20 04:24:21 PM PDT 24 | 9604420000 ps | ||
| T35 | /workspace/coverage/default/22.prim_present_test.3365692442 | Jul 20 04:23:37 PM PDT 24 | Jul 20 04:24:51 PM PDT 24 | 12373340000 ps | ||
| T36 | /workspace/coverage/default/42.prim_present_test.213791010 | Jul 20 04:24:38 PM PDT 24 | Jul 20 04:25:07 PM PDT 24 | 5289840000 ps | ||
| T37 | /workspace/coverage/default/7.prim_present_test.2723226476 | Jul 20 04:24:56 PM PDT 24 | Jul 20 04:25:30 PM PDT 24 | 5575040000 ps | ||
| T38 | /workspace/coverage/default/1.prim_present_test.2562668993 | Jul 20 04:24:39 PM PDT 24 | Jul 20 04:26:05 PM PDT 24 | 13929540000 ps | ||
| T39 | /workspace/coverage/default/13.prim_present_test.521413439 | Jul 20 04:24:33 PM PDT 24 | Jul 20 04:25:51 PM PDT 24 | 13134700000 ps | ||
| T40 | /workspace/coverage/default/8.prim_present_test.3691091164 | Jul 20 04:19:48 PM PDT 24 | Jul 20 04:20:25 PM PDT 24 | 5695320000 ps | ||
| T41 | /workspace/coverage/default/28.prim_present_test.414657746 | Jul 20 04:23:46 PM PDT 24 | Jul 20 04:25:10 PM PDT 24 | 13085720000 ps | ||
| T42 | /workspace/coverage/default/47.prim_present_test.1824009080 | Jul 20 04:24:38 PM PDT 24 | Jul 20 04:26:06 PM PDT 24 | 14400120000 ps | ||
| T43 | /workspace/coverage/default/44.prim_present_test.121088473 | Jul 20 04:21:24 PM PDT 24 | Jul 20 04:23:08 PM PDT 24 | 14288520000 ps | ||
| T44 | /workspace/coverage/default/14.prim_present_test.2267335447 | Jul 20 04:24:33 PM PDT 24 | Jul 20 04:25:25 PM PDT 24 | 8340240000 ps | ||
| T45 | /workspace/coverage/default/4.prim_present_test.169030442 | Jul 20 04:24:56 PM PDT 24 | Jul 20 04:26:24 PM PDT 24 | 14829160000 ps | ||
| T46 | /workspace/coverage/default/6.prim_present_test.2803682290 | Jul 20 04:21:06 PM PDT 24 | Jul 20 04:22:28 PM PDT 24 | 14129800000 ps | ||
| T47 | /workspace/coverage/default/17.prim_present_test.533364964 | Jul 20 04:20:02 PM PDT 24 | Jul 20 04:21:28 PM PDT 24 | 11627480000 ps | ||
| T48 | /workspace/coverage/default/19.prim_present_test.542075995 | Jul 20 04:23:35 PM PDT 24 | Jul 20 04:24:27 PM PDT 24 | 9551720000 ps | ||
| T49 | /workspace/coverage/default/36.prim_present_test.4177946310 | Jul 20 04:20:33 PM PDT 24 | Jul 20 04:21:15 PM PDT 24 | 5687260000 ps | ||
| T50 | /workspace/coverage/default/9.prim_present_test.4004584129 | Jul 20 04:24:10 PM PDT 24 | Jul 20 04:25:21 PM PDT 24 | 11816580000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.2786732552 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5940840000 ps |
| CPU time | 20.68 seconds |
| Started | Jul 20 04:22:12 PM PDT 24 |
| Finished | Jul 20 04:22:50 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-20100e5d-2843-4dcb-9fb3-5aaebb958f86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786732552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2786732552 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3932180071 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8378060000 ps |
| CPU time | 32.15 seconds |
| Started | Jul 20 04:22:00 PM PDT 24 |
| Finished | Jul 20 04:23:01 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-3242cdb2-0cdb-48d7-bfa1-bdb3ec98f6a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932180071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3932180071 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2562668993 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13929540000 ps |
| CPU time | 46.26 seconds |
| Started | Jul 20 04:24:39 PM PDT 24 |
| Finished | Jul 20 04:26:05 PM PDT 24 |
| Peak memory | 144544 kb |
| Host | smart-389a92be-4ebc-4f78-b169-f1a68bf79e91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562668993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2562668993 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.963787851 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7486500000 ps |
| CPU time | 21.41 seconds |
| Started | Jul 20 04:24:11 PM PDT 24 |
| Finished | Jul 20 04:24:51 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-d610652d-56eb-4ee0-9bfc-10094c14fb8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963787851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.963787851 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1487207320 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6027640000 ps |
| CPU time | 23.19 seconds |
| Started | Jul 20 04:19:48 PM PDT 24 |
| Finished | Jul 20 04:20:32 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-dba07a24-81dd-4b87-8de1-3a83f9400520 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487207320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1487207320 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.521413439 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13134700000 ps |
| CPU time | 41.8 seconds |
| Started | Jul 20 04:24:33 PM PDT 24 |
| Finished | Jul 20 04:25:51 PM PDT 24 |
| Peak memory | 143568 kb |
| Host | smart-cdbd621f-278b-4682-9d43-2d3debc3c2b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=521413439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.521413439 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2267335447 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8340240000 ps |
| CPU time | 27.56 seconds |
| Started | Jul 20 04:24:33 PM PDT 24 |
| Finished | Jul 20 04:25:25 PM PDT 24 |
| Peak memory | 143512 kb |
| Host | smart-1e1a03e1-d38a-435a-869d-f77bf7a15088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267335447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2267335447 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.4264902528 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 14268060000 ps |
| CPU time | 56.05 seconds |
| Started | Jul 20 04:20:46 PM PDT 24 |
| Finished | Jul 20 04:22:33 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-74145908-70d0-4786-8026-b31794072e05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264902528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4264902528 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2917030074 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4869480000 ps |
| CPU time | 18.79 seconds |
| Started | Jul 20 04:23:53 PM PDT 24 |
| Finished | Jul 20 04:24:28 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-422ad630-7d87-4f0c-a247-228622031761 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917030074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2917030074 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.533364964 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11627480000 ps |
| CPU time | 45.38 seconds |
| Started | Jul 20 04:20:02 PM PDT 24 |
| Finished | Jul 20 04:21:28 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-d4e762b6-61cb-4a89-992e-8344f3b27cf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=533364964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.533364964 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2956381339 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9604420000 ps |
| CPU time | 27.01 seconds |
| Started | Jul 20 04:23:31 PM PDT 24 |
| Finished | Jul 20 04:24:21 PM PDT 24 |
| Peak memory | 143700 kb |
| Host | smart-6aaa15b9-6e53-4f66-802a-dd80f5818488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956381339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2956381339 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.542075995 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9551720000 ps |
| CPU time | 28.81 seconds |
| Started | Jul 20 04:23:35 PM PDT 24 |
| Finished | Jul 20 04:24:27 PM PDT 24 |
| Peak memory | 143776 kb |
| Host | smart-ead2d245-a6cf-4894-b01b-348723c58934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542075995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.542075995 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2605857845 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11406140000 ps |
| CPU time | 45.37 seconds |
| Started | Jul 20 04:20:05 PM PDT 24 |
| Finished | Jul 20 04:21:31 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-34030d59-727b-49a0-b7ae-db8e705e0160 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605857845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2605857845 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2059217508 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5598600000 ps |
| CPU time | 18.73 seconds |
| Started | Jul 20 04:24:21 PM PDT 24 |
| Finished | Jul 20 04:24:55 PM PDT 24 |
| Peak memory | 144544 kb |
| Host | smart-90b6c775-0a3e-4877-b39a-ca0eec3f36e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059217508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2059217508 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3544365893 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6436220000 ps |
| CPU time | 23.04 seconds |
| Started | Jul 20 04:20:38 PM PDT 24 |
| Finished | Jul 20 04:21:21 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-84e458d5-145e-440e-9dfe-9ea8159d60ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544365893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3544365893 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3365692442 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12373340000 ps |
| CPU time | 39.65 seconds |
| Started | Jul 20 04:23:37 PM PDT 24 |
| Finished | Jul 20 04:24:51 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-8a573d3d-dde0-4570-bcd3-99eeedbc1b34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365692442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3365692442 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3640191721 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11545640000 ps |
| CPU time | 37.88 seconds |
| Started | Jul 20 04:24:22 PM PDT 24 |
| Finished | Jul 20 04:25:33 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-e44b92f2-5818-4299-84a1-f264d731dcd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3640191721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3640191721 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2148879469 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7219280000 ps |
| CPU time | 25.82 seconds |
| Started | Jul 20 04:24:30 PM PDT 24 |
| Finished | Jul 20 04:25:19 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-70dad9f1-9703-4eea-a4ab-c9a86aef9023 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148879469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2148879469 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1716782728 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5135460000 ps |
| CPU time | 19.66 seconds |
| Started | Jul 20 04:21:41 PM PDT 24 |
| Finished | Jul 20 04:22:18 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-d66f0e53-3a0e-4074-b3f1-ba07a2df0f43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716782728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1716782728 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.916011837 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3876240000 ps |
| CPU time | 13.81 seconds |
| Started | Jul 20 04:24:29 PM PDT 24 |
| Finished | Jul 20 04:24:56 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-1e4d2899-9cf8-4f5d-bbf1-5ae48937dd11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916011837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.916011837 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3589827636 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13029920000 ps |
| CPU time | 48.24 seconds |
| Started | Jul 20 04:19:11 PM PDT 24 |
| Finished | Jul 20 04:20:43 PM PDT 24 |
| Peak memory | 143980 kb |
| Host | smart-78f016cf-0cda-458e-868c-fb30dd636c55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589827636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3589827636 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.414657746 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13085720000 ps |
| CPU time | 43.69 seconds |
| Started | Jul 20 04:23:46 PM PDT 24 |
| Finished | Jul 20 04:25:10 PM PDT 24 |
| Peak memory | 143468 kb |
| Host | smart-2f79963a-7f5f-481e-b883-08b2798fa901 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414657746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.414657746 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.119482111 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7690480000 ps |
| CPU time | 28.09 seconds |
| Started | Jul 20 04:23:37 PM PDT 24 |
| Finished | Jul 20 04:24:30 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-a6e89cf1-ee6b-457b-8ffb-c075abfb9758 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119482111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.119482111 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.4036587906 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10481720000 ps |
| CPU time | 34.29 seconds |
| Started | Jul 20 04:24:44 PM PDT 24 |
| Finished | Jul 20 04:25:50 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-53db8848-6e0b-460b-8c0b-a3ed2f3892dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036587906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.4036587906 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2182486171 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 14373460000 ps |
| CPU time | 51.14 seconds |
| Started | Jul 20 04:23:38 PM PDT 24 |
| Finished | Jul 20 04:25:13 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-0c1a13b4-d2a6-42f5-9321-3b0061e58a23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182486171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2182486171 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2635247888 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10040900000 ps |
| CPU time | 37.56 seconds |
| Started | Jul 20 04:19:58 PM PDT 24 |
| Finished | Jul 20 04:21:08 PM PDT 24 |
| Peak memory | 144704 kb |
| Host | smart-a9eaa133-eb3d-4c7d-8188-e388438bb0c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635247888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2635247888 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2007452584 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3770220000 ps |
| CPU time | 11.32 seconds |
| Started | Jul 20 04:23:25 PM PDT 24 |
| Finished | Jul 20 04:23:46 PM PDT 24 |
| Peak memory | 144344 kb |
| Host | smart-bed9d17d-dbd2-45a8-a019-1eb5c7aed00e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007452584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2007452584 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1428378755 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10817760000 ps |
| CPU time | 39.15 seconds |
| Started | Jul 20 04:23:57 PM PDT 24 |
| Finished | Jul 20 04:25:11 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-93667703-2cd4-4aac-823e-5fb40747cd0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1428378755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1428378755 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.4174245383 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9123300000 ps |
| CPU time | 35.86 seconds |
| Started | Jul 20 04:23:53 PM PDT 24 |
| Finished | Jul 20 04:25:02 PM PDT 24 |
| Peak memory | 142060 kb |
| Host | smart-3c7808f9-417d-402b-aa45-18c2c6613760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174245383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.4174245383 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2512141998 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12856320000 ps |
| CPU time | 48.75 seconds |
| Started | Jul 20 04:23:53 PM PDT 24 |
| Finished | Jul 20 04:25:26 PM PDT 24 |
| Peak memory | 141692 kb |
| Host | smart-ea4062b1-d17d-4f98-94ff-6334b271680a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512141998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2512141998 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4177946310 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5687260000 ps |
| CPU time | 22.34 seconds |
| Started | Jul 20 04:20:33 PM PDT 24 |
| Finished | Jul 20 04:21:15 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-be560f06-e964-4204-a3b3-9a9bac292c83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177946310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4177946310 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1652128073 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8882120000 ps |
| CPU time | 33.99 seconds |
| Started | Jul 20 04:23:53 PM PDT 24 |
| Finished | Jul 20 04:24:59 PM PDT 24 |
| Peak memory | 142824 kb |
| Host | smart-77b5d929-cb6a-4f22-aeb2-e9dc68a0c308 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652128073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1652128073 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.695524978 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 15225340000 ps |
| CPU time | 51.71 seconds |
| Started | Jul 20 04:19:51 PM PDT 24 |
| Finished | Jul 20 04:21:26 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-2b03240d-8fab-40fd-9ae1-3c590f3c6e9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695524978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.695524978 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3932954744 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7161620000 ps |
| CPU time | 26.62 seconds |
| Started | Jul 20 04:19:55 PM PDT 24 |
| Finished | Jul 20 04:20:46 PM PDT 24 |
| Peak memory | 143760 kb |
| Host | smart-3fe9dd50-b8a5-4400-adf7-1aeaa507849d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932954744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3932954744 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.169030442 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14829160000 ps |
| CPU time | 46.61 seconds |
| Started | Jul 20 04:24:56 PM PDT 24 |
| Finished | Jul 20 04:26:24 PM PDT 24 |
| Peak memory | 143804 kb |
| Host | smart-3d43d981-80fc-4165-8c12-e31f8f7fec87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=169030442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.169030442 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.718627499 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3986600000 ps |
| CPU time | 16.05 seconds |
| Started | Jul 20 04:23:53 PM PDT 24 |
| Finished | Jul 20 04:24:24 PM PDT 24 |
| Peak memory | 141676 kb |
| Host | smart-05a4ff8e-4b48-492f-b1d4-95a4eddf9ea5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718627499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.718627499 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1060387630 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4301560000 ps |
| CPU time | 11.76 seconds |
| Started | Jul 20 04:23:39 PM PDT 24 |
| Finished | Jul 20 04:24:01 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-30019ec9-c8f5-4635-a0ae-6b8dfb8855b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060387630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1060387630 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.213791010 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5289840000 ps |
| CPU time | 15.49 seconds |
| Started | Jul 20 04:24:38 PM PDT 24 |
| Finished | Jul 20 04:25:07 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-bcad3b39-486a-492e-b9b1-faca5120f362 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213791010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.213791010 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3780373615 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12670940000 ps |
| CPU time | 45.2 seconds |
| Started | Jul 20 04:20:32 PM PDT 24 |
| Finished | Jul 20 04:21:57 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-19231f99-41c5-4346-99d8-599f62b6643b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780373615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3780373615 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.121088473 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14288520000 ps |
| CPU time | 55.3 seconds |
| Started | Jul 20 04:21:24 PM PDT 24 |
| Finished | Jul 20 04:23:08 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-b87ce5ba-985b-4b66-85e3-b4d24668c6e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121088473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.121088473 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3588054514 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4808720000 ps |
| CPU time | 18.14 seconds |
| Started | Jul 20 04:22:37 PM PDT 24 |
| Finished | Jul 20 04:23:11 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-7208a32d-30b5-4d8d-bac4-aff3cd1cfb18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588054514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3588054514 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2742679281 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6607960000 ps |
| CPU time | 22.23 seconds |
| Started | Jul 20 04:23:00 PM PDT 24 |
| Finished | Jul 20 04:23:41 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-cc79a8ea-41a4-4dbd-af50-616b1609d77e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2742679281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2742679281 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1824009080 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14400120000 ps |
| CPU time | 47.06 seconds |
| Started | Jul 20 04:24:38 PM PDT 24 |
| Finished | Jul 20 04:26:06 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-76187bc9-b831-4951-b1d3-98c96ac384d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824009080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1824009080 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2761739746 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10575960000 ps |
| CPU time | 35.33 seconds |
| Started | Jul 20 04:24:21 PM PDT 24 |
| Finished | Jul 20 04:25:27 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-7d4aba4a-4ae6-4802-b93c-4dd29ed8c00d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761739746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2761739746 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1939367270 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13957440000 ps |
| CPU time | 43.6 seconds |
| Started | Jul 20 04:24:22 PM PDT 24 |
| Finished | Jul 20 04:25:43 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-68059c89-d936-42ed-b7ec-41d3be19ea74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939367270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1939367270 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3699165130 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14811180000 ps |
| CPU time | 56.33 seconds |
| Started | Jul 20 04:21:26 PM PDT 24 |
| Finished | Jul 20 04:23:15 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-88dadd3f-4a0e-426b-aa45-d22e16e606d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699165130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3699165130 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2803682290 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14129800000 ps |
| CPU time | 44.66 seconds |
| Started | Jul 20 04:21:06 PM PDT 24 |
| Finished | Jul 20 04:22:28 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-87a7a863-fb56-468b-ac5f-6e36c18090cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803682290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2803682290 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2723226476 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5575040000 ps |
| CPU time | 17.7 seconds |
| Started | Jul 20 04:24:56 PM PDT 24 |
| Finished | Jul 20 04:25:30 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-967a6953-53eb-47f0-91aa-4ff8f53685e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723226476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2723226476 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3691091164 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5695320000 ps |
| CPU time | 19.84 seconds |
| Started | Jul 20 04:19:48 PM PDT 24 |
| Finished | Jul 20 04:20:25 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-6707e4e9-25d4-45a4-8d5a-03ceacf16c4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691091164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3691091164 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.4004584129 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11816580000 ps |
| CPU time | 37.88 seconds |
| Started | Jul 20 04:24:10 PM PDT 24 |
| Finished | Jul 20 04:25:21 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-cb2edb0d-8562-47db-91ea-dc7ab0f45c25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004584129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.4004584129 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |