| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.2947302705 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3129220190 |
| /workspace/coverage/default/10.prim_present_test.2060457639 |
| /workspace/coverage/default/11.prim_present_test.3932789947 |
| /workspace/coverage/default/12.prim_present_test.593829321 |
| /workspace/coverage/default/13.prim_present_test.2478857786 |
| /workspace/coverage/default/14.prim_present_test.695513982 |
| /workspace/coverage/default/15.prim_present_test.307698046 |
| /workspace/coverage/default/16.prim_present_test.242412413 |
| /workspace/coverage/default/17.prim_present_test.2950833571 |
| /workspace/coverage/default/18.prim_present_test.3284203439 |
| /workspace/coverage/default/19.prim_present_test.3704071378 |
| /workspace/coverage/default/2.prim_present_test.357072063 |
| /workspace/coverage/default/20.prim_present_test.2789080044 |
| /workspace/coverage/default/21.prim_present_test.3284103493 |
| /workspace/coverage/default/22.prim_present_test.3423049610 |
| /workspace/coverage/default/23.prim_present_test.4014630430 |
| /workspace/coverage/default/24.prim_present_test.1385434199 |
| /workspace/coverage/default/25.prim_present_test.1879099304 |
| /workspace/coverage/default/26.prim_present_test.4102358164 |
| /workspace/coverage/default/27.prim_present_test.3317550271 |
| /workspace/coverage/default/28.prim_present_test.2132872622 |
| /workspace/coverage/default/29.prim_present_test.2858084211 |
| /workspace/coverage/default/3.prim_present_test.2039784212 |
| /workspace/coverage/default/30.prim_present_test.2789215495 |
| /workspace/coverage/default/31.prim_present_test.4219479881 |
| /workspace/coverage/default/32.prim_present_test.3472919396 |
| /workspace/coverage/default/33.prim_present_test.1879447786 |
| /workspace/coverage/default/34.prim_present_test.4243292121 |
| /workspace/coverage/default/35.prim_present_test.2671852754 |
| /workspace/coverage/default/36.prim_present_test.223840409 |
| /workspace/coverage/default/37.prim_present_test.1731511665 |
| /workspace/coverage/default/38.prim_present_test.4164437171 |
| /workspace/coverage/default/39.prim_present_test.3724258203 |
| /workspace/coverage/default/4.prim_present_test.857333045 |
| /workspace/coverage/default/40.prim_present_test.2628613475 |
| /workspace/coverage/default/41.prim_present_test.4147874937 |
| /workspace/coverage/default/42.prim_present_test.219382790 |
| /workspace/coverage/default/43.prim_present_test.3445039663 |
| /workspace/coverage/default/44.prim_present_test.2201008821 |
| /workspace/coverage/default/45.prim_present_test.4095628215 |
| /workspace/coverage/default/46.prim_present_test.2353843417 |
| /workspace/coverage/default/47.prim_present_test.412543635 |
| /workspace/coverage/default/48.prim_present_test.142884939 |
| /workspace/coverage/default/49.prim_present_test.753419650 |
| /workspace/coverage/default/5.prim_present_test.3710723345 |
| /workspace/coverage/default/6.prim_present_test.2067415510 |
| /workspace/coverage/default/7.prim_present_test.3287420889 |
| /workspace/coverage/default/8.prim_present_test.1621094623 |
| /workspace/coverage/default/9.prim_present_test.1313966396 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/19.prim_present_test.3704071378 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:19:51 PM PDT 24 | 13440980000 ps | ||
| T2 | /workspace/coverage/default/1.prim_present_test.2947302705 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:19:29 PM PDT 24 | 11751480000 ps | ||
| T3 | /workspace/coverage/default/6.prim_present_test.2067415510 | Jul 21 04:18:11 PM PDT 24 | Jul 21 04:18:33 PM PDT 24 | 3567480000 ps | ||
| T4 | /workspace/coverage/default/39.prim_present_test.3724258203 | Jul 21 04:19:07 PM PDT 24 | Jul 21 04:19:29 PM PDT 24 | 3379620000 ps | ||
| T5 | /workspace/coverage/default/47.prim_present_test.412543635 | Jul 21 04:18:09 PM PDT 24 | Jul 21 04:19:09 PM PDT 24 | 8932340000 ps | ||
| T6 | /workspace/coverage/default/31.prim_present_test.4219479881 | Jul 21 04:19:20 PM PDT 24 | Jul 21 04:20:18 PM PDT 24 | 9021000000 ps | ||
| T7 | /workspace/coverage/default/32.prim_present_test.3472919396 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:19:48 PM PDT 24 | 14989120000 ps | ||
| T8 | /workspace/coverage/default/27.prim_present_test.3317550271 | Jul 21 04:18:09 PM PDT 24 | Jul 21 04:19:12 PM PDT 24 | 8438200000 ps | ||
| T9 | /workspace/coverage/default/34.prim_present_test.4243292121 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:19:26 PM PDT 24 | 10172960000 ps | ||
| T10 | /workspace/coverage/default/45.prim_present_test.4095628215 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:19:48 PM PDT 24 | 15147840000 ps | ||
| T11 | /workspace/coverage/default/12.prim_present_test.593829321 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:40 PM PDT 24 | 14087020000 ps | ||
| T12 | /workspace/coverage/default/49.prim_present_test.753419650 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:19:00 PM PDT 24 | 7674980000 ps | ||
| T13 | /workspace/coverage/default/46.prim_present_test.2353843417 | Jul 21 04:19:09 PM PDT 24 | Jul 21 04:20:10 PM PDT 24 | 9151820000 ps | ||
| T14 | /workspace/coverage/default/3.prim_present_test.2039784212 | Jul 21 04:18:00 PM PDT 24 | Jul 21 04:19:34 PM PDT 24 | 13399440000 ps | ||
| T15 | /workspace/coverage/default/11.prim_present_test.3932789947 | Jul 21 04:17:56 PM PDT 24 | Jul 21 04:18:35 PM PDT 24 | 5661840000 ps | ||
| T16 | /workspace/coverage/default/7.prim_present_test.3287420889 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:22 PM PDT 24 | 11479920000 ps | ||
| T17 | /workspace/coverage/default/18.prim_present_test.3284203439 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:18:54 PM PDT 24 | 6371120000 ps | ||
| T18 | /workspace/coverage/default/17.prim_present_test.2950833571 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:18:35 PM PDT 24 | 3667300000 ps | ||
| T19 | /workspace/coverage/default/48.prim_present_test.142884939 | Jul 21 04:19:23 PM PDT 24 | Jul 21 04:21:11 PM PDT 24 | 14187460000 ps | ||
| T20 | /workspace/coverage/default/0.prim_present_test.3129220190 | Jul 21 04:17:46 PM PDT 24 | Jul 21 04:19:16 PM PDT 24 | 13954960000 ps | ||
| T21 | /workspace/coverage/default/2.prim_present_test.357072063 | Jul 21 04:17:51 PM PDT 24 | Jul 21 04:19:00 PM PDT 24 | 9962160000 ps | ||
| T22 | /workspace/coverage/default/8.prim_present_test.1621094623 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:28 PM PDT 24 | 10789240000 ps | ||
| T23 | /workspace/coverage/default/21.prim_present_test.3284103493 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:24 PM PDT 24 | 11634920000 ps | ||
| T24 | /workspace/coverage/default/40.prim_present_test.2628613475 | Jul 21 04:18:09 PM PDT 24 | Jul 21 04:19:38 PM PDT 24 | 13528400000 ps | ||
| T25 | /workspace/coverage/default/23.prim_present_test.4014630430 | Jul 21 04:18:09 PM PDT 24 | Jul 21 04:19:48 PM PDT 24 | 13140900000 ps | ||
| T26 | /workspace/coverage/default/25.prim_present_test.1879099304 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:11 PM PDT 24 | 8890800000 ps | ||
| T27 | /workspace/coverage/default/13.prim_present_test.2478857786 | Jul 21 04:17:59 PM PDT 24 | Jul 21 04:19:14 PM PDT 24 | 10765680000 ps | ||
| T28 | /workspace/coverage/default/16.prim_present_test.242412413 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:18:51 PM PDT 24 | 6024540000 ps | ||
| T29 | /workspace/coverage/default/10.prim_present_test.2060457639 | Jul 21 04:19:16 PM PDT 24 | Jul 21 04:19:57 PM PDT 24 | 6748080000 ps | ||
| T30 | /workspace/coverage/default/36.prim_present_test.223840409 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:50 PM PDT 24 | 14309600000 ps | ||
| T31 | /workspace/coverage/default/41.prim_present_test.4147874937 | Jul 21 04:18:09 PM PDT 24 | Jul 21 04:19:48 PM PDT 24 | 13117340000 ps | ||
| T32 | /workspace/coverage/default/33.prim_present_test.1879447786 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:12 PM PDT 24 | 9614960000 ps | ||
| T33 | /workspace/coverage/default/4.prim_present_test.857333045 | Jul 21 04:17:50 PM PDT 24 | Jul 21 04:19:11 PM PDT 24 | 12249340000 ps | ||
| T34 | /workspace/coverage/default/42.prim_present_test.219382790 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:35 PM PDT 24 | 11465040000 ps | ||
| T35 | /workspace/coverage/default/5.prim_present_test.3710723345 | Jul 21 04:18:11 PM PDT 24 | Jul 21 04:19:02 PM PDT 24 | 8603120000 ps | ||
| T36 | /workspace/coverage/default/43.prim_present_test.3445039663 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:18:57 PM PDT 24 | 7057460000 ps | ||
| T37 | /workspace/coverage/default/20.prim_present_test.2789080044 | Jul 21 04:17:55 PM PDT 24 | Jul 21 04:18:57 PM PDT 24 | 8735180000 ps | ||
| T38 | /workspace/coverage/default/26.prim_present_test.4102358164 | Jul 21 04:19:16 PM PDT 24 | Jul 21 04:20:42 PM PDT 24 | 13738580000 ps | ||
| T39 | /workspace/coverage/default/14.prim_present_test.695513982 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:18:47 PM PDT 24 | 5845980000 ps | ||
| T40 | /workspace/coverage/default/22.prim_present_test.3423049610 | Jul 21 04:19:07 PM PDT 24 | Jul 21 04:19:41 PM PDT 24 | 5382220000 ps | ||
| T41 | /workspace/coverage/default/30.prim_present_test.2789215495 | Jul 21 04:18:00 PM PDT 24 | Jul 21 04:19:10 PM PDT 24 | 10265340000 ps | ||
| T42 | /workspace/coverage/default/28.prim_present_test.2132872622 | Jul 21 04:18:07 PM PDT 24 | Jul 21 04:19:30 PM PDT 24 | 11628100000 ps | ||
| T43 | /workspace/coverage/default/35.prim_present_test.2671852754 | Jul 21 04:19:09 PM PDT 24 | Jul 21 04:19:42 PM PDT 24 | 5042460000 ps | ||
| T44 | /workspace/coverage/default/9.prim_present_test.1313966396 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:18:58 PM PDT 24 | 7347620000 ps | ||
| T45 | /workspace/coverage/default/24.prim_present_test.1385434199 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:19:34 PM PDT 24 | 13651780000 ps | ||
| T46 | /workspace/coverage/default/44.prim_present_test.2201008821 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:19:10 PM PDT 24 | 10479240000 ps | ||
| T47 | /workspace/coverage/default/15.prim_present_test.307698046 | Jul 21 04:18:00 PM PDT 24 | Jul 21 04:18:55 PM PDT 24 | 7705360000 ps | ||
| T48 | /workspace/coverage/default/38.prim_present_test.4164437171 | Jul 21 04:18:00 PM PDT 24 | Jul 21 04:19:23 PM PDT 24 | 12704420000 ps | ||
| T49 | /workspace/coverage/default/37.prim_present_test.1731511665 | Jul 21 04:18:08 PM PDT 24 | Jul 21 04:18:53 PM PDT 24 | 7081020000 ps | ||
| T50 | /workspace/coverage/default/29.prim_present_test.2858084211 | Jul 21 04:17:56 PM PDT 24 | Jul 21 04:19:14 PM PDT 24 | 11574780000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.2947302705 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11751480000 ps |
| CPU time | 42.81 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:19:29 PM PDT 24 |
| Peak memory | 143968 kb |
| Host | smart-a30f6973-8653-4690-a882-bf4943982d79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947302705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2947302705 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3129220190 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13954960000 ps |
| CPU time | 46.75 seconds |
| Started | Jul 21 04:17:46 PM PDT 24 |
| Finished | Jul 21 04:19:16 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-bf9bf897-5997-4404-afce-e8301df46331 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3129220190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3129220190 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2060457639 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6748080000 ps |
| CPU time | 22.43 seconds |
| Started | Jul 21 04:19:16 PM PDT 24 |
| Finished | Jul 21 04:19:57 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-e2cc2f44-0f7a-47e8-b6b0-7b9ee75e1068 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060457639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2060457639 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3932789947 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5661840000 ps |
| CPU time | 20.35 seconds |
| Started | Jul 21 04:17:56 PM PDT 24 |
| Finished | Jul 21 04:18:35 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-e2b8f83f-7964-4494-bd4e-066a103e8656 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932789947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3932789947 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.593829321 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14087020000 ps |
| CPU time | 49.81 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:40 PM PDT 24 |
| Peak memory | 143632 kb |
| Host | smart-fc895230-18fa-45c0-8100-d4ee9c861dfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593829321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.593829321 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2478857786 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10765680000 ps |
| CPU time | 39.59 seconds |
| Started | Jul 21 04:17:59 PM PDT 24 |
| Finished | Jul 21 04:19:14 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-ce5de747-98dc-49cb-bc36-02368f1cc9bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478857786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2478857786 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.695513982 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5845980000 ps |
| CPU time | 20.7 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:18:47 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-94d082df-5d06-4c62-9878-aec6d5c6b40f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695513982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.695513982 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.307698046 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7705360000 ps |
| CPU time | 29.1 seconds |
| Started | Jul 21 04:18:00 PM PDT 24 |
| Finished | Jul 21 04:18:55 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-14f97a74-f505-4bdd-834d-625500ddf6db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307698046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.307698046 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.242412413 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6024540000 ps |
| CPU time | 22.97 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:18:51 PM PDT 24 |
| Peak memory | 143396 kb |
| Host | smart-e5f51711-01a0-4186-9614-b878a17a36ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242412413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.242412413 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2950833571 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3667300000 ps |
| CPU time | 14.42 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:18:35 PM PDT 24 |
| Peak memory | 142692 kb |
| Host | smart-17bba0c7-d545-43e6-8900-4b8d8c88ec4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950833571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2950833571 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3284203439 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6371120000 ps |
| CPU time | 23.97 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:18:54 PM PDT 24 |
| Peak memory | 144500 kb |
| Host | smart-5db796fe-a79d-416c-8c1f-65242108500b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3284203439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3284203439 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3704071378 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13440980000 ps |
| CPU time | 52.89 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:19:51 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-d5c6acc1-b2a2-471f-bd7a-b2424fdc11eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3704071378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3704071378 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.357072063 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9962160000 ps |
| CPU time | 36.63 seconds |
| Started | Jul 21 04:17:51 PM PDT 24 |
| Finished | Jul 21 04:19:00 PM PDT 24 |
| Peak memory | 144640 kb |
| Host | smart-424e3453-cab6-429f-8ebe-5f8b4403666e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357072063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.357072063 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2789080044 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8735180000 ps |
| CPU time | 32.14 seconds |
| Started | Jul 21 04:17:55 PM PDT 24 |
| Finished | Jul 21 04:18:57 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-17a38021-e2b5-4dad-8022-3620b2b3ffb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789080044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2789080044 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3284103493 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11634920000 ps |
| CPU time | 41.11 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:24 PM PDT 24 |
| Peak memory | 144012 kb |
| Host | smart-31a4da2a-842d-4276-a0f1-7ed0de0903cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3284103493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3284103493 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3423049610 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5382220000 ps |
| CPU time | 17.99 seconds |
| Started | Jul 21 04:19:07 PM PDT 24 |
| Finished | Jul 21 04:19:41 PM PDT 24 |
| Peak memory | 143364 kb |
| Host | smart-a72a553e-3375-41ca-99eb-9790330fbd86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423049610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3423049610 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.4014630430 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13140900000 ps |
| CPU time | 51.45 seconds |
| Started | Jul 21 04:18:09 PM PDT 24 |
| Finished | Jul 21 04:19:48 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-7318f510-ed9c-4f52-9bbf-8a58e8fbd92d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014630430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.4014630430 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1385434199 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13651780000 ps |
| CPU time | 46.1 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:19:34 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-1470a3e6-b5be-41ff-83dc-8b2dd2fa9171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385434199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1385434199 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1879099304 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8890800000 ps |
| CPU time | 33.7 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:11 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-d2906efa-44fa-49eb-a3bf-dfa9e1165197 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879099304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1879099304 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.4102358164 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13738580000 ps |
| CPU time | 45.9 seconds |
| Started | Jul 21 04:19:16 PM PDT 24 |
| Finished | Jul 21 04:20:42 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-83ee6f1b-f6a1-42ee-b139-49cda199400d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102358164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.4102358164 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3317550271 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8438200000 ps |
| CPU time | 32.62 seconds |
| Started | Jul 21 04:18:09 PM PDT 24 |
| Finished | Jul 21 04:19:12 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-a37a56a5-3c83-416d-9593-a5225335c4d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317550271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3317550271 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2132872622 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11628100000 ps |
| CPU time | 44.12 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:30 PM PDT 24 |
| Peak memory | 143204 kb |
| Host | smart-11885c10-0e21-4284-bea4-2316cc3e464a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132872622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2132872622 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2858084211 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11574780000 ps |
| CPU time | 41.19 seconds |
| Started | Jul 21 04:17:56 PM PDT 24 |
| Finished | Jul 21 04:19:14 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-13186893-5d46-4cb4-ab77-52c86f32eb93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858084211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2858084211 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2039784212 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13399440000 ps |
| CPU time | 49.97 seconds |
| Started | Jul 21 04:18:00 PM PDT 24 |
| Finished | Jul 21 04:19:34 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-cc2ac9be-fd00-4801-86d2-b6005ff33a57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039784212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2039784212 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2789215495 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10265340000 ps |
| CPU time | 37 seconds |
| Started | Jul 21 04:18:00 PM PDT 24 |
| Finished | Jul 21 04:19:10 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-3fd4f5d8-ef13-48a3-8c45-6f3ed6cb728d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789215495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2789215495 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.4219479881 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9021000000 ps |
| CPU time | 30.91 seconds |
| Started | Jul 21 04:19:20 PM PDT 24 |
| Finished | Jul 21 04:20:18 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-c17c8d25-bcaf-4c3a-bf97-81854f2fde1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219479881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4219479881 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3472919396 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14989120000 ps |
| CPU time | 52.53 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:19:48 PM PDT 24 |
| Peak memory | 144528 kb |
| Host | smart-bfe0e9af-a8c8-4406-ab42-c7a100e7a005 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472919396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3472919396 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1879447786 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9614960000 ps |
| CPU time | 34.72 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:12 PM PDT 24 |
| Peak memory | 143484 kb |
| Host | smart-20642e45-e1a4-4c9f-9175-c5dec2253ae8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879447786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1879447786 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.4243292121 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10172960000 ps |
| CPU time | 39.94 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:19:26 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-981459ef-3f63-43d9-8ab3-958f97d5f568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243292121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.4243292121 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2671852754 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5042460000 ps |
| CPU time | 17.34 seconds |
| Started | Jul 21 04:19:09 PM PDT 24 |
| Finished | Jul 21 04:19:42 PM PDT 24 |
| Peak memory | 142712 kb |
| Host | smart-f2b95da7-c18c-4909-9922-203d2b093c92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671852754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2671852754 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.223840409 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14309600000 ps |
| CPU time | 54.2 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:50 PM PDT 24 |
| Peak memory | 143016 kb |
| Host | smart-c5dd9ee1-d8e6-476c-bd18-9090aa5bd774 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223840409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.223840409 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1731511665 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7081020000 ps |
| CPU time | 23.97 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:18:53 PM PDT 24 |
| Peak memory | 143376 kb |
| Host | smart-fa37e658-80dc-4610-ab7f-356b872c753d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731511665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1731511665 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.4164437171 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12704420000 ps |
| CPU time | 44.59 seconds |
| Started | Jul 21 04:18:00 PM PDT 24 |
| Finished | Jul 21 04:19:23 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-3f589987-a708-4898-8d09-9de3b778cacd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164437171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.4164437171 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3724258203 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3379620000 ps |
| CPU time | 11.18 seconds |
| Started | Jul 21 04:19:07 PM PDT 24 |
| Finished | Jul 21 04:19:29 PM PDT 24 |
| Peak memory | 143828 kb |
| Host | smart-86e7b23d-de6d-4407-b1a0-38181e89a54b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724258203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3724258203 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.857333045 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12249340000 ps |
| CPU time | 42.78 seconds |
| Started | Jul 21 04:17:50 PM PDT 24 |
| Finished | Jul 21 04:19:11 PM PDT 24 |
| Peak memory | 144040 kb |
| Host | smart-4b1a375f-9b6a-4d60-b1f2-260b27bb6b3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857333045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.857333045 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2628613475 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 13528400000 ps |
| CPU time | 48.12 seconds |
| Started | Jul 21 04:18:09 PM PDT 24 |
| Finished | Jul 21 04:19:38 PM PDT 24 |
| Peak memory | 144084 kb |
| Host | smart-5e42c899-f838-4230-a067-e30048138215 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628613475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2628613475 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.4147874937 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13117340000 ps |
| CPU time | 51.99 seconds |
| Started | Jul 21 04:18:09 PM PDT 24 |
| Finished | Jul 21 04:19:48 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-e1cc5b18-6ee9-44e6-b5ed-719c5a55e743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147874937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4147874937 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.219382790 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11465040000 ps |
| CPU time | 45.43 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:35 PM PDT 24 |
| Peak memory | 142888 kb |
| Host | smart-3ae82c58-2038-44db-9ca5-7362a9dcc849 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219382790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.219382790 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3445039663 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7057460000 ps |
| CPU time | 25.95 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:18:57 PM PDT 24 |
| Peak memory | 144520 kb |
| Host | smart-0631ee32-a55e-4350-b1e8-8ddc09ac3788 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445039663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3445039663 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2201008821 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10479240000 ps |
| CPU time | 33.38 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:19:10 PM PDT 24 |
| Peak memory | 143436 kb |
| Host | smart-dcc6fe16-33f4-443b-9294-03ce7d655082 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201008821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2201008821 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4095628215 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 15147840000 ps |
| CPU time | 52.85 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:19:48 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-a2ba2003-aa41-4e02-a641-cd1f9f05f53f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095628215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4095628215 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2353843417 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9151820000 ps |
| CPU time | 32.68 seconds |
| Started | Jul 21 04:19:09 PM PDT 24 |
| Finished | Jul 21 04:20:10 PM PDT 24 |
| Peak memory | 142528 kb |
| Host | smart-7a7cf222-71f4-4ccc-8c28-a7f5c0188455 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2353843417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2353843417 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.412543635 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8932340000 ps |
| CPU time | 31.9 seconds |
| Started | Jul 21 04:18:09 PM PDT 24 |
| Finished | Jul 21 04:19:09 PM PDT 24 |
| Peak memory | 144508 kb |
| Host | smart-7b7ae4fe-5793-4490-9a9e-16abb00babc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412543635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.412543635 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.142884939 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14187460000 ps |
| CPU time | 56.4 seconds |
| Started | Jul 21 04:19:23 PM PDT 24 |
| Finished | Jul 21 04:21:11 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-a6f6def6-074f-4bd3-861b-27dd3bd2e88a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142884939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.142884939 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.753419650 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7674980000 ps |
| CPU time | 27.45 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:19:00 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-4b06b4d9-c83a-4b10-9cd8-82dbf1bb7588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753419650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.753419650 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3710723345 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8603120000 ps |
| CPU time | 27.98 seconds |
| Started | Jul 21 04:18:11 PM PDT 24 |
| Finished | Jul 21 04:19:02 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-b81f8090-4271-4faa-8149-99cbd5359559 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710723345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3710723345 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2067415510 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3567480000 ps |
| CPU time | 11.92 seconds |
| Started | Jul 21 04:18:11 PM PDT 24 |
| Finished | Jul 21 04:18:33 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-dfcab009-5656-47e4-8b6e-f0b4fb8a6fd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067415510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2067415510 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3287420889 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11479920000 ps |
| CPU time | 40.25 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:22 PM PDT 24 |
| Peak memory | 144532 kb |
| Host | smart-6bd980d7-4ee5-4228-8d86-06789c40a2cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287420889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3287420889 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1621094623 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10789240000 ps |
| CPU time | 41.96 seconds |
| Started | Jul 21 04:18:07 PM PDT 24 |
| Finished | Jul 21 04:19:28 PM PDT 24 |
| Peak memory | 143376 kb |
| Host | smart-cb050e24-b01a-4381-9143-3e7e731fad5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621094623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1621094623 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1313966396 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7347620000 ps |
| CPU time | 26.39 seconds |
| Started | Jul 21 04:18:08 PM PDT 24 |
| Finished | Jul 21 04:18:58 PM PDT 24 |
| Peak memory | 144608 kb |
| Host | smart-46ba6010-c9a9-4bc3-88c1-7334d33924e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313966396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1313966396 |
| Directory | /workspace/9.prim_present_test/latest |
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