| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2846755939 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.1177652913 |
| /workspace/coverage/default/10.prim_present_test.3269001507 |
| /workspace/coverage/default/11.prim_present_test.1991443043 |
| /workspace/coverage/default/12.prim_present_test.957855124 |
| /workspace/coverage/default/13.prim_present_test.3097674749 |
| /workspace/coverage/default/14.prim_present_test.853600711 |
| /workspace/coverage/default/15.prim_present_test.2257643148 |
| /workspace/coverage/default/16.prim_present_test.1370428285 |
| /workspace/coverage/default/17.prim_present_test.4294507703 |
| /workspace/coverage/default/18.prim_present_test.2915901621 |
| /workspace/coverage/default/19.prim_present_test.2003322322 |
| /workspace/coverage/default/2.prim_present_test.2855876352 |
| /workspace/coverage/default/20.prim_present_test.3150824248 |
| /workspace/coverage/default/21.prim_present_test.2877997987 |
| /workspace/coverage/default/22.prim_present_test.1076253147 |
| /workspace/coverage/default/23.prim_present_test.3510125068 |
| /workspace/coverage/default/24.prim_present_test.1641453247 |
| /workspace/coverage/default/25.prim_present_test.3836428837 |
| /workspace/coverage/default/26.prim_present_test.160496306 |
| /workspace/coverage/default/27.prim_present_test.467464370 |
| /workspace/coverage/default/28.prim_present_test.754265233 |
| /workspace/coverage/default/29.prim_present_test.3865237794 |
| /workspace/coverage/default/3.prim_present_test.688731868 |
| /workspace/coverage/default/30.prim_present_test.3687194611 |
| /workspace/coverage/default/31.prim_present_test.3025566228 |
| /workspace/coverage/default/32.prim_present_test.289414975 |
| /workspace/coverage/default/33.prim_present_test.2362512366 |
| /workspace/coverage/default/34.prim_present_test.3079015351 |
| /workspace/coverage/default/35.prim_present_test.4266702977 |
| /workspace/coverage/default/36.prim_present_test.1823187470 |
| /workspace/coverage/default/37.prim_present_test.378857405 |
| /workspace/coverage/default/38.prim_present_test.2590902064 |
| /workspace/coverage/default/39.prim_present_test.1807570462 |
| /workspace/coverage/default/4.prim_present_test.2721286095 |
| /workspace/coverage/default/40.prim_present_test.459025013 |
| /workspace/coverage/default/41.prim_present_test.1969292158 |
| /workspace/coverage/default/42.prim_present_test.1841092743 |
| /workspace/coverage/default/43.prim_present_test.3018790412 |
| /workspace/coverage/default/44.prim_present_test.1185286073 |
| /workspace/coverage/default/45.prim_present_test.2849172556 |
| /workspace/coverage/default/46.prim_present_test.3584510702 |
| /workspace/coverage/default/47.prim_present_test.1925904788 |
| /workspace/coverage/default/48.prim_present_test.2053167514 |
| /workspace/coverage/default/49.prim_present_test.3912009614 |
| /workspace/coverage/default/5.prim_present_test.560128126 |
| /workspace/coverage/default/6.prim_present_test.2878851538 |
| /workspace/coverage/default/7.prim_present_test.181003081 |
| /workspace/coverage/default/8.prim_present_test.2011188097 |
| /workspace/coverage/default/9.prim_present_test.1037613837 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/34.prim_present_test.3079015351 | Jul 22 06:33:52 PM PDT 24 | Jul 22 06:35:07 PM PDT 24 | 11466900000 ps | ||
| T2 | /workspace/coverage/default/36.prim_present_test.1823187470 | Jul 22 06:33:52 PM PDT 24 | Jul 22 06:34:13 PM PDT 24 | 3251900000 ps | ||
| T3 | /workspace/coverage/default/25.prim_present_test.3836428837 | Jul 22 06:33:52 PM PDT 24 | Jul 22 06:34:33 PM PDT 24 | 5648820000 ps | ||
| T4 | /workspace/coverage/default/9.prim_present_test.1037613837 | Jul 22 06:33:43 PM PDT 24 | Jul 22 06:34:28 PM PDT 24 | 6810080000 ps | ||
| T5 | /workspace/coverage/default/41.prim_present_test.1969292158 | Jul 22 06:33:50 PM PDT 24 | Jul 22 06:35:36 PM PDT 24 | 14829780000 ps | ||
| T6 | /workspace/coverage/default/32.prim_present_test.289414975 | Jul 22 06:33:59 PM PDT 24 | Jul 22 06:35:24 PM PDT 24 | 13635040000 ps | ||
| T7 | /workspace/coverage/default/31.prim_present_test.3025566228 | Jul 22 06:33:51 PM PDT 24 | Jul 22 06:35:16 PM PDT 24 | 12522760000 ps | ||
| T8 | /workspace/coverage/default/45.prim_present_test.2849172556 | Jul 22 06:33:54 PM PDT 24 | Jul 22 06:34:31 PM PDT 24 | 5106940000 ps | ||
| T9 | /workspace/coverage/default/0.prim_present_test.2846755939 | Jul 22 06:33:43 PM PDT 24 | Jul 22 06:35:04 PM PDT 24 | 10574720000 ps | ||
| T10 | /workspace/coverage/default/26.prim_present_test.160496306 | Jul 22 06:33:52 PM PDT 24 | Jul 22 06:34:21 PM PDT 24 | 3985360000 ps | ||
| T11 | /workspace/coverage/default/12.prim_present_test.957855124 | Jul 22 06:34:29 PM PDT 24 | Jul 22 06:34:50 PM PDT 24 | 3511060000 ps | ||
| T12 | /workspace/coverage/default/14.prim_present_test.853600711 | Jul 22 06:34:29 PM PDT 24 | Jul 22 06:35:12 PM PDT 24 | 8035200000 ps | ||
| T13 | /workspace/coverage/default/44.prim_present_test.1185286073 | Jul 22 06:33:54 PM PDT 24 | Jul 22 06:35:24 PM PDT 24 | 13592260000 ps | ||
| T14 | /workspace/coverage/default/1.prim_present_test.1177652913 | Jul 22 06:33:44 PM PDT 24 | Jul 22 06:34:40 PM PDT 24 | 7758060000 ps | ||
| T15 | /workspace/coverage/default/28.prim_present_test.754265233 | Jul 22 06:33:51 PM PDT 24 | Jul 22 06:35:16 PM PDT 24 | 11918260000 ps | ||
| T16 | /workspace/coverage/default/42.prim_present_test.1841092743 | Jul 22 06:33:52 PM PDT 24 | Jul 22 06:35:04 PM PDT 24 | 11055220000 ps | ||
| T17 | /workspace/coverage/default/48.prim_present_test.2053167514 | Jul 22 06:33:50 PM PDT 24 | Jul 22 06:35:24 PM PDT 24 | 12774480000 ps | ||
| T18 | /workspace/coverage/default/23.prim_present_test.3510125068 | Jul 22 06:33:55 PM PDT 24 | Jul 22 06:35:24 PM PDT 24 | 12953660000 ps | ||
| T19 | /workspace/coverage/default/46.prim_present_test.3584510702 | Jul 22 06:33:49 PM PDT 24 | Jul 22 06:35:05 PM PDT 24 | 9993160000 ps | ||
| T20 | /workspace/coverage/default/20.prim_present_test.3150824248 | Jul 22 06:33:54 PM PDT 24 | Jul 22 06:35:07 PM PDT 24 | 10161800000 ps | ||
| T21 | /workspace/coverage/default/37.prim_present_test.378857405 | Jul 22 06:33:59 PM PDT 24 | Jul 22 06:34:53 PM PDT 24 | 8453080000 ps | ||
| T22 | /workspace/coverage/default/29.prim_present_test.3865237794 | Jul 22 06:33:53 PM PDT 24 | Jul 22 06:34:26 PM PDT 24 | 4778960000 ps | ||
| T23 | /workspace/coverage/default/17.prim_present_test.4294507703 | Jul 22 06:33:42 PM PDT 24 | Jul 22 06:34:44 PM PDT 24 | 7854780000 ps | ||
| T24 | /workspace/coverage/default/38.prim_present_test.2590902064 | Jul 22 06:33:54 PM PDT 24 | Jul 22 06:35:08 PM PDT 24 | 9801580000 ps | ||
| T25 | /workspace/coverage/default/47.prim_present_test.1925904788 | Jul 22 06:33:52 PM PDT 24 | Jul 22 06:35:25 PM PDT 24 | 15054840000 ps | ||
| T26 | /workspace/coverage/default/40.prim_present_test.459025013 | Jul 22 06:33:52 PM PDT 24 | Jul 22 06:34:48 PM PDT 24 | 7704740000 ps | ||
| T27 | /workspace/coverage/default/2.prim_present_test.2855876352 | Jul 22 06:33:46 PM PDT 24 | Jul 22 06:34:30 PM PDT 24 | 6296720000 ps | ||
| T28 | /workspace/coverage/default/24.prim_present_test.1641453247 | Jul 22 06:33:55 PM PDT 24 | Jul 22 06:35:09 PM PDT 24 | 13016900000 ps | ||
| T29 | /workspace/coverage/default/19.prim_present_test.2003322322 | Jul 22 06:33:42 PM PDT 24 | Jul 22 06:35:13 PM PDT 24 | 13620780000 ps | ||
| T30 | /workspace/coverage/default/7.prim_present_test.181003081 | Jul 22 06:33:41 PM PDT 24 | Jul 22 06:34:23 PM PDT 24 | 6480860000 ps | ||
| T31 | /workspace/coverage/default/35.prim_present_test.4266702977 | Jul 22 06:33:55 PM PDT 24 | Jul 22 06:34:41 PM PDT 24 | 6317180000 ps | ||
| T32 | /workspace/coverage/default/18.prim_present_test.2915901621 | Jul 22 06:33:44 PM PDT 24 | Jul 22 06:34:57 PM PDT 24 | 10311220000 ps | ||
| T33 | /workspace/coverage/default/30.prim_present_test.3687194611 | Jul 22 06:33:50 PM PDT 24 | Jul 22 06:35:28 PM PDT 24 | 13315740000 ps | ||
| T34 | /workspace/coverage/default/11.prim_present_test.1991443043 | Jul 22 06:33:42 PM PDT 24 | Jul 22 06:34:48 PM PDT 24 | 9890240000 ps | ||
| T35 | /workspace/coverage/default/13.prim_present_test.3097674749 | Jul 22 06:33:46 PM PDT 24 | Jul 22 06:34:35 PM PDT 24 | 7005380000 ps | ||
| T36 | /workspace/coverage/default/8.prim_present_test.2011188097 | Jul 22 06:33:41 PM PDT 24 | Jul 22 06:34:56 PM PDT 24 | 11687000000 ps | ||
| T37 | /workspace/coverage/default/4.prim_present_test.2721286095 | Jul 22 06:33:43 PM PDT 24 | Jul 22 06:34:21 PM PDT 24 | 5356800000 ps | ||
| T38 | /workspace/coverage/default/15.prim_present_test.2257643148 | Jul 22 06:33:41 PM PDT 24 | Jul 22 06:35:00 PM PDT 24 | 10220080000 ps | ||
| T39 | /workspace/coverage/default/43.prim_present_test.3018790412 | Jul 22 06:33:50 PM PDT 24 | Jul 22 06:34:55 PM PDT 24 | 11181080000 ps | ||
| T40 | /workspace/coverage/default/5.prim_present_test.560128126 | Jul 22 06:33:43 PM PDT 24 | Jul 22 06:35:35 PM PDT 24 | 15253860000 ps | ||
| T41 | /workspace/coverage/default/16.prim_present_test.1370428285 | Jul 22 06:34:56 PM PDT 24 | Jul 22 06:36:09 PM PDT 24 | 12920180000 ps | ||
| T42 | /workspace/coverage/default/3.prim_present_test.688731868 | Jul 22 06:33:40 PM PDT 24 | Jul 22 06:34:22 PM PDT 24 | 6529840000 ps | ||
| T43 | /workspace/coverage/default/49.prim_present_test.3912009614 | Jul 22 06:33:58 PM PDT 24 | Jul 22 06:34:55 PM PDT 24 | 8833140000 ps | ||
| T44 | /workspace/coverage/default/27.prim_present_test.467464370 | Jul 22 06:33:51 PM PDT 24 | Jul 22 06:34:52 PM PDT 24 | 8756260000 ps | ||
| T45 | /workspace/coverage/default/33.prim_present_test.2362512366 | Jul 22 06:33:53 PM PDT 24 | Jul 22 06:34:19 PM PDT 24 | 4043640000 ps | ||
| T46 | /workspace/coverage/default/6.prim_present_test.2878851538 | Jul 22 06:33:46 PM PDT 24 | Jul 22 06:35:15 PM PDT 24 | 12592200000 ps | ||
| T47 | /workspace/coverage/default/39.prim_present_test.1807570462 | Jul 22 06:33:52 PM PDT 24 | Jul 22 06:35:27 PM PDT 24 | 14431740000 ps | ||
| T48 | /workspace/coverage/default/10.prim_present_test.3269001507 | Jul 22 06:34:29 PM PDT 24 | Jul 22 06:35:13 PM PDT 24 | 7534860000 ps | ||
| T49 | /workspace/coverage/default/21.prim_present_test.2877997987 | Jul 22 06:33:50 PM PDT 24 | Jul 22 06:34:34 PM PDT 24 | 6352520000 ps | ||
| T50 | /workspace/coverage/default/22.prim_present_test.1076253147 | Jul 22 06:33:59 PM PDT 24 | Jul 22 06:34:21 PM PDT 24 | 3752240000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2846755939 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10574720000 ps |
| CPU time | 41.75 seconds |
| Started | Jul 22 06:33:43 PM PDT 24 |
| Finished | Jul 22 06:35:04 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-f08ee870-b0ce-4e5a-84cb-d3bec1f8df1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846755939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2846755939 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1177652913 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7758060000 ps |
| CPU time | 28.93 seconds |
| Started | Jul 22 06:33:44 PM PDT 24 |
| Finished | Jul 22 06:34:40 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-7c355254-b5fb-4569-b92e-466825efd65b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177652913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1177652913 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3269001507 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7534860000 ps |
| CPU time | 23.51 seconds |
| Started | Jul 22 06:34:29 PM PDT 24 |
| Finished | Jul 22 06:35:13 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-4528fc42-95ba-4d1e-8399-b9c8b60b748f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269001507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3269001507 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1991443043 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9890240000 ps |
| CPU time | 35.29 seconds |
| Started | Jul 22 06:33:42 PM PDT 24 |
| Finished | Jul 22 06:34:48 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-d29278d9-9b19-488f-8618-13972db6a969 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991443043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1991443043 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.957855124 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3511060000 ps |
| CPU time | 10.95 seconds |
| Started | Jul 22 06:34:29 PM PDT 24 |
| Finished | Jul 22 06:34:50 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-09a7d440-8bc9-4e22-b771-3bb7b6d1b933 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=957855124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.957855124 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3097674749 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7005380000 ps |
| CPU time | 25.46 seconds |
| Started | Jul 22 06:33:46 PM PDT 24 |
| Finished | Jul 22 06:34:35 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-b25c8e49-7533-4253-8778-a638cf07cf21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097674749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3097674749 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.853600711 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8035200000 ps |
| CPU time | 23.33 seconds |
| Started | Jul 22 06:34:29 PM PDT 24 |
| Finished | Jul 22 06:35:12 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-413a427a-28df-4b73-8868-77b7b16fcab9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853600711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.853600711 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2257643148 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10220080000 ps |
| CPU time | 40.78 seconds |
| Started | Jul 22 06:33:41 PM PDT 24 |
| Finished | Jul 22 06:35:00 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-86e507d8-d397-4866-a825-c480ca9dae3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257643148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2257643148 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1370428285 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12920180000 ps |
| CPU time | 38.86 seconds |
| Started | Jul 22 06:34:56 PM PDT 24 |
| Finished | Jul 22 06:36:09 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-6e6023b9-80c2-44d3-8a5d-4138d99194cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370428285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1370428285 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4294507703 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7854780000 ps |
| CPU time | 32.02 seconds |
| Started | Jul 22 06:33:42 PM PDT 24 |
| Finished | Jul 22 06:34:44 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-0200c8bf-cd46-476c-b048-4a2f24586b11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294507703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4294507703 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2915901621 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10311220000 ps |
| CPU time | 38.3 seconds |
| Started | Jul 22 06:33:44 PM PDT 24 |
| Finished | Jul 22 06:34:57 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-f607f803-5a00-4159-8cb3-8895c687dbff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915901621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2915901621 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2003322322 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13620780000 ps |
| CPU time | 47.92 seconds |
| Started | Jul 22 06:33:42 PM PDT 24 |
| Finished | Jul 22 06:35:13 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-074249dd-ec91-46ce-8ede-25a12aea28b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003322322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2003322322 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2855876352 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6296720000 ps |
| CPU time | 22.83 seconds |
| Started | Jul 22 06:33:46 PM PDT 24 |
| Finished | Jul 22 06:34:30 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-58d7d2d1-749f-4d87-bc46-6e8d7c0ef0ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855876352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2855876352 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3150824248 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10161800000 ps |
| CPU time | 39 seconds |
| Started | Jul 22 06:33:54 PM PDT 24 |
| Finished | Jul 22 06:35:07 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-05a35520-ba07-4a52-9922-a1e6369237a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150824248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3150824248 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2877997987 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6352520000 ps |
| CPU time | 23.34 seconds |
| Started | Jul 22 06:33:50 PM PDT 24 |
| Finished | Jul 22 06:34:34 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-fc54ca9d-7e39-4a33-9979-9e3c8754f178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877997987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2877997987 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1076253147 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3752240000 ps |
| CPU time | 11.68 seconds |
| Started | Jul 22 06:33:59 PM PDT 24 |
| Finished | Jul 22 06:34:21 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-cddb06a2-e8cb-4f26-8ec6-435b3254023c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1076253147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1076253147 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3510125068 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12953660000 ps |
| CPU time | 46.43 seconds |
| Started | Jul 22 06:33:55 PM PDT 24 |
| Finished | Jul 22 06:35:24 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-8ac25fb2-4752-44c9-8bdb-471e2fcdbf63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510125068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3510125068 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1641453247 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13016900000 ps |
| CPU time | 39.43 seconds |
| Started | Jul 22 06:33:55 PM PDT 24 |
| Finished | Jul 22 06:35:09 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-e5930922-9202-469c-a13d-eb1f4931b930 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641453247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1641453247 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3836428837 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5648820000 ps |
| CPU time | 21.77 seconds |
| Started | Jul 22 06:33:52 PM PDT 24 |
| Finished | Jul 22 06:34:33 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-b41d653c-7466-4d35-a529-602249b6f3f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3836428837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3836428837 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.160496306 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3985360000 ps |
| CPU time | 15.26 seconds |
| Started | Jul 22 06:33:52 PM PDT 24 |
| Finished | Jul 22 06:34:21 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-f9eee739-3f33-4bf0-abb0-fb46bf6d2d6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160496306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.160496306 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.467464370 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8756260000 ps |
| CPU time | 32.2 seconds |
| Started | Jul 22 06:33:51 PM PDT 24 |
| Finished | Jul 22 06:34:52 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-856470d8-6d38-427e-ab39-69f762b264fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467464370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.467464370 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.754265233 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11918260000 ps |
| CPU time | 44.26 seconds |
| Started | Jul 22 06:33:51 PM PDT 24 |
| Finished | Jul 22 06:35:16 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-7f9ac4db-3901-4a11-9ffd-4191e43a270d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754265233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.754265233 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3865237794 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4778960000 ps |
| CPU time | 17.32 seconds |
| Started | Jul 22 06:33:53 PM PDT 24 |
| Finished | Jul 22 06:34:26 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-961ddb0f-a85b-4699-abd6-2144f0df1ef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865237794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3865237794 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.688731868 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6529840000 ps |
| CPU time | 22.55 seconds |
| Started | Jul 22 06:33:40 PM PDT 24 |
| Finished | Jul 22 06:34:22 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-076409ab-df70-4577-b1ea-5db84cadd4cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688731868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.688731868 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3687194611 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13315740000 ps |
| CPU time | 51.67 seconds |
| Started | Jul 22 06:33:50 PM PDT 24 |
| Finished | Jul 22 06:35:28 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e5828fec-9396-4aef-aea5-4281116e0f11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687194611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3687194611 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3025566228 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12522760000 ps |
| CPU time | 45.06 seconds |
| Started | Jul 22 06:33:51 PM PDT 24 |
| Finished | Jul 22 06:35:16 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-708069f8-3f25-4deb-bf77-04bfe7efeae1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025566228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3025566228 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.289414975 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13635040000 ps |
| CPU time | 45.49 seconds |
| Started | Jul 22 06:33:59 PM PDT 24 |
| Finished | Jul 22 06:35:24 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-a37ac25b-4791-4fdb-8679-9bca67a898e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289414975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.289414975 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2362512366 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4043640000 ps |
| CPU time | 13.75 seconds |
| Started | Jul 22 06:33:53 PM PDT 24 |
| Finished | Jul 22 06:34:19 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-80bd6f11-f766-45b7-b4ac-8248ff7f6286 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362512366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2362512366 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3079015351 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11466900000 ps |
| CPU time | 39.35 seconds |
| Started | Jul 22 06:33:52 PM PDT 24 |
| Finished | Jul 22 06:35:07 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-00b1afa6-e519-4925-a5a3-a5d3a21b6ad8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079015351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3079015351 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4266702977 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6317180000 ps |
| CPU time | 23.67 seconds |
| Started | Jul 22 06:33:55 PM PDT 24 |
| Finished | Jul 22 06:34:41 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-54c62ca2-674f-4fa6-a6ed-e3f2315810b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266702977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4266702977 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1823187470 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3251900000 ps |
| CPU time | 10.91 seconds |
| Started | Jul 22 06:33:52 PM PDT 24 |
| Finished | Jul 22 06:34:13 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-1fae05bc-0905-4d46-a9fa-b10fff1f2573 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823187470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1823187470 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.378857405 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8453080000 ps |
| CPU time | 29.34 seconds |
| Started | Jul 22 06:33:59 PM PDT 24 |
| Finished | Jul 22 06:34:53 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-714ecd6e-5a68-4b86-9b84-d5eb131a3d08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378857405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.378857405 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2590902064 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9801580000 ps |
| CPU time | 38.17 seconds |
| Started | Jul 22 06:33:54 PM PDT 24 |
| Finished | Jul 22 06:35:08 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-ded91529-7c26-47ae-b538-0b1080b3526e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590902064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2590902064 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1807570462 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14431740000 ps |
| CPU time | 49.79 seconds |
| Started | Jul 22 06:33:52 PM PDT 24 |
| Finished | Jul 22 06:35:27 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-87fadff3-aa1f-4762-bcaa-ed733a315ff9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807570462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1807570462 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2721286095 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5356800000 ps |
| CPU time | 19.42 seconds |
| Started | Jul 22 06:33:43 PM PDT 24 |
| Finished | Jul 22 06:34:21 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-16134176-5714-4a07-85da-39c5190921f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721286095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2721286095 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.459025013 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7704740000 ps |
| CPU time | 29.37 seconds |
| Started | Jul 22 06:33:52 PM PDT 24 |
| Finished | Jul 22 06:34:48 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-3bc71fe2-2bc3-4d6f-98e4-0fe300ecb165 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459025013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.459025013 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1969292158 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14829780000 ps |
| CPU time | 55.16 seconds |
| Started | Jul 22 06:33:50 PM PDT 24 |
| Finished | Jul 22 06:35:36 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-d8d6eeeb-69a5-4e21-8ca8-c287c415c0e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969292158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1969292158 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1841092743 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11055220000 ps |
| CPU time | 37.91 seconds |
| Started | Jul 22 06:33:52 PM PDT 24 |
| Finished | Jul 22 06:35:04 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-b2f58c36-eb42-4e76-a778-07c1c0c2f360 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841092743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1841092743 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3018790412 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11181080000 ps |
| CPU time | 35.47 seconds |
| Started | Jul 22 06:33:50 PM PDT 24 |
| Finished | Jul 22 06:34:55 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-4545a497-b9b6-4dec-8116-a5c38c149e0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018790412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3018790412 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1185286073 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13592260000 ps |
| CPU time | 47.33 seconds |
| Started | Jul 22 06:33:54 PM PDT 24 |
| Finished | Jul 22 06:35:24 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-27fffb22-d2b4-4910-966f-f9fb4b59e801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185286073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1185286073 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2849172556 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5106940000 ps |
| CPU time | 19.47 seconds |
| Started | Jul 22 06:33:54 PM PDT 24 |
| Finished | Jul 22 06:34:31 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-dfaf5788-7701-46ca-bfa3-37aec35e217f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2849172556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2849172556 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3584510702 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9993160000 ps |
| CPU time | 39.05 seconds |
| Started | Jul 22 06:33:49 PM PDT 24 |
| Finished | Jul 22 06:35:05 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-226a7dc4-b3c7-4378-85e8-59430cc49cb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584510702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3584510702 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1925904788 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 15054840000 ps |
| CPU time | 49.66 seconds |
| Started | Jul 22 06:33:52 PM PDT 24 |
| Finished | Jul 22 06:35:25 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-299d1f7f-25d2-45b8-883b-e1f29c6606ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925904788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1925904788 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2053167514 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12774480000 ps |
| CPU time | 48.03 seconds |
| Started | Jul 22 06:33:50 PM PDT 24 |
| Finished | Jul 22 06:35:24 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-4d0cbbb3-df89-4eff-b5fd-e825584ca6c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053167514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2053167514 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3912009614 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8833140000 ps |
| CPU time | 29.95 seconds |
| Started | Jul 22 06:33:58 PM PDT 24 |
| Finished | Jul 22 06:34:55 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-a770bf74-dec7-4399-ab2f-fb10681a7e43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912009614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3912009614 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.560128126 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15253860000 ps |
| CPU time | 57.66 seconds |
| Started | Jul 22 06:33:43 PM PDT 24 |
| Finished | Jul 22 06:35:35 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-4cb0518b-3e33-4da9-9dee-f6c037ea7e3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560128126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.560128126 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2878851538 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12592200000 ps |
| CPU time | 47.22 seconds |
| Started | Jul 22 06:33:46 PM PDT 24 |
| Finished | Jul 22 06:35:15 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-9efd3394-f583-465a-8e4a-330fcda7ad31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878851538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2878851538 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.181003081 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6480860000 ps |
| CPU time | 22.35 seconds |
| Started | Jul 22 06:33:41 PM PDT 24 |
| Finished | Jul 22 06:34:23 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-85f040bb-c582-45f2-88c3-804545e09887 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=181003081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.181003081 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2011188097 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11687000000 ps |
| CPU time | 40.26 seconds |
| Started | Jul 22 06:33:41 PM PDT 24 |
| Finished | Jul 22 06:34:56 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-7d52221b-f106-452b-b13c-e4082fe5cd37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011188097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2011188097 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1037613837 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6810080000 ps |
| CPU time | 23.87 seconds |
| Started | Jul 22 06:33:43 PM PDT 24 |
| Finished | Jul 22 06:34:28 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-a0d704ab-1a12-47eb-98b8-be959a849990 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037613837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1037613837 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |