| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/14.prim_present_test.3586164384 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.862605226 |
| /workspace/coverage/default/1.prim_present_test.4235700957 |
| /workspace/coverage/default/10.prim_present_test.478032891 |
| /workspace/coverage/default/11.prim_present_test.542857262 |
| /workspace/coverage/default/12.prim_present_test.1050261642 |
| /workspace/coverage/default/13.prim_present_test.1112572477 |
| /workspace/coverage/default/15.prim_present_test.176445543 |
| /workspace/coverage/default/16.prim_present_test.445868094 |
| /workspace/coverage/default/17.prim_present_test.1791402590 |
| /workspace/coverage/default/18.prim_present_test.2192221356 |
| /workspace/coverage/default/19.prim_present_test.2924189348 |
| /workspace/coverage/default/2.prim_present_test.1028858488 |
| /workspace/coverage/default/20.prim_present_test.600273155 |
| /workspace/coverage/default/21.prim_present_test.265306592 |
| /workspace/coverage/default/22.prim_present_test.1264038262 |
| /workspace/coverage/default/23.prim_present_test.1223867766 |
| /workspace/coverage/default/24.prim_present_test.877021778 |
| /workspace/coverage/default/25.prim_present_test.3057230626 |
| /workspace/coverage/default/26.prim_present_test.1646484937 |
| /workspace/coverage/default/27.prim_present_test.4053415771 |
| /workspace/coverage/default/28.prim_present_test.527101104 |
| /workspace/coverage/default/29.prim_present_test.4287414951 |
| /workspace/coverage/default/3.prim_present_test.3031694656 |
| /workspace/coverage/default/30.prim_present_test.714023380 |
| /workspace/coverage/default/31.prim_present_test.1071063057 |
| /workspace/coverage/default/32.prim_present_test.547614695 |
| /workspace/coverage/default/33.prim_present_test.3746001945 |
| /workspace/coverage/default/34.prim_present_test.3212675849 |
| /workspace/coverage/default/35.prim_present_test.30031674 |
| /workspace/coverage/default/36.prim_present_test.2913439817 |
| /workspace/coverage/default/37.prim_present_test.2151539892 |
| /workspace/coverage/default/38.prim_present_test.2568319270 |
| /workspace/coverage/default/39.prim_present_test.3767687228 |
| /workspace/coverage/default/4.prim_present_test.1724541744 |
| /workspace/coverage/default/40.prim_present_test.2567826319 |
| /workspace/coverage/default/41.prim_present_test.1346144498 |
| /workspace/coverage/default/42.prim_present_test.2002129303 |
| /workspace/coverage/default/43.prim_present_test.2768466116 |
| /workspace/coverage/default/44.prim_present_test.1040427313 |
| /workspace/coverage/default/45.prim_present_test.1782364962 |
| /workspace/coverage/default/46.prim_present_test.3897103123 |
| /workspace/coverage/default/47.prim_present_test.3424638707 |
| /workspace/coverage/default/48.prim_present_test.3141743567 |
| /workspace/coverage/default/49.prim_present_test.2113175739 |
| /workspace/coverage/default/5.prim_present_test.203867533 |
| /workspace/coverage/default/6.prim_present_test.3132673352 |
| /workspace/coverage/default/7.prim_present_test.2734943368 |
| /workspace/coverage/default/8.prim_present_test.1180032497 |
| /workspace/coverage/default/9.prim_present_test.1700417494 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/23.prim_present_test.1223867766 | Jul 23 06:29:56 PM PDT 24 | Jul 23 06:31:12 PM PDT 24 | 12259260000 ps | ||
| T2 | /workspace/coverage/default/14.prim_present_test.3586164384 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:31:09 PM PDT 24 | 10363300000 ps | ||
| T3 | /workspace/coverage/default/38.prim_present_test.2568319270 | Jul 23 06:29:58 PM PDT 24 | Jul 23 06:31:00 PM PDT 24 | 8431380000 ps | ||
| T4 | /workspace/coverage/default/20.prim_present_test.600273155 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:30:35 PM PDT 24 | 6704060000 ps | ||
| T5 | /workspace/coverage/default/41.prim_present_test.1346144498 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:30:49 PM PDT 24 | 5925960000 ps | ||
| T6 | /workspace/coverage/default/4.prim_present_test.1724541744 | Jul 23 06:29:45 PM PDT 24 | Jul 23 06:31:30 PM PDT 24 | 14796920000 ps | ||
| T7 | /workspace/coverage/default/43.prim_present_test.2768466116 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:30:22 PM PDT 24 | 3252520000 ps | ||
| T8 | /workspace/coverage/default/48.prim_present_test.3141743567 | Jul 23 06:29:59 PM PDT 24 | Jul 23 06:30:30 PM PDT 24 | 4016980000 ps | ||
| T9 | /workspace/coverage/default/17.prim_present_test.1791402590 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:31:00 PM PDT 24 | 10666480000 ps | ||
| T10 | /workspace/coverage/default/31.prim_present_test.1071063057 | Jul 23 06:30:03 PM PDT 24 | Jul 23 06:31:28 PM PDT 24 | 13147720000 ps | ||
| T11 | /workspace/coverage/default/8.prim_present_test.1180032497 | Jul 23 06:29:44 PM PDT 24 | Jul 23 06:30:40 PM PDT 24 | 8031480000 ps | ||
| T12 | /workspace/coverage/default/47.prim_present_test.3424638707 | Jul 23 06:29:54 PM PDT 24 | Jul 23 06:30:42 PM PDT 24 | 7936000000 ps | ||
| T13 | /workspace/coverage/default/45.prim_present_test.1782364962 | Jul 23 06:30:03 PM PDT 24 | Jul 23 06:31:00 PM PDT 24 | 8221820000 ps | ||
| T14 | /workspace/coverage/default/18.prim_present_test.2192221356 | Jul 23 06:29:58 PM PDT 24 | Jul 23 06:31:11 PM PDT 24 | 10055780000 ps | ||
| T15 | /workspace/coverage/default/46.prim_present_test.3897103123 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:30:45 PM PDT 24 | 6965700000 ps | ||
| T16 | /workspace/coverage/default/9.prim_present_test.1700417494 | Jul 23 06:29:46 PM PDT 24 | Jul 23 06:31:36 PM PDT 24 | 15353680000 ps | ||
| T17 | /workspace/coverage/default/7.prim_present_test.2734943368 | Jul 23 06:29:45 PM PDT 24 | Jul 23 06:30:32 PM PDT 24 | 6686700000 ps | ||
| T18 | /workspace/coverage/default/42.prim_present_test.2002129303 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:31:28 PM PDT 24 | 13878080000 ps | ||
| T19 | /workspace/coverage/default/5.prim_present_test.203867533 | Jul 23 06:29:45 PM PDT 24 | Jul 23 06:31:26 PM PDT 24 | 14212880000 ps | ||
| T20 | /workspace/coverage/default/49.prim_present_test.2113175739 | Jul 23 06:30:01 PM PDT 24 | Jul 23 06:30:42 PM PDT 24 | 5778400000 ps | ||
| T21 | /workspace/coverage/default/24.prim_present_test.877021778 | Jul 23 06:29:54 PM PDT 24 | Jul 23 06:31:10 PM PDT 24 | 11067000000 ps | ||
| T22 | /workspace/coverage/default/3.prim_present_test.3031694656 | Jul 23 06:29:51 PM PDT 24 | Jul 23 06:30:44 PM PDT 24 | 6883240000 ps | ||
| T23 | /workspace/coverage/default/30.prim_present_test.714023380 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:31:31 PM PDT 24 | 14350520000 ps | ||
| T24 | /workspace/coverage/default/27.prim_present_test.4053415771 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:30:47 PM PDT 24 | 6522400000 ps | ||
| T25 | /workspace/coverage/default/15.prim_present_test.176445543 | Jul 23 06:29:56 PM PDT 24 | Jul 23 06:30:46 PM PDT 24 | 7922360000 ps | ||
| T26 | /workspace/coverage/default/13.prim_present_test.1112572477 | Jul 23 06:29:54 PM PDT 24 | Jul 23 06:31:15 PM PDT 24 | 12384500000 ps | ||
| T27 | /workspace/coverage/default/25.prim_present_test.3057230626 | Jul 23 06:29:57 PM PDT 24 | Jul 23 06:30:46 PM PDT 24 | 6121260000 ps | ||
| T28 | /workspace/coverage/default/10.prim_present_test.478032891 | Jul 23 06:29:58 PM PDT 24 | Jul 23 06:31:16 PM PDT 24 | 10040280000 ps | ||
| T29 | /workspace/coverage/default/32.prim_present_test.547614695 | Jul 23 06:29:56 PM PDT 24 | Jul 23 06:30:21 PM PDT 24 | 3850200000 ps | ||
| T30 | /workspace/coverage/default/40.prim_present_test.2567826319 | Jul 23 06:29:54 PM PDT 24 | Jul 23 06:30:33 PM PDT 24 | 5173280000 ps | ||
| T31 | /workspace/coverage/default/26.prim_present_test.1646484937 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:31:15 PM PDT 24 | 12943120000 ps | ||
| T32 | /workspace/coverage/default/29.prim_present_test.4287414951 | Jul 23 06:29:54 PM PDT 24 | Jul 23 06:30:47 PM PDT 24 | 7066760000 ps | ||
| T33 | /workspace/coverage/default/28.prim_present_test.527101104 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:30:22 PM PDT 24 | 3527800000 ps | ||
| T34 | /workspace/coverage/default/12.prim_present_test.1050261642 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:31:30 PM PDT 24 | 14655560000 ps | ||
| T35 | /workspace/coverage/default/44.prim_present_test.1040427313 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:31:09 PM PDT 24 | 10507140000 ps | ||
| T36 | /workspace/coverage/default/0.prim_present_test.862605226 | Jul 23 06:29:51 PM PDT 24 | Jul 23 06:31:17 PM PDT 24 | 13151440000 ps | ||
| T37 | /workspace/coverage/default/21.prim_present_test.265306592 | Jul 23 06:29:54 PM PDT 24 | Jul 23 06:31:10 PM PDT 24 | 10561700000 ps | ||
| T38 | /workspace/coverage/default/11.prim_present_test.542857262 | Jul 23 06:29:52 PM PDT 24 | Jul 23 06:30:43 PM PDT 24 | 7915540000 ps | ||
| T39 | /workspace/coverage/default/16.prim_present_test.445868094 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:31:49 PM PDT 24 | 13569940000 ps | ||
| T40 | /workspace/coverage/default/6.prim_present_test.3132673352 | Jul 23 06:29:45 PM PDT 24 | Jul 23 06:30:34 PM PDT 24 | 6894400000 ps | ||
| T41 | /workspace/coverage/default/39.prim_present_test.3767687228 | Jul 23 06:29:57 PM PDT 24 | Jul 23 06:30:57 PM PDT 24 | 8636600000 ps | ||
| T42 | /workspace/coverage/default/37.prim_present_test.2151539892 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:30:37 PM PDT 24 | 6761720000 ps | ||
| T43 | /workspace/coverage/default/33.prim_present_test.3746001945 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:31:19 PM PDT 24 | 12827180000 ps | ||
| T44 | /workspace/coverage/default/22.prim_present_test.1264038262 | Jul 23 06:29:57 PM PDT 24 | Jul 23 06:31:21 PM PDT 24 | 11039720000 ps | ||
| T45 | /workspace/coverage/default/36.prim_present_test.2913439817 | Jul 23 06:29:53 PM PDT 24 | Jul 23 06:30:52 PM PDT 24 | 8389220000 ps | ||
| T46 | /workspace/coverage/default/1.prim_present_test.4235700957 | Jul 23 06:29:44 PM PDT 24 | Jul 23 06:30:58 PM PDT 24 | 10209540000 ps | ||
| T47 | /workspace/coverage/default/2.prim_present_test.1028858488 | Jul 23 06:29:44 PM PDT 24 | Jul 23 06:30:51 PM PDT 24 | 9373160000 ps | ||
| T48 | /workspace/coverage/default/35.prim_present_test.30031674 | Jul 23 06:29:55 PM PDT 24 | Jul 23 06:31:07 PM PDT 24 | 11497280000 ps | ||
| T49 | /workspace/coverage/default/34.prim_present_test.3212675849 | Jul 23 06:29:54 PM PDT 24 | Jul 23 06:30:48 PM PDT 24 | 7833080000 ps | ||
| T50 | /workspace/coverage/default/19.prim_present_test.2924189348 | Jul 23 06:29:56 PM PDT 24 | Jul 23 06:31:18 PM PDT 24 | 11735360000 ps |
| Test location | /workspace/coverage/default/14.prim_present_test.3586164384 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10363300000 ps |
| CPU time | 39.4 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:31:09 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-c772f45f-6d94-4b4c-ad13-f628d46bebc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586164384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3586164384 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.862605226 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13151440000 ps |
| CPU time | 44.84 seconds |
| Started | Jul 23 06:29:51 PM PDT 24 |
| Finished | Jul 23 06:31:17 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-821478e4-c16d-4ad3-9c99-54ef0a481414 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862605226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.862605226 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4235700957 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10209540000 ps |
| CPU time | 37.4 seconds |
| Started | Jul 23 06:29:44 PM PDT 24 |
| Finished | Jul 23 06:30:58 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-2d25d760-a24f-49ac-96f9-0ea994069019 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235700957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4235700957 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.478032891 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10040280000 ps |
| CPU time | 39.51 seconds |
| Started | Jul 23 06:29:58 PM PDT 24 |
| Finished | Jul 23 06:31:16 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-e92d8cc9-3c46-4d2f-a834-b5b2aea3b5a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478032891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.478032891 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.542857262 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7915540000 ps |
| CPU time | 26.66 seconds |
| Started | Jul 23 06:29:52 PM PDT 24 |
| Finished | Jul 23 06:30:43 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-17273031-2fb6-406b-a0d0-f3585f7aa3a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542857262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.542857262 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1050261642 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 14655560000 ps |
| CPU time | 49.74 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:31:30 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-f0aa90d9-af08-45f7-bdc8-897389d02df8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050261642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1050261642 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1112572477 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12384500000 ps |
| CPU time | 42.41 seconds |
| Started | Jul 23 06:29:54 PM PDT 24 |
| Finished | Jul 23 06:31:15 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-4959e345-0890-4e6a-9799-00fbe30ba048 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112572477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1112572477 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.176445543 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7922360000 ps |
| CPU time | 26.12 seconds |
| Started | Jul 23 06:29:56 PM PDT 24 |
| Finished | Jul 23 06:30:46 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-a0478c48-f54e-483b-83f1-4047a41dcd8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176445543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.176445543 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.445868094 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13569940000 ps |
| CPU time | 56.99 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:31:49 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-29f6cd8b-bdce-4778-8740-4d231f5af1a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445868094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.445868094 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1791402590 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10666480000 ps |
| CPU time | 34.23 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:31:00 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-d0cdbc4f-8ded-43a8-aa9e-74e3c64fffc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791402590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1791402590 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2192221356 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10055780000 ps |
| CPU time | 38.19 seconds |
| Started | Jul 23 06:29:58 PM PDT 24 |
| Finished | Jul 23 06:31:11 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c1871122-91ab-45b5-948f-7b8dcec33f1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2192221356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2192221356 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2924189348 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11735360000 ps |
| CPU time | 42.49 seconds |
| Started | Jul 23 06:29:56 PM PDT 24 |
| Finished | Jul 23 06:31:18 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-d5597233-83c9-4f80-944d-0a039bfc1e58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924189348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2924189348 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1028858488 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9373160000 ps |
| CPU time | 34.09 seconds |
| Started | Jul 23 06:29:44 PM PDT 24 |
| Finished | Jul 23 06:30:51 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-aa697171-60d2-40b9-afaf-f24f0bb89ec4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028858488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1028858488 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.600273155 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6704060000 ps |
| CPU time | 21.6 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:30:35 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-b4056481-4150-41d3-be73-5c53ee007be1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=600273155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.600273155 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.265306592 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10561700000 ps |
| CPU time | 39.21 seconds |
| Started | Jul 23 06:29:54 PM PDT 24 |
| Finished | Jul 23 06:31:10 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-03f6a742-bb1a-4bd5-8592-de037961fc26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265306592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.265306592 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1264038262 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11039720000 ps |
| CPU time | 42.75 seconds |
| Started | Jul 23 06:29:57 PM PDT 24 |
| Finished | Jul 23 06:31:21 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-0023cbbe-39b8-4a51-aa75-0630adfc1219 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264038262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1264038262 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1223867766 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12259260000 ps |
| CPU time | 40.41 seconds |
| Started | Jul 23 06:29:56 PM PDT 24 |
| Finished | Jul 23 06:31:12 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-c77a76b8-6f5b-4bc3-94b7-0aa35604886c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223867766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1223867766 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.877021778 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11067000000 ps |
| CPU time | 39.34 seconds |
| Started | Jul 23 06:29:54 PM PDT 24 |
| Finished | Jul 23 06:31:10 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-12b42542-e493-4721-ab22-7e5f7399a806 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877021778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.877021778 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3057230626 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6121260000 ps |
| CPU time | 24.3 seconds |
| Started | Jul 23 06:29:57 PM PDT 24 |
| Finished | Jul 23 06:30:46 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-bae33d19-845c-46f6-bbe3-bd707341b379 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057230626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3057230626 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1646484937 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12943120000 ps |
| CPU time | 43.01 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:31:15 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-ed936729-af4d-41c6-beb0-8b67f0ef767f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646484937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1646484937 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.4053415771 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6522400000 ps |
| CPU time | 26.56 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:30:47 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-6d1e114d-887f-4482-8c08-240403f11205 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053415771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.4053415771 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.527101104 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3527800000 ps |
| CPU time | 14.71 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:30:22 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-a7d9fb29-291d-49dd-aa2a-6122b3cc2a17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=527101104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.527101104 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4287414951 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7066760000 ps |
| CPU time | 26.89 seconds |
| Started | Jul 23 06:29:54 PM PDT 24 |
| Finished | Jul 23 06:30:47 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-84694fab-d995-4880-840e-7ec2e38db591 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287414951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4287414951 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3031694656 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6883240000 ps |
| CPU time | 27.24 seconds |
| Started | Jul 23 06:29:51 PM PDT 24 |
| Finished | Jul 23 06:30:44 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-70896808-c441-4c31-a6d1-437d96a417ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031694656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3031694656 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.714023380 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14350520000 ps |
| CPU time | 50.71 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:31:31 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-146e10a1-993e-4605-aaa5-b0ec5f1ce55b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714023380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.714023380 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1071063057 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13147720000 ps |
| CPU time | 42.54 seconds |
| Started | Jul 23 06:30:03 PM PDT 24 |
| Finished | Jul 23 06:31:28 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-6682bda0-8d27-4a6e-a0fe-d494aed18bfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071063057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1071063057 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.547614695 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3850200000 ps |
| CPU time | 12.72 seconds |
| Started | Jul 23 06:29:56 PM PDT 24 |
| Finished | Jul 23 06:30:21 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-d6a6184e-be0e-4aa2-a2f6-2fa89d8312b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547614695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.547614695 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3746001945 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12827180000 ps |
| CPU time | 44.55 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:31:19 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-df59517a-e216-4637-b59c-1c2c50308c02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746001945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3746001945 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3212675849 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7833080000 ps |
| CPU time | 28.02 seconds |
| Started | Jul 23 06:29:54 PM PDT 24 |
| Finished | Jul 23 06:30:48 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-4232bee0-156b-49ee-a1a8-3a60050962a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212675849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3212675849 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.30031674 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11497280000 ps |
| CPU time | 37.38 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:31:07 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-5c404a78-b192-4feb-9a40-e37fe8f25da9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30031674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.30031674 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2913439817 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8389220000 ps |
| CPU time | 30.67 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:30:52 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-5a86d85c-e3c6-4695-9a6f-b92dd030d983 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913439817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2913439817 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2151539892 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6761720000 ps |
| CPU time | 22.55 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:30:37 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-d2f5eb56-4cbf-4daf-a807-b0be8b4f880e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151539892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2151539892 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2568319270 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8431380000 ps |
| CPU time | 32.29 seconds |
| Started | Jul 23 06:29:58 PM PDT 24 |
| Finished | Jul 23 06:31:00 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-361ee50b-8cdf-400a-ba87-557b0c35a4d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568319270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2568319270 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3767687228 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8636600000 ps |
| CPU time | 31.09 seconds |
| Started | Jul 23 06:29:57 PM PDT 24 |
| Finished | Jul 23 06:30:57 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ec3b3be0-0ee6-4935-af2f-dbfb115617ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767687228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3767687228 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1724541744 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14796920000 ps |
| CPU time | 53.65 seconds |
| Started | Jul 23 06:29:45 PM PDT 24 |
| Finished | Jul 23 06:31:30 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-89a9d66a-909f-4805-9f39-f381d5fe3ba9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1724541744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1724541744 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2567826319 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5173280000 ps |
| CPU time | 19.51 seconds |
| Started | Jul 23 06:29:54 PM PDT 24 |
| Finished | Jul 23 06:30:33 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-cccd1491-1cec-4fce-b50e-5dd255e5e7e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567826319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2567826319 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1346144498 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5925960000 ps |
| CPU time | 26.16 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:30:49 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-4c33bb67-aa47-48ed-ab78-87bc2cb909ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1346144498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1346144498 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2002129303 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13878080000 ps |
| CPU time | 48.89 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:31:28 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c165dfc6-79c6-447a-9951-56e0a59a6ce7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002129303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2002129303 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2768466116 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3252520000 ps |
| CPU time | 13.61 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:30:22 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-812d5255-6083-4c72-ba93-467da4e4a305 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768466116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2768466116 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1040427313 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10507140000 ps |
| CPU time | 38.99 seconds |
| Started | Jul 23 06:29:55 PM PDT 24 |
| Finished | Jul 23 06:31:09 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-b7dedf1e-b778-40bf-a769-15aa5c543147 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040427313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1040427313 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1782364962 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8221820000 ps |
| CPU time | 27.74 seconds |
| Started | Jul 23 06:30:03 PM PDT 24 |
| Finished | Jul 23 06:31:00 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-cf52dc98-b662-41f5-a19b-032f977acc94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782364962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1782364962 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3897103123 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6965700000 ps |
| CPU time | 26.63 seconds |
| Started | Jul 23 06:29:53 PM PDT 24 |
| Finished | Jul 23 06:30:45 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-547f7092-900c-4aa1-a90c-0bbd1b29420d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897103123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3897103123 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3424638707 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7936000000 ps |
| CPU time | 25.13 seconds |
| Started | Jul 23 06:29:54 PM PDT 24 |
| Finished | Jul 23 06:30:42 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-66df7d71-c60e-4817-8fc8-694e695f0dc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424638707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3424638707 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3141743567 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4016980000 ps |
| CPU time | 15.82 seconds |
| Started | Jul 23 06:29:59 PM PDT 24 |
| Finished | Jul 23 06:30:30 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-aa2ab023-b492-4e8c-9940-e43e31093812 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3141743567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3141743567 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2113175739 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5778400000 ps |
| CPU time | 21.23 seconds |
| Started | Jul 23 06:30:01 PM PDT 24 |
| Finished | Jul 23 06:30:42 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-fc5d03c4-f615-4e36-bfb2-531d04df4017 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113175739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2113175739 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.203867533 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14212880000 ps |
| CPU time | 52.16 seconds |
| Started | Jul 23 06:29:45 PM PDT 24 |
| Finished | Jul 23 06:31:26 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-7de27699-0700-479e-901c-25c3c21c7ea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203867533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.203867533 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3132673352 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6894400000 ps |
| CPU time | 24.26 seconds |
| Started | Jul 23 06:29:45 PM PDT 24 |
| Finished | Jul 23 06:30:34 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-f17e1836-02b7-4e9d-80c6-24c44b1e5c02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132673352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3132673352 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2734943368 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6686700000 ps |
| CPU time | 23.1 seconds |
| Started | Jul 23 06:29:45 PM PDT 24 |
| Finished | Jul 23 06:30:32 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-7c42565b-79a0-458b-a9c8-a8d0da401890 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734943368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2734943368 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1180032497 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8031480000 ps |
| CPU time | 28.03 seconds |
| Started | Jul 23 06:29:44 PM PDT 24 |
| Finished | Jul 23 06:30:40 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-e004b032-53c1-4389-8643-63283355bfa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180032497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1180032497 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1700417494 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 15353680000 ps |
| CPU time | 55.88 seconds |
| Started | Jul 23 06:29:46 PM PDT 24 |
| Finished | Jul 23 06:31:36 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-9d310f8a-fb88-4e62-a23a-2a1399960c9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700417494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1700417494 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |