| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.2538727847 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2078638065 |
| /workspace/coverage/default/1.prim_present_test.3344411536 |
| /workspace/coverage/default/11.prim_present_test.3602342412 |
| /workspace/coverage/default/12.prim_present_test.1021608764 |
| /workspace/coverage/default/13.prim_present_test.3426103801 |
| /workspace/coverage/default/14.prim_present_test.1342090342 |
| /workspace/coverage/default/15.prim_present_test.3193950204 |
| /workspace/coverage/default/16.prim_present_test.2157567172 |
| /workspace/coverage/default/17.prim_present_test.2594380563 |
| /workspace/coverage/default/18.prim_present_test.1819587494 |
| /workspace/coverage/default/19.prim_present_test.3577277206 |
| /workspace/coverage/default/2.prim_present_test.1842843761 |
| /workspace/coverage/default/20.prim_present_test.2278113938 |
| /workspace/coverage/default/21.prim_present_test.3297374139 |
| /workspace/coverage/default/22.prim_present_test.3359179234 |
| /workspace/coverage/default/23.prim_present_test.1236886623 |
| /workspace/coverage/default/24.prim_present_test.3871935407 |
| /workspace/coverage/default/25.prim_present_test.459222494 |
| /workspace/coverage/default/26.prim_present_test.1365849873 |
| /workspace/coverage/default/27.prim_present_test.2452585318 |
| /workspace/coverage/default/28.prim_present_test.4140128052 |
| /workspace/coverage/default/29.prim_present_test.45619894 |
| /workspace/coverage/default/3.prim_present_test.1776967674 |
| /workspace/coverage/default/30.prim_present_test.36253866 |
| /workspace/coverage/default/31.prim_present_test.2976130580 |
| /workspace/coverage/default/32.prim_present_test.2085351943 |
| /workspace/coverage/default/33.prim_present_test.1061947633 |
| /workspace/coverage/default/34.prim_present_test.2820304709 |
| /workspace/coverage/default/35.prim_present_test.2639023759 |
| /workspace/coverage/default/36.prim_present_test.2314407379 |
| /workspace/coverage/default/37.prim_present_test.983717486 |
| /workspace/coverage/default/38.prim_present_test.3042678834 |
| /workspace/coverage/default/39.prim_present_test.233198752 |
| /workspace/coverage/default/4.prim_present_test.890051853 |
| /workspace/coverage/default/40.prim_present_test.3770314179 |
| /workspace/coverage/default/41.prim_present_test.2149361749 |
| /workspace/coverage/default/42.prim_present_test.3370291189 |
| /workspace/coverage/default/43.prim_present_test.2884214026 |
| /workspace/coverage/default/44.prim_present_test.3505419018 |
| /workspace/coverage/default/45.prim_present_test.2485903955 |
| /workspace/coverage/default/46.prim_present_test.1937591183 |
| /workspace/coverage/default/47.prim_present_test.2334227883 |
| /workspace/coverage/default/48.prim_present_test.3743717641 |
| /workspace/coverage/default/49.prim_present_test.3792426365 |
| /workspace/coverage/default/5.prim_present_test.3080262866 |
| /workspace/coverage/default/6.prim_present_test.3816363002 |
| /workspace/coverage/default/7.prim_present_test.1991150088 |
| /workspace/coverage/default/8.prim_present_test.1953114793 |
| /workspace/coverage/default/9.prim_present_test.3461032548 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_present_test.2538727847 | Jul 24 04:21:14 PM PDT 24 | Jul 24 04:21:40 PM PDT 24 | 4510500000 ps | ||
| T2 | /workspace/coverage/default/18.prim_present_test.1819587494 | Jul 24 04:20:19 PM PDT 24 | Jul 24 04:21:22 PM PDT 24 | 8967060000 ps | ||
| T3 | /workspace/coverage/default/20.prim_present_test.2278113938 | Jul 24 04:21:26 PM PDT 24 | Jul 24 04:22:02 PM PDT 24 | 6480860000 ps | ||
| T4 | /workspace/coverage/default/37.prim_present_test.983717486 | Jul 24 04:22:04 PM PDT 24 | Jul 24 04:22:40 PM PDT 24 | 4654340000 ps | ||
| T5 | /workspace/coverage/default/41.prim_present_test.2149361749 | Jul 24 04:25:59 PM PDT 24 | Jul 24 04:27:06 PM PDT 24 | 11860600000 ps | ||
| T6 | /workspace/coverage/default/11.prim_present_test.3602342412 | Jul 24 04:21:25 PM PDT 24 | Jul 24 04:22:35 PM PDT 24 | 11048400000 ps | ||
| T7 | /workspace/coverage/default/23.prim_present_test.1236886623 | Jul 24 04:20:12 PM PDT 24 | Jul 24 04:21:01 PM PDT 24 | 7193240000 ps | ||
| T8 | /workspace/coverage/default/2.prim_present_test.1842843761 | Jul 24 04:20:15 PM PDT 24 | Jul 24 04:21:35 PM PDT 24 | 11953600000 ps | ||
| T9 | /workspace/coverage/default/42.prim_present_test.3370291189 | Jul 24 04:22:20 PM PDT 24 | Jul 24 04:23:02 PM PDT 24 | 7379860000 ps | ||
| T10 | /workspace/coverage/default/45.prim_present_test.2485903955 | Jul 24 04:24:47 PM PDT 24 | Jul 24 04:25:53 PM PDT 24 | 13050380000 ps | ||
| T11 | /workspace/coverage/default/14.prim_present_test.1342090342 | Jul 24 04:20:17 PM PDT 24 | Jul 24 04:20:58 PM PDT 24 | 7547260000 ps | ||
| T12 | /workspace/coverage/default/44.prim_present_test.3505419018 | Jul 24 04:25:15 PM PDT 24 | Jul 24 04:26:37 PM PDT 24 | 12443400000 ps | ||
| T13 | /workspace/coverage/default/19.prim_present_test.3577277206 | Jul 24 04:20:52 PM PDT 24 | Jul 24 04:21:25 PM PDT 24 | 5001540000 ps | ||
| T14 | /workspace/coverage/default/34.prim_present_test.2820304709 | Jul 24 04:20:52 PM PDT 24 | Jul 24 04:21:32 PM PDT 24 | 5954480000 ps | ||
| T15 | /workspace/coverage/default/31.prim_present_test.2976130580 | Jul 24 04:25:45 PM PDT 24 | Jul 24 04:26:06 PM PDT 24 | 3461460000 ps | ||
| T16 | /workspace/coverage/default/40.prim_present_test.3770314179 | Jul 24 04:24:39 PM PDT 24 | Jul 24 04:26:32 PM PDT 24 | 14361060000 ps | ||
| T17 | /workspace/coverage/default/6.prim_present_test.3816363002 | Jul 24 04:20:10 PM PDT 24 | Jul 24 04:21:21 PM PDT 24 | 11427220000 ps | ||
| T18 | /workspace/coverage/default/27.prim_present_test.2452585318 | Jul 24 04:20:53 PM PDT 24 | Jul 24 04:21:22 PM PDT 24 | 4222820000 ps | ||
| T19 | /workspace/coverage/default/48.prim_present_test.3743717641 | Jul 24 04:25:02 PM PDT 24 | Jul 24 04:26:02 PM PDT 24 | 8857320000 ps | ||
| T20 | /workspace/coverage/default/30.prim_present_test.36253866 | Jul 24 04:25:39 PM PDT 24 | Jul 24 04:26:17 PM PDT 24 | 5783360000 ps | ||
| T21 | /workspace/coverage/default/32.prim_present_test.2085351943 | Jul 24 04:21:03 PM PDT 24 | Jul 24 04:22:19 PM PDT 24 | 11813480000 ps | ||
| T22 | /workspace/coverage/default/47.prim_present_test.2334227883 | Jul 24 04:22:04 PM PDT 24 | Jul 24 04:23:47 PM PDT 24 | 13888620000 ps | ||
| T23 | /workspace/coverage/default/17.prim_present_test.2594380563 | Jul 24 04:21:25 PM PDT 24 | Jul 24 04:22:29 PM PDT 24 | 11176120000 ps | ||
| T24 | /workspace/coverage/default/43.prim_present_test.2884214026 | Jul 24 04:23:48 PM PDT 24 | Jul 24 04:24:19 PM PDT 24 | 5562640000 ps | ||
| T25 | /workspace/coverage/default/33.prim_present_test.1061947633 | Jul 24 04:21:17 PM PDT 24 | Jul 24 04:22:05 PM PDT 24 | 7041340000 ps | ||
| T26 | /workspace/coverage/default/12.prim_present_test.1021608764 | Jul 24 04:21:26 PM PDT 24 | Jul 24 04:21:52 PM PDT 24 | 3944440000 ps | ||
| T27 | /workspace/coverage/default/1.prim_present_test.3344411536 | Jul 24 04:20:12 PM PDT 24 | Jul 24 04:21:26 PM PDT 24 | 12007540000 ps | ||
| T28 | /workspace/coverage/default/13.prim_present_test.3426103801 | Jul 24 04:21:14 PM PDT 24 | Jul 24 04:22:36 PM PDT 24 | 14822340000 ps | ||
| T29 | /workspace/coverage/default/9.prim_present_test.3461032548 | Jul 24 04:20:11 PM PDT 24 | Jul 24 04:21:11 PM PDT 24 | 9011080000 ps | ||
| T30 | /workspace/coverage/default/39.prim_present_test.233198752 | Jul 24 04:22:04 PM PDT 24 | Jul 24 04:22:57 PM PDT 24 | 7718380000 ps | ||
| T31 | /workspace/coverage/default/38.prim_present_test.3042678834 | Jul 24 04:26:00 PM PDT 24 | Jul 24 04:27:15 PM PDT 24 | 13870640000 ps | ||
| T32 | /workspace/coverage/default/35.prim_present_test.2639023759 | Jul 24 04:25:46 PM PDT 24 | Jul 24 04:26:36 PM PDT 24 | 8822600000 ps | ||
| T33 | /workspace/coverage/default/24.prim_present_test.3871935407 | Jul 24 04:20:14 PM PDT 24 | Jul 24 04:20:35 PM PDT 24 | 4001480000 ps | ||
| T34 | /workspace/coverage/default/28.prim_present_test.4140128052 | Jul 24 04:23:28 PM PDT 24 | Jul 24 04:24:44 PM PDT 24 | 10856820000 ps | ||
| T35 | /workspace/coverage/default/5.prim_present_test.3080262866 | Jul 24 04:20:11 PM PDT 24 | Jul 24 04:20:53 PM PDT 24 | 6215500000 ps | ||
| T36 | /workspace/coverage/default/29.prim_present_test.45619894 | Jul 24 04:21:07 PM PDT 24 | Jul 24 04:22:02 PM PDT 24 | 8649000000 ps | ||
| T37 | /workspace/coverage/default/15.prim_present_test.3193950204 | Jul 24 04:21:16 PM PDT 24 | Jul 24 04:21:45 PM PDT 24 | 4646900000 ps | ||
| T38 | /workspace/coverage/default/0.prim_present_test.2078638065 | Jul 24 04:20:13 PM PDT 24 | Jul 24 04:20:33 PM PDT 24 | 3624520000 ps | ||
| T39 | /workspace/coverage/default/25.prim_present_test.459222494 | Jul 24 04:25:39 PM PDT 24 | Jul 24 04:26:32 PM PDT 24 | 7652660000 ps | ||
| T40 | /workspace/coverage/default/3.prim_present_test.1776967674 | Jul 24 04:20:17 PM PDT 24 | Jul 24 04:20:41 PM PDT 24 | 3617080000 ps | ||
| T41 | /workspace/coverage/default/22.prim_present_test.3359179234 | Jul 24 04:21:03 PM PDT 24 | Jul 24 04:22:19 PM PDT 24 | 11588420000 ps | ||
| T42 | /workspace/coverage/default/4.prim_present_test.890051853 | Jul 24 04:20:01 PM PDT 24 | Jul 24 04:20:26 PM PDT 24 | 4062860000 ps | ||
| T43 | /workspace/coverage/default/8.prim_present_test.1953114793 | Jul 24 04:20:11 PM PDT 24 | Jul 24 04:21:32 PM PDT 24 | 12772000000 ps | ||
| T44 | /workspace/coverage/default/21.prim_present_test.3297374139 | Jul 24 04:21:26 PM PDT 24 | Jul 24 04:22:40 PM PDT 24 | 13292180000 ps | ||
| T45 | /workspace/coverage/default/16.prim_present_test.2157567172 | Jul 24 04:21:25 PM PDT 24 | Jul 24 04:22:45 PM PDT 24 | 12825940000 ps | ||
| T46 | /workspace/coverage/default/7.prim_present_test.1991150088 | Jul 24 04:20:13 PM PDT 24 | Jul 24 04:20:59 PM PDT 24 | 8082320000 ps | ||
| T47 | /workspace/coverage/default/36.prim_present_test.2314407379 | Jul 24 04:22:04 PM PDT 24 | Jul 24 04:23:11 PM PDT 24 | 8652720000 ps | ||
| T48 | /workspace/coverage/default/49.prim_present_test.3792426365 | Jul 24 04:22:28 PM PDT 24 | Jul 24 04:23:50 PM PDT 24 | 11386300000 ps | ||
| T49 | /workspace/coverage/default/26.prim_present_test.1365849873 | Jul 24 04:21:18 PM PDT 24 | Jul 24 04:23:15 PM PDT 24 | 15466520000 ps | ||
| T50 | /workspace/coverage/default/46.prim_present_test.1937591183 | Jul 24 04:25:02 PM PDT 24 | Jul 24 04:25:37 PM PDT 24 | 4999060000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.2538727847 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4510500000 ps |
| CPU time | 13.96 seconds |
| Started | Jul 24 04:21:14 PM PDT 24 |
| Finished | Jul 24 04:21:40 PM PDT 24 |
| Peak memory | 144500 kb |
| Host | smart-2ff454c3-53e1-4881-869b-5c43defd134c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538727847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2538727847 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2078638065 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3624520000 ps |
| CPU time | 11.2 seconds |
| Started | Jul 24 04:20:13 PM PDT 24 |
| Finished | Jul 24 04:20:33 PM PDT 24 |
| Peak memory | 143888 kb |
| Host | smart-03e009fd-0ae5-4824-ab09-13af691fb83d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078638065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2078638065 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3344411536 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12007540000 ps |
| CPU time | 39.86 seconds |
| Started | Jul 24 04:20:12 PM PDT 24 |
| Finished | Jul 24 04:21:26 PM PDT 24 |
| Peak memory | 144808 kb |
| Host | smart-ecd666e8-3fb0-489b-8a90-09d76102b5d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3344411536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3344411536 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3602342412 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11048400000 ps |
| CPU time | 37.66 seconds |
| Started | Jul 24 04:21:25 PM PDT 24 |
| Finished | Jul 24 04:22:35 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-a14179a1-85b4-47b4-b8b9-d1bafe0ccbdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602342412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3602342412 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1021608764 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3944440000 ps |
| CPU time | 13.91 seconds |
| Started | Jul 24 04:21:26 PM PDT 24 |
| Finished | Jul 24 04:21:52 PM PDT 24 |
| Peak memory | 144548 kb |
| Host | smart-a168ba26-21b4-4000-8c71-0d197ff03ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021608764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1021608764 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3426103801 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14822340000 ps |
| CPU time | 45.43 seconds |
| Started | Jul 24 04:21:14 PM PDT 24 |
| Finished | Jul 24 04:22:36 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-e288e3cc-f0a0-4f20-b834-b4c6d998652f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426103801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3426103801 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1342090342 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7547260000 ps |
| CPU time | 22.55 seconds |
| Started | Jul 24 04:20:17 PM PDT 24 |
| Finished | Jul 24 04:20:58 PM PDT 24 |
| Peak memory | 144580 kb |
| Host | smart-190ef255-39e1-4afc-94be-0643683791d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342090342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1342090342 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3193950204 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4646900000 ps |
| CPU time | 15.77 seconds |
| Started | Jul 24 04:21:16 PM PDT 24 |
| Finished | Jul 24 04:21:45 PM PDT 24 |
| Peak memory | 144592 kb |
| Host | smart-98441a2d-912e-4b3a-9ec9-c653081c076b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193950204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3193950204 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2157567172 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12825940000 ps |
| CPU time | 43.64 seconds |
| Started | Jul 24 04:21:25 PM PDT 24 |
| Finished | Jul 24 04:22:45 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-090a1fa6-ce19-47d7-a789-19a53478758a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157567172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2157567172 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2594380563 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11176120000 ps |
| CPU time | 34.75 seconds |
| Started | Jul 24 04:21:25 PM PDT 24 |
| Finished | Jul 24 04:22:29 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-b3e26304-8854-4eae-a2af-53402e3bbed9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594380563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2594380563 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1819587494 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8967060000 ps |
| CPU time | 33.09 seconds |
| Started | Jul 24 04:20:19 PM PDT 24 |
| Finished | Jul 24 04:21:22 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-de794598-b48e-48df-bdb2-cd9270df534b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1819587494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1819587494 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3577277206 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5001540000 ps |
| CPU time | 17.99 seconds |
| Started | Jul 24 04:20:52 PM PDT 24 |
| Finished | Jul 24 04:21:25 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-e7311098-2a45-4b60-9df6-b898726b4baf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577277206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3577277206 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1842843761 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11953600000 ps |
| CPU time | 42.66 seconds |
| Started | Jul 24 04:20:15 PM PDT 24 |
| Finished | Jul 24 04:21:35 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-a4b367b4-bb4d-4253-9036-322aa5df8db0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842843761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1842843761 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2278113938 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6480860000 ps |
| CPU time | 19.74 seconds |
| Started | Jul 24 04:21:26 PM PDT 24 |
| Finished | Jul 24 04:22:02 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-83ca60a9-9da7-4ff9-b934-6fb9dfb8b2de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278113938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2278113938 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3297374139 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13292180000 ps |
| CPU time | 40.74 seconds |
| Started | Jul 24 04:21:26 PM PDT 24 |
| Finished | Jul 24 04:22:40 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-32386dc4-a43b-46e5-8416-42c5d5633713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297374139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3297374139 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3359179234 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11588420000 ps |
| CPU time | 40.9 seconds |
| Started | Jul 24 04:21:03 PM PDT 24 |
| Finished | Jul 24 04:22:19 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-63d0b702-b1f8-4ed7-8c23-3572750f9e5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3359179234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3359179234 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1236886623 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7193240000 ps |
| CPU time | 26.21 seconds |
| Started | Jul 24 04:20:12 PM PDT 24 |
| Finished | Jul 24 04:21:01 PM PDT 24 |
| Peak memory | 144808 kb |
| Host | smart-70676b86-2e2e-420a-a096-49b15404fd61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236886623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1236886623 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3871935407 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4001480000 ps |
| CPU time | 12 seconds |
| Started | Jul 24 04:20:14 PM PDT 24 |
| Finished | Jul 24 04:20:35 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-c27e86b0-126c-432b-8e06-8a5dd25e5038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871935407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3871935407 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.459222494 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7652660000 ps |
| CPU time | 28.12 seconds |
| Started | Jul 24 04:25:39 PM PDT 24 |
| Finished | Jul 24 04:26:32 PM PDT 24 |
| Peak memory | 143592 kb |
| Host | smart-15019137-c7c0-4b14-8802-8aad45b90ab7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459222494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.459222494 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1365849873 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15466520000 ps |
| CPU time | 60.81 seconds |
| Started | Jul 24 04:21:18 PM PDT 24 |
| Finished | Jul 24 04:23:15 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-fd53b56c-8770-4832-a4bd-8a52c8f321e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365849873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1365849873 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2452585318 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4222820000 ps |
| CPU time | 15.88 seconds |
| Started | Jul 24 04:20:53 PM PDT 24 |
| Finished | Jul 24 04:21:22 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-5a1c1003-3da8-4e9d-b6f1-febf8b6fef62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452585318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2452585318 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.4140128052 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10856820000 ps |
| CPU time | 39.79 seconds |
| Started | Jul 24 04:23:28 PM PDT 24 |
| Finished | Jul 24 04:24:44 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-4d0a1e03-f0bb-41b6-a49e-5f033357b945 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140128052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.4140128052 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.45619894 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8649000000 ps |
| CPU time | 29.1 seconds |
| Started | Jul 24 04:21:07 PM PDT 24 |
| Finished | Jul 24 04:22:02 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-ba0544ec-b971-4eff-8f78-e30ef37295e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45619894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.45619894 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1776967674 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3617080000 ps |
| CPU time | 13.01 seconds |
| Started | Jul 24 04:20:17 PM PDT 24 |
| Finished | Jul 24 04:20:41 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-4a5f2d6c-5d79-42f9-9337-c064435cf876 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776967674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1776967674 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.36253866 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5783360000 ps |
| CPU time | 20.16 seconds |
| Started | Jul 24 04:25:39 PM PDT 24 |
| Finished | Jul 24 04:26:17 PM PDT 24 |
| Peak memory | 143788 kb |
| Host | smart-a026dca8-56fd-4de3-8e2d-65e29920daf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36253866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.36253866 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2976130580 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3461460000 ps |
| CPU time | 11.51 seconds |
| Started | Jul 24 04:25:45 PM PDT 24 |
| Finished | Jul 24 04:26:06 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-4ce10220-5e21-475f-8696-8e641e286d35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976130580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2976130580 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2085351943 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11813480000 ps |
| CPU time | 41.01 seconds |
| Started | Jul 24 04:21:03 PM PDT 24 |
| Finished | Jul 24 04:22:19 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-2531dd5c-e786-4dbb-afe8-8ea745f40f0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085351943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2085351943 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1061947633 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7041340000 ps |
| CPU time | 25.84 seconds |
| Started | Jul 24 04:21:17 PM PDT 24 |
| Finished | Jul 24 04:22:05 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-45af5787-5d61-4c68-a3f7-6f9de3484502 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061947633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1061947633 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2820304709 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5954480000 ps |
| CPU time | 21.35 seconds |
| Started | Jul 24 04:20:52 PM PDT 24 |
| Finished | Jul 24 04:21:32 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-89ace28f-4717-4846-ac3c-a77f451e8b44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820304709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2820304709 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2639023759 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8822600000 ps |
| CPU time | 27.27 seconds |
| Started | Jul 24 04:25:46 PM PDT 24 |
| Finished | Jul 24 04:26:36 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-aa230c69-2264-449e-8623-09b912dc5901 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639023759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2639023759 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2314407379 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8652720000 ps |
| CPU time | 34.96 seconds |
| Started | Jul 24 04:22:04 PM PDT 24 |
| Finished | Jul 24 04:23:11 PM PDT 24 |
| Peak memory | 144844 kb |
| Host | smart-785f0e36-570d-4a7e-8f1a-910e7c2ae27f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314407379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2314407379 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.983717486 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4654340000 ps |
| CPU time | 18.7 seconds |
| Started | Jul 24 04:22:04 PM PDT 24 |
| Finished | Jul 24 04:22:40 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-9cf78c53-22dc-42f6-9981-f4bb297b35c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983717486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.983717486 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3042678834 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13870640000 ps |
| CPU time | 41.39 seconds |
| Started | Jul 24 04:26:00 PM PDT 24 |
| Finished | Jul 24 04:27:15 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-7684ee3a-36f3-4b3d-a1df-0c30220d48ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3042678834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3042678834 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.233198752 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7718380000 ps |
| CPU time | 27.95 seconds |
| Started | Jul 24 04:22:04 PM PDT 24 |
| Finished | Jul 24 04:22:57 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-e5fe1033-3ff7-4531-9d66-8eaf48baa01a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233198752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.233198752 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.890051853 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4062860000 ps |
| CPU time | 13.1 seconds |
| Started | Jul 24 04:20:01 PM PDT 24 |
| Finished | Jul 24 04:20:26 PM PDT 24 |
| Peak memory | 143780 kb |
| Host | smart-c650431e-86a1-4123-9ba6-ae78341cefd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890051853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.890051853 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3770314179 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 14361060000 ps |
| CPU time | 57.28 seconds |
| Started | Jul 24 04:24:39 PM PDT 24 |
| Finished | Jul 24 04:26:32 PM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-c50c1e9d-c950-4df7-99f0-158abf3ee0c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770314179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3770314179 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2149361749 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11860600000 ps |
| CPU time | 36.73 seconds |
| Started | Jul 24 04:25:59 PM PDT 24 |
| Finished | Jul 24 04:27:06 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-eedb7267-0cf1-4905-a82e-a9479799ec23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2149361749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2149361749 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3370291189 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7379860000 ps |
| CPU time | 23.55 seconds |
| Started | Jul 24 04:22:20 PM PDT 24 |
| Finished | Jul 24 04:23:02 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-25a8ec13-c9c8-4d3b-a8b0-b0efb3f36a3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370291189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3370291189 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2884214026 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5562640000 ps |
| CPU time | 17.16 seconds |
| Started | Jul 24 04:23:48 PM PDT 24 |
| Finished | Jul 24 04:24:19 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-ed6d0170-73a9-4a1b-997a-76d4a403a03a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2884214026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2884214026 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3505419018 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12443400000 ps |
| CPU time | 43.27 seconds |
| Started | Jul 24 04:25:15 PM PDT 24 |
| Finished | Jul 24 04:26:37 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-c088f29e-8e2f-4bab-bbfd-c60ebb04e27a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505419018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3505419018 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2485903955 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13050380000 ps |
| CPU time | 36.18 seconds |
| Started | Jul 24 04:24:47 PM PDT 24 |
| Finished | Jul 24 04:25:53 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-853ba54c-d2aa-4c82-9a83-a930a4eab3e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485903955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2485903955 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1937591183 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4999060000 ps |
| CPU time | 18.49 seconds |
| Started | Jul 24 04:25:02 PM PDT 24 |
| Finished | Jul 24 04:25:37 PM PDT 24 |
| Peak memory | 143724 kb |
| Host | smart-f5e65bae-da18-43ec-b03a-63e44547b61e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937591183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1937591183 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2334227883 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13888620000 ps |
| CPU time | 53.59 seconds |
| Started | Jul 24 04:22:04 PM PDT 24 |
| Finished | Jul 24 04:23:47 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-53170fdc-9fcb-401b-8f0a-fb4eeaf8d9a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334227883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2334227883 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3743717641 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8857320000 ps |
| CPU time | 31.77 seconds |
| Started | Jul 24 04:25:02 PM PDT 24 |
| Finished | Jul 24 04:26:02 PM PDT 24 |
| Peak memory | 143656 kb |
| Host | smart-c77d0eaf-a788-447c-9f18-3ccf3cab64fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743717641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3743717641 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3792426365 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11386300000 ps |
| CPU time | 42.45 seconds |
| Started | Jul 24 04:22:28 PM PDT 24 |
| Finished | Jul 24 04:23:50 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-17e3fc68-9d5b-4736-ba52-d1985c94b00f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792426365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3792426365 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3080262866 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6215500000 ps |
| CPU time | 21.89 seconds |
| Started | Jul 24 04:20:11 PM PDT 24 |
| Finished | Jul 24 04:20:53 PM PDT 24 |
| Peak memory | 143892 kb |
| Host | smart-c5b5941b-d07a-4b0a-8bb4-a9cf23563cb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3080262866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3080262866 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3816363002 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11427220000 ps |
| CPU time | 38.16 seconds |
| Started | Jul 24 04:20:10 PM PDT 24 |
| Finished | Jul 24 04:21:21 PM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-997294af-0d1c-4abb-97ea-5f430d7560fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816363002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3816363002 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1991150088 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8082320000 ps |
| CPU time | 25.25 seconds |
| Started | Jul 24 04:20:13 PM PDT 24 |
| Finished | Jul 24 04:20:59 PM PDT 24 |
| Peak memory | 144044 kb |
| Host | smart-2559f975-8e0d-47bf-8d31-415db5b6d8fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991150088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1991150088 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1953114793 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12772000000 ps |
| CPU time | 44.16 seconds |
| Started | Jul 24 04:20:11 PM PDT 24 |
| Finished | Jul 24 04:21:32 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-9e08c161-57d5-41bf-b3fd-980321c4ff63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1953114793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1953114793 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3461032548 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9011080000 ps |
| CPU time | 31.55 seconds |
| Started | Jul 24 04:20:11 PM PDT 24 |
| Finished | Jul 24 04:21:11 PM PDT 24 |
| Peak memory | 144092 kb |
| Host | smart-cc13ad0b-19e2-49f1-8b26-84fa568dc1c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461032548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3461032548 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |